mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-22 23:52:03 +00:00
cpu: add CPU driver for microblaze
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:
U-Boot-mONStR> cpu list
0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR> cpu detail
0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
ID = 0, freq = 50 MHz: L1 cache, MMU
Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Ovidiu Panait
Michal Simek
parent
9df16c5937
commit
816226d27e
5 changed files with 380 additions and 0 deletions
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@ -8,6 +8,117 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(CPU_MICROBLAZE)
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/* These key value are as per MBV field in PVR0 */
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static const struct microblaze_version_map cpu_ver_lookup[] = {
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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{"7.20.a", 0x0c},
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{"7.20.b", 0x0d},
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{"7.20.c", 0x0e},
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{"7.20.d", 0x0f},
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{"7.30.a", 0x10},
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{"7.30.b", 0x11},
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{"8.00.a", 0x12},
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{"8.00.b", 0x13},
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{"8.10.a", 0x14},
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{"8.20.a", 0x15},
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{"8.20.b", 0x16},
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{"8.30.a", 0x17},
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{"8.40.a", 0x18},
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{"8.40.b", 0x19},
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{"8.50.a", 0x1a},
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{"8.50.b", 0x1c},
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{"8.50.c", 0x1e},
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{"9.0", 0x1b},
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{"9.1", 0x1d},
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{"9.2", 0x1f},
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{"9.3", 0x20},
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{"9.4", 0x21},
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{"9.5", 0x22},
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{"9.6", 0x23},
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{"10.0", 0x24},
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{"11.0", 0x25},
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{NULL, 0},
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};
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static const struct microblaze_version_map family_string_lookup[] = {
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{"virtex2", 0x4},
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{"virtex2pro", 0x5},
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{"spartan3", 0x6},
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{"virtex4", 0x7},
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{"virtex5", 0x8},
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{"spartan3e", 0x9},
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{"spartan3a", 0xa},
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{"spartan3an", 0xb},
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{"spartan3adsp", 0xc},
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{"spartan6", 0xd},
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{"virtex6", 0xe},
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{"virtex7", 0xf},
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/* FIXME There is no key code defined for spartan2 */
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{"spartan2", 0xf0},
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{"kintex7", 0x10},
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{"artix7", 0x11},
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{"zynq7000", 0x12},
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{"UltraScale Virtex", 0x13},
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{"UltraScale Kintex", 0x14},
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{"UltraScale+ Zynq", 0x15},
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{"UltraScale+ Virtex", 0x16},
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{"UltraScale+ Kintex", 0x17},
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{"Spartan7", 0x18},
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{NULL, 0},
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};
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static const char *lookup_string(u32 code,
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const struct microblaze_version_map *entry)
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{
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for (; entry->string; ++entry)
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if (entry->code == code)
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return entry->string;
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return "(unknown)";
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}
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static const u32 lookup_code(const char *string,
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const struct microblaze_version_map *entry)
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{
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for (; entry->string; ++entry)
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if (!strcmp(entry->string, string))
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return entry->code;
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return 0;
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}
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const char *microblaze_lookup_fpga_family_string(const u32 code)
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{
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return lookup_string(code, family_string_lookup);
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}
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const char *microblaze_lookup_cpu_version_string(const u32 code)
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{
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return lookup_string(code, cpu_ver_lookup);
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}
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const u32 microblaze_lookup_fpga_family_code(const char *string)
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{
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return lookup_code(string, family_string_lookup);
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}
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const u32 microblaze_lookup_cpu_version_code(const char *string)
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{
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return lookup_code(string, cpu_ver_lookup);
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}
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#endif /* CONFIG_CPU_MICROBLAZE */
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void microblaze_early_cpuinfo_init(void)
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{
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struct microblaze_cpuinfo *ci = gd_cpuinfo();
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@ -13,6 +13,11 @@
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* @icache_line_length: Instruction cache line length in bytes.
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* @dcache_size: Size of data cache memory in bytes.
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* @dcache_line_length: Data cache line length in bytes.
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* @use_mmu: MMU support flag.
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* @cpu_freq: Cpu clock frequency in Hz.
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* @addr_size: Address bus width in bits.
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* @ver_code: Cpu version code.
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* @fpga_code: FPGA family version code.
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*/
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struct microblaze_cpuinfo {
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u32 icache_size;
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@ -20,8 +25,82 @@ struct microblaze_cpuinfo {
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u32 dcache_size;
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u32 dcache_line_length;
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#if CONFIG_IS_ENABLED(CPU_MICROBLAZE)
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u32 use_mmu;
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u32 cpu_freq;
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u32 addr_size;
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u32 ver_code;
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u32 fpga_code;
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#endif /* CONFIG_CPU_MICROBLAZE */
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};
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/**
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* struct microblaze_version_data - Maps a hex version code to a cpu/fpga name.
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*/
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struct microblaze_version_map {
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const char *string;
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const u32 code;
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};
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/**
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* microblaze_lookup_cpu_version_code() - Get hex version code for the
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* specified cpu name string.
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*
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* This function searches the cpu_ver_lookup[] array for the hex version code
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* associated with a specific CPU name. The version code is returned if a match
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* is found, otherwise 0.
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*
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* @string: cpu name string
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*
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* Return: >0 if the entry is found, 0 otherwise.
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*/
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const u32 microblaze_lookup_cpu_version_code(const char *string);
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/**
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* microblaze_lookup_fpga_family_code() - Get hex version code for the
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* specified fpga family name.
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*
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* This function searches the family_string_lookup[] array for the hex version
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* code associated with a specific fpga family name. The version code is
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* returned if a match is found, otherwise 0.
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*
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* @string: fpga family name string
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*
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* Return: >0 if the entry is found, 0 otherwise.
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*/
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const u32 microblaze_lookup_fpga_family_code(const char *string);
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/**
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* microblaze_lookup_cpu_version_string() - Get cpu name for the specified cpu
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* version code.
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*
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* This function searches the cpu_ver_lookup[] array for the cpu name string
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* associated with a specific version code. The cpu name is returned if a match
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* is found, otherwise "(unknown)".
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*
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* @code: cpu version code
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*
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* Return: Pointer to the cpu name if the entry is found, otherwise "(unknown)".
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*/
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const char *microblaze_lookup_cpu_version_string(const u32 code);
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/**
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* microblaze_lookup_fpga_family_string() - Get fpga family name for the
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* specified version code.
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*
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* This function searches the family_string_lookup[] array for the fpga family
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* name string associated with a specific version code. The fpga family name is
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* returned if a match is found, otherwise "(unknown)".
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*
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* @code: fpga family version code
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*
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* Return: Pointer to the fpga family name if the entry is found, otherwise
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* "(unknown)".
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*/
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const char *microblaze_lookup_fpga_family_string(const u32 code);
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/**
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* microblaze_early_cpuinfo_init() - Initialize cpuinfo with default values.
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*
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@ -19,3 +19,12 @@ config CPU_RISCV
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depends on CPU && RISCV
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help
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Support CPU cores for RISC-V architecture.
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config CPU_MICROBLAZE
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bool "Enable Microblaze CPU driver"
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depends on CPU && MICROBLAZE
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select EVENT
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select DM_EVENT
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select XILINX_MICROBLAZE0_PVR
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help
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Support CPU cores for Microblaze architecture.
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@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
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obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
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obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
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obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
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obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
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obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
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180
drivers/cpu/microblaze_cpu.c
Normal file
180
drivers/cpu/microblaze_cpu.c
Normal file
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@ -0,0 +1,180 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <asm/cpuinfo.h>
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#include <asm/global_data.h>
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#include <asm/pvr.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define update_cpuinfo_pvr(pvr, ci, name) \
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{ \
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u32 tmp = PVR_##name(pvr); \
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if (ci != tmp) \
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printf("PVR value for " #name " does not match static data!\n");\
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ci = tmp; \
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}
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static int microblaze_cpu_probe_all(void *ctx, struct event *event)
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{
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int ret;
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ret = cpu_probe_all();
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if (ret)
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return log_msg_ret("Microblaze cpus probe failed\n", ret);
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return 0;
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}
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EVENT_SPY(EVT_DM_POST_INIT, microblaze_cpu_probe_all);
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static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci)
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{
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u32 pvr[PVR_FULL_COUNT];
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microblaze_get_all_pvrs(pvr);
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update_cpuinfo_pvr(pvr, ci->icache_size, ICACHE_BYTE_SIZE);
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update_cpuinfo_pvr(pvr, ci->icache_line_length, ICACHE_LINE_LEN);
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update_cpuinfo_pvr(pvr, ci->dcache_size, DCACHE_BYTE_SIZE);
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update_cpuinfo_pvr(pvr, ci->dcache_line_length, DCACHE_LINE_LEN);
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update_cpuinfo_pvr(pvr, ci->use_mmu, USE_MMU);
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update_cpuinfo_pvr(pvr, ci->ver_code, VERSION);
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update_cpuinfo_pvr(pvr, ci->fpga_code, TARGET_FAMILY);
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}
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static void microblaze_set_cpuinfo_static(struct udevice *dev,
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struct microblaze_cpuinfo *ci)
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{
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const char *hw_ver = CONFIG_XILINX_MICROBLAZE0_HW_VER;
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const char *fpga_family = CONFIG_XILINX_MICROBLAZE0_FPGA_FAMILY;
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ci->icache_size = dev_read_u32_default(dev, "i-cache-size", 0);
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ci->icache_line_length = dev_read_u32_default(dev,
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"i-cache-line-size", 0);
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ci->dcache_size = dev_read_u32_default(dev, "d-cache-size", 0);
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ci->dcache_line_length = dev_read_u32_default(dev,
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"d-cache-line-size", 0);
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ci->cpu_freq = dev_read_u32_default(dev, "clock-frequency", 0);
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ci->addr_size = dev_read_u32_default(dev, "xlnx,addr-size", 32);
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ci->use_mmu = dev_read_u32_default(dev, "xlnx,use-mmu", 0);
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ci->ver_code = microblaze_lookup_cpu_version_code(hw_ver);
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ci->fpga_code = microblaze_lookup_fpga_family_code(fpga_family);
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}
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static int microblaze_cpu_probe(struct udevice *dev)
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{
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microblaze_set_cpuinfo_static(dev, gd_cpuinfo());
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if (microblaze_cpu_has_pvr_full())
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microblaze_set_cpuinfo_pvr(gd_cpuinfo());
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else
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debug("No PVR support. Using only static CPU info.\n");
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return 0;
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}
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static int microblaze_cpu_get_desc(const struct udevice *dev, char *buf,
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int size)
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{
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struct microblaze_cpuinfo *ci = gd_cpuinfo();
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const char *cpu_ver, *fpga_family;
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u32 cpu_freq_mhz;
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int ret;
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cpu_freq_mhz = ci->cpu_freq / 1000000;
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cpu_ver = microblaze_lookup_cpu_version_string(ci->ver_code);
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fpga_family = microblaze_lookup_fpga_family_string(ci->fpga_code);
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ret = snprintf(buf, size,
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"MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s",
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cpu_freq_mhz, cpu_ver, fpga_family);
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return 0;
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}
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static int microblaze_cpu_get_info(const struct udevice *dev,
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struct cpu_info *info)
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{
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struct microblaze_cpuinfo *ci = gd_cpuinfo();
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info->cpu_freq = ci->cpu_freq;
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info->address_width = ci->addr_size;
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if (ci->icache_size || ci->dcache_size)
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info->features |= BIT(CPU_FEAT_L1_CACHE);
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if (ci->use_mmu)
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info->features |= BIT(CPU_FEAT_MMU);
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return 0;
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}
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static int microblaze_cpu_get_count(const struct udevice *dev)
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{
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return 1;
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}
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static const struct cpu_ops microblaze_cpu_ops = {
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.get_desc = microblaze_cpu_get_desc,
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.get_info = microblaze_cpu_get_info,
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.get_count = microblaze_cpu_get_count,
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};
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static const struct udevice_id microblaze_cpu_ids[] = {
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{ .compatible = "xlnx,microblaze-11.0" },
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{ .compatible = "xlnx,microblaze-10.0" },
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{ .compatible = "xlnx,microblaze-9.6" },
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{ .compatible = "xlnx,microblaze-9.5" },
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{ .compatible = "xlnx,microblaze-9.4" },
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{ .compatible = "xlnx,microblaze-9.3" },
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{ .compatible = "xlnx,microblaze-9.2" },
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{ .compatible = "xlnx,microblaze-9.1" },
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{ .compatible = "xlnx,microblaze-9.0" },
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{ .compatible = "xlnx,microblaze-8.50.c" },
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{ .compatible = "xlnx,microblaze-8.50.b" },
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{ .compatible = "xlnx,microblaze-8.50.a" },
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{ .compatible = "xlnx,microblaze-8.40.b" },
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{ .compatible = "xlnx,microblaze-8.40.a" },
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{ .compatible = "xlnx,microblaze-8.30.a" },
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{ .compatible = "xlnx,microblaze-8.20.b" },
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{ .compatible = "xlnx,microblaze-8.20.a" },
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{ .compatible = "xlnx,microblaze-8.10.a" },
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{ .compatible = "xlnx,microblaze-8.00.b" },
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{ .compatible = "xlnx,microblaze-8.00.a" },
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{ .compatible = "xlnx,microblaze-7.30.b" },
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{ .compatible = "xlnx,microblaze-7.30.a" },
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{ .compatible = "xlnx,microblaze-7.20.d" },
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{ .compatible = "xlnx,microblaze-7.20.c" },
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{ .compatible = "xlnx,microblaze-7.20.b" },
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{ .compatible = "xlnx,microblaze-7.20.a" },
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{ .compatible = "xlnx,microblaze-7.10.d" },
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{ .compatible = "xlnx,microblaze-7.10.c" },
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{ .compatible = "xlnx,microblaze-7.10.b" },
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{ .compatible = "xlnx,microblaze-7.10.a" },
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{ .compatible = "xlnx,microblaze-7.00.b" },
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{ .compatible = "xlnx,microblaze-7.00.a" },
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{ .compatible = "xlnx,microblaze-6.00.b" },
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{ .compatible = "xlnx,microblaze-6.00.a" },
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{ .compatible = "xlnx,microblaze-5.00.c" },
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{ .compatible = "xlnx,microblaze-5.00.b" },
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{ .compatible = "xlnx,microblaze-5.00.a" },
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{ }
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};
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U_BOOT_DRIVER(microblaze_cpu) = {
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.name = "microblaze_cpu",
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.id = UCLASS_CPU,
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.of_match = microblaze_cpu_ids,
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.probe = microblaze_cpu_probe,
|
||||
.ops = µblaze_cpu_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
Loading…
Reference in a new issue