Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- mvebu: Armada 32bit: Cache setup fixes (Pali)
- cmd: mvebu/bubt: Misc enhancements (Pali)
- kirkwood: Add CONFIG_SUPPORT_PASSING_ATAGS (Tony)
- board: turris: Misc improvements (Pali)
- tools: kwboot: Change KWBOOT_MSG_RSP_TIMEO_AXP to 10ms (Stefan)
- tools: termios_linux.h: Fix compilation on non-glibc systems (Pali)

arch/arm/include/asm/pl310.h

@@ -7,13 +7,12 @@
 #ifndef _PL310_H_
 #define _PL310_H_
 
-#include <linux/types.h>
-
 /* Register bit fields */
 #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
 #define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
 #define L2X0_STNDBY_MODE_EN			(1 << 0)
 #define L2X0_CTRL_EN				1
+#define L2X0_CTRL_OFF				0x100
 
 #define L310_SHARED_ATT_OVERRIDE_ENABLE		(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
@@ -27,6 +26,10 @@
 #define L2X0_CACHE_ID_RTL_MASK          0x3f
 #define L2X0_CACHE_ID_RTL_R3P2          0x8
 
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
 struct pl310_regs {
 	u32 pl310_cache_id;
 	u32 pl310_cache_type;
@@ -87,3 +90,5 @@ void pl310_inval_range(u32 start, u32 end);
 void pl310_clean_inval_range(u32 start, u32 end);
 
 #endif
+
+#endif

arch/arm/mach-kirkwood/cpu.c

@@ -52,7 +52,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
 	return (0x0000ffff & j);
 }
 
-static struct mbus_win windows[] = {
+static const struct mbus_win windows[] = {
 	/* Window 0: PCIE MEM address space */
 	{ KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE,
 	  KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },

arch/arm/mach-kirkwood/include/mach/cpu.h

@@ -150,7 +150,7 @@ struct kwgpio_registers {
 unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_mbus_probe(const struct mbus_win windows[], int count);
 void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 		unsigned int gpp0_oe, unsigned int gpp1_oe);
 int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,

arch/arm/mach-mvebu/cpu.c

@@ -20,7 +20,7 @@
 #define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
 #define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
 
-static struct mbus_win windows[] = {
+static const struct mbus_win windows[] = {
 	/* SPI */
 	{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
 	  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
@@ -445,19 +445,6 @@ static void setup_usb_phys(void)
  */
 int arch_cpu_init(void)
 {
-	struct pl310_regs *const pl310 =
-		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
-	if (IS_ENABLED(CONFIG_ARMADA_38X)) {
-		/*
-		 * To fully release / unlock this area from cache, we need
-		 * to flush all caches and disable the L2 cache.
-		 */
-		icache_disable();
-		dcache_disable();
-		clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-	}
-
 	/*
 	 * We need to call mvebu_mbus_probe() before calling
 	 * update_sdram_window_sizes() as it disables all previously
@@ -663,7 +650,7 @@ void enable_caches(void)
 	 * ethernet driver (mvpp2). So lets keep the d-cache disabled
 	 * until this is solved.
 	 */
-	if (IS_ENABLED(CONFIG_ARMADA_375)) {
+	if (!IS_ENABLED(CONFIG_ARMADA_375)) {
 		/* Enable D-cache. I-cache is already enabled in start.S */
 		dcache_enable();
 	}
@@ -671,12 +658,20 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
-		struct pl310_regs *const pl310 =
-			(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-		u32 u;
+	struct pl310_regs *const pl310 =
+		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-		/* The L2 cache is already disabled at this point */
+	/* The L2 cache is already disabled at this point */
+
+	/*
+	 * For now L2 cache will be enabled only for Armada XP and Armada 38x.
+	 * It can be enabled also for other SoCs after testing that it works fine.
+	 */
+	if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X))
+		return;
+
+	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
+		u32 u;
 
 		/*
 		 * For Aurora cache in no outer mode, enable via the CP15
@@ -687,10 +682,10 @@ void v7_outer_cache_enable(void)
 		asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
 
 		isb();
-
-		/* Enable the L2 cache */
-		setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 	}
+
+	/* Enable the L2 cache */
+	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
 void v7_outer_cache_disable(void)

arch/arm/mach-mvebu/include/mach/cpu.h

@@ -128,7 +128,7 @@ struct sar_freq_modes {
 unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_mbus_probe(const struct mbus_win windows[], int count);
 u32 mvebu_get_nand_clock(void);
 
 void __noreturn return_to_bootrom(void);

arch/arm/mach-mvebu/lowlevel.S

@@ -2,6 +2,8 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/pl310.h>
 
 ENTRY(arch_very_early_init)
 #ifdef CONFIG_ARMADA_38X
@@ -10,10 +12,36 @@ ENTRY(arch_very_early_init)
 	 * register address on Armada 38x. Without this the SDRAM
 	 * located at >= 0x4000.0000 is also not accessible, as its
 	 * still locked to cache.
+	 *
+	 * So to fully release / unlock this area from cache, we need
+	 * to first flush all caches, then disable the MMU and
+	 * disable the L2 cache.
 	 */
+
+	/* Invalidate L1 I/D */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
+	mcr	p15, 0, r0, c7, c10, 4	@ DSB
+	mcr	p15, 0, r0, c7, c5, 4	@ ISB
+
+	/* Disable MMU */
 	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, #1
+	bic	r0, #CR_M
 	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Disable L2 cache
+	 *
+	 * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
+	 *       but CONFIG_SYS_PL310_BASE is already calculated from base
+	 *       address SOC_REGS_PHY_BASE.
+	 */
+	ldr	r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+	ldr	r0, [r1, #L2X0_CTRL_OFF]
+	bic	r0, #L2X0_CTRL_EN
+	str	r0, [r1, #L2X0_CTRL_OFF]
 #endif
 
 	/* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */

arch/arm/mach-mvebu/mbus.c

@@ -469,7 +469,7 @@ int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr)
 	return 0;
 }
 
-int mvebu_mbus_probe(struct mbus_win windows[], int count)
+int mvebu_mbus_probe(const struct mbus_win windows[], int count)
 {
 	int win;
 	int ret;

arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c

@@ -105,7 +105,7 @@ struct serdes_unit_data {
 	u8 serdes_unit_num;
 };
 
-static struct serdes_unit_data serdes_type_to_unit_info[] = {
+static const struct serdes_unit_data serdes_type_to_unit_info[] = {
 	{PEX_UNIT_ID, 0,},
 	{PEX_UNIT_ID, 1,},
 	{PEX_UNIT_ID, 2,},

arch/arm/mach-mvebu/system-controller.c

@@ -86,7 +86,7 @@ static const struct udevice_id mvebu_reset_of_match[] = {
 	{ },
 };
 
-static struct reset_ops mvebu_reset_ops = {
+static const struct reset_ops mvebu_reset_ops = {
 	.of_xlate = mvebu_reset_of_xlate,
 	.request = mvebu_reset_request,
 	.rfree = mvebu_reset_free,

board/CZ.NIC/turris_atsha_otp.c

@@ -93,30 +93,57 @@ int turris_atsha_otp_init_mac_addresses(int first_idx)
 	return 0;
 }
 
-int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num)
+int turris_atsha_otp_init_serial_number(void)
+{
+	char serial[17];
+	int ret;
+
+	ret = turris_atsha_otp_get_serial_number(serial);
+	if (ret)
+		return ret;
+
+	if (!env_get("serial#"))
+		return -1;
+
+	return 0;
+}
+
+int turris_atsha_otp_get_serial_number(char serial[17])
 {
 	struct udevice *dev = get_atsha204a_dev();
+	u32 version_num, serial_num;
+	const char *serial_env;
 	int ret;
 
 	if (!dev)
 		return -1;
 
+	serial_env = env_get("serial#");
+	if (serial_env && strlen(serial_env) == 16) {
+		memcpy(serial, serial_env, 17);
+		return 0;
+	}
+
 	ret = atsha204a_wakeup(dev);
 	if (ret)
 		return ret;
 
 	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 			     TURRIS_ATSHA_OTP_VERSION,
-			     (u8 *)version_num);
+			     (u8 *)&version_num);
 	if (ret)
 		return ret;
 
 	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 			     TURRIS_ATSHA_OTP_SERIAL,
-			     (u8 *)serial_num);
+			     (u8 *)&serial_num);
 	if (ret)
 		return ret;
 
 	atsha204a_sleep(dev);
+
+	sprintf(serial, "%08X%08X", be32_to_cpu(version_num), be32_to_cpu(serial_num));
+	env_set("serial#", serial);
+
 	return 0;
 }

board/CZ.NIC/turris_atsha_otp.h

@@ -4,6 +4,7 @@
 #define TURRIS_ATSHA_OTP_H
 
 int turris_atsha_otp_init_mac_addresses(int first_idx);
-int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num);
+int turris_atsha_otp_init_serial_number(void);
+int turris_atsha_otp_get_serial_number(char serial[17]);
 
 #endif

board/CZ.NIC/turris_mox/turris_mox.c

@@ -23,6 +23,7 @@
 #include <linux/string.h>
 #include <miiphy.h>
 #include <spi.h>
+#include <spi_flash.h>
 
 #include "mox_sp.h"
 
@@ -339,6 +340,51 @@ static int get_reset_gpio(struct gpio_desc *reset_gpio)
 	return 0;
 }
 
+/* Load default system DTB binary to $fdr_addr */
+static void load_spi_dtb(void)
+{
+	const char *const env_name[1] = { "fdt_addr" };
+	unsigned long size, offset;
+	struct udevice *spi_dev;
+	struct spi_flash *flash;
+	const char *addr_str;
+	unsigned long addr;
+	void *buf;
+
+	addr_str = env_get(env_name[0]);
+	if (!addr_str) {
+		env_set_default_vars(1, (char * const *)env_name, 0);
+		addr_str = env_get(env_name[0]);
+	}
+
+	if (!addr_str)
+		return;
+
+	addr = hextoul(addr_str, NULL);
+	if (!addr)
+		return;
+
+	spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, &spi_dev);
+	flash = dev_get_uclass_priv(spi_dev);
+	if (!flash)
+		return;
+
+	/*
+	 * SPI NOR "dtb" partition offset & size hardcoded for now because the
+	 * mtd subsystem does not offer finding the partition yet and we do not
+	 * want to reimplement OF partition parser here.
+	 */
+	offset = 0x7f0000;
+	size = 0x10000;
+
+	buf = map_physmem(addr, size, MAP_WRBACK);
+	if (!buf)
+		return;
+
+	spi_flash_read(flash, offset, size, buf);
+	unmap_physmem(buf, size);
+}
+
 int misc_init_r(void)
 {
 	u8 mac[2][6];
@@ -358,6 +404,8 @@ int misc_init_r(void)
 			eth_env_set_enetaddr_by_index("eth", i, mac[i]);
 	}
 
+	load_spi_dtb();
+
 	return 0;
 }
 
@@ -440,8 +488,9 @@ static void handle_reset_button(void)
 	env_set_default_vars(1, (char * const *)vars, 0);
 
 	if (read_reset_button()) {
-		const char * const vars[2] = {
+		const char * const vars[3] = {
 			"bootcmd",
+			"bootdelay",
 			"distro_bootcmd",
 		};
 
@@ -449,7 +498,7 @@ static void handle_reset_button(void)
 		 * Set the above envs to their default values, in case the user
 		 * managed to break them.
 		 */
-		env_set_default_vars(2, (char * const *)vars, 0);
+		env_set_default_vars(3, (char * const *)vars, 0);
 
 		/* Ensure bootcmd_rescue is used by distroboot */
 		env_set("boot_targets", "rescue");

board/CZ.NIC/turris_omnia/turris_omnia.c

@@ -549,8 +549,9 @@ static void handle_reset_button(void)
 	env_set_ulong("omnia_reset", reset_status);
 
 	if (reset_status) {
-		const char * const vars[2] = {
+		const char * const vars[3] = {
 			"bootcmd",
+			"bootdelay",
 			"distro_bootcmd",
 		};
 
@@ -558,7 +559,7 @@ static void handle_reset_button(void)
 		 * Set the above envs to their default values, in case the user
 		 * managed to break them.
 		 */
-		env_set_default_vars(2, (char * const *)vars, 0);
+		env_set_default_vars(3, (char * const *)vars, 0);
 
 		/* Ensure bootcmd_rescue is used by distroboot */
 		env_set("boot_targets", "rescue");
@@ -963,19 +964,15 @@ int board_late_init(void)
 
 int show_board_info(void)
 {
-	u32 version_num, serial_num;
+	char serial[17];
 	int err;
 
-	err = turris_atsha_otp_get_serial_number(&version_num, &serial_num);
+	err = turris_atsha_otp_get_serial_number(serial);
 	printf("Model: Turris Omnia\n");
 	printf("  MCU type: %s\n", omnia_get_mcu_type());
 	printf("  MCU version: %s\n", omnia_get_mcu_version());
 	printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
-	if (err)
-		printf("  Serial Number: unknown\n");
-	else
-		printf("  Serial Number: %08X%08X\n", be32_to_cpu(version_num),
-		       be32_to_cpu(serial_num));
+	printf("  Serial Number: %s\n", !err ? serial : "unknown");
 
 	return 0;
 }
@@ -983,6 +980,7 @@ int show_board_info(void)
 int misc_init_r(void)
 {
 	turris_atsha_otp_init_mac_addresses(1);
+	turris_atsha_otp_init_serial_number();
 	return 0;
 }
 

board/Marvell/mvebu_armada-37xx/board.c

@@ -132,6 +132,8 @@ int board_late_init(void)
 		dev = mmc_dev->dev;
 		device_remove(dev, DM_REMOVE_NORMAL);
 		device_unbind(dev);
+		if (of_live_active())
+			ofnode_set_enabled(dev_ofnode(dev), false);
 	}
 
 	/* Ensure that 'env default -a' set correct value to $fdtfile */

cmd/mvebu/Kconfig

@@ -5,6 +5,7 @@ config CMD_MVEBU_BUBT
 	bool "bubt"
 	select SHA256 if ARMADA_3700
 	select SHA512 if ARMADA_3700
+	select MVEBU_EFUSE if ARMADA_38X || ARMADA_3700
 	help
 	  bubt - Burn a u-boot image to flash
 	  For details about bubt command please see the documentation

cmd/mvebu/bubt.c

@@ -13,6 +13,8 @@
 #include <vsprintf.h>
 #include <errno.h>
 #include <dm.h>
+#include <fuse.h>
+#include <mach/efuse.h>
 
 #include <spi_flash.h>
 #include <spi.h>
@@ -121,6 +123,17 @@ struct a38x_main_hdr_v1 {
 	u8  checksum;              /* 0x1F      */
 };
 
+/*
+ * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x)
+ */
+struct a38x_opt_hdr_v1 {
+	u8	headertype;
+	u8	headersz_msb;
+	u16	headersz_lsb;
+	u8	data[0];
+};
+#define A38X_OPT_HDR_V1_SECURE_TYPE	0x1
+
 struct a38x_boot_mode {
 	unsigned int id;
 	const char *name;
@@ -688,9 +701,25 @@ static uint8_t image_checksum8(const void *start, size_t len)
 	return csum;
 }
 
+static uint32_t image_checksum32(const void *start, size_t len)
+{
+	u32 csum = 0;
+	const u32 *p = start;
+
+	while (len) {
+		csum += *p;
+		++p;
+		len -= sizeof(u32);
+	}
+
+	return csum;
+}
+
 static int check_image_header(void)
 {
 	u8 checksum;
+	u32 checksum32, exp_checksum32;
+	u32 offset, size;
 	const struct a38x_main_hdr_v1 *hdr =
 		(struct a38x_main_hdr_v1 *)get_load_addr();
 	const size_t image_size = a38x_header_size(hdr);
@@ -701,14 +730,74 @@ static int check_image_header(void)
 	checksum = image_checksum8(hdr, image_size);
 	checksum -= hdr->checksum;
 	if (checksum != hdr->checksum) {
-		printf("Error: Bad A38x image checksum. 0x%x != 0x%x\n",
+		printf("Error: Bad A38x image header checksum. 0x%x != 0x%x\n",
 		       checksum, hdr->checksum);
 		return -ENOEXEC;
 	}
 
+	offset = le32_to_cpu(hdr->srcaddr);
+	size = le32_to_cpu(hdr->blocksize);
+
+	if (hdr->blockid == 0x78) { /* SATA id */
+		if (offset < 1) {
+			printf("Error: Bad A38x image srcaddr.\n");
+			return -ENOEXEC;
+		}
+		offset -= 1;
+		offset *= 512;
+	}
+
+	if (hdr->blockid == 0xAE) /* SDIO id */
+		offset *= 512;
+
+	if (offset % 4 != 0 || size < 4 || size % 4 != 0) {
+		printf("Error: Bad A38x image blocksize.\n");
+		return -ENOEXEC;
+	}
+
+	checksum32 = image_checksum32((u8 *)hdr + offset, size - 4);
+	exp_checksum32 = *(u32 *)((u8 *)hdr + offset + size - 4);
+	if (checksum32 != exp_checksum32) {
+		printf("Error: Bad A38x image data checksum. 0x%08x != 0x%08x\n",
+		       checksum32, exp_checksum32);
+		return -ENOEXEC;
+	}
+
 	printf("Image checksum...OK!\n");
 	return 0;
 }
+
+#if defined(CONFIG_ARMADA_38X)
+static int a38x_image_is_secure(const struct a38x_main_hdr_v1 *hdr)
+{
+	u32 image_size = a38x_header_size(hdr);
+	struct a38x_opt_hdr_v1 *ohdr;
+	u32 ohdr_size;
+
+	if (hdr->version != 1)
+		return 0;
+
+	if (!hdr->ext)
+		return 0;
+
+	ohdr = (struct a38x_opt_hdr_v1 *)(hdr + 1);
+	do {
+		if (ohdr->headertype == A38X_OPT_HDR_V1_SECURE_TYPE)
+			return 1;
+
+		ohdr_size = (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
+
+		if (!*((u8 *)ohdr + ohdr_size - 4))
+			break;
+
+		ohdr = (struct a38x_opt_hdr_v1 *)((u8 *)ohdr + ohdr_size);
+		if ((u8 *)ohdr >= (u8 *)hdr + image_size)
+			break;
+	} while (1);
+
+	return 0;
+}
+#endif
 #else /* Not ARMADA? */
 static int check_image_header(void)
 {
@@ -717,20 +806,60 @@ static int check_image_header(void)
 }
 #endif
 
+#if defined(CONFIG_ARMADA_3700) || defined(CONFIG_ARMADA_32BIT)
+static u64 fuse_read_u64(u32 bank)
+{
+	u32 val[2];
+	int ret;
+
+	ret = fuse_read(bank, 0, &val[0]);
+	if (ret < 0)
+		return -1;
+
+	ret = fuse_read(bank, 1, &val[1]);
+	if (ret < 0)
+		return -1;
+
+	return ((u64)val[1] << 32) | val[0];
+}
+#endif
+
+#if defined(CONFIG_ARMADA_3700)
+static inline u8 maj3(u8 val)
+{
+	/* return majority vote of 3 bits */
+	return ((val & 0x7) == 3 || (val & 0x7) > 4) ? 1 : 0;
+}
+#endif
+
 static int bubt_check_boot_mode(const struct bubt_dev *dst)
 {
 #if defined(CONFIG_ARMADA_3700) || defined(CONFIG_ARMADA_32BIT)
-	int mode;
+	int mode, secure_mode;
 #if defined(CONFIG_ARMADA_3700)
 	const struct tim_boot_flash_sign *boot_modes = tim_boot_flash_signs;
 	const struct common_tim_data *hdr =
 		(struct common_tim_data *)get_load_addr();
 	u32 id = hdr->boot_flash_sign;
+	int is_secure = hdr->trusted != 0;
+	u64 otp_secure_bits = fuse_read_u64(1);
+	int otp_secure_boot = ((maj3(otp_secure_bits >> 0) << 0) |
+			       (maj3(otp_secure_bits >> 4) << 1)) == 2;
+	unsigned int otp_boot_device = (maj3(otp_secure_bits >> 48) << 0) |
+				       (maj3(otp_secure_bits >> 52) << 1) |
+				       (maj3(otp_secure_bits >> 56) << 2) |
+				       (maj3(otp_secure_bits >> 60) << 3);
 #elif defined(CONFIG_ARMADA_32BIT)
 	const struct a38x_boot_mode *boot_modes = a38x_boot_modes;
 	const struct a38x_main_hdr_v1 *hdr =
 		(struct a38x_main_hdr_v1 *)get_load_addr();
 	u32 id = hdr->blockid;
+#if defined(CONFIG_ARMADA_38X)
+	int is_secure = a38x_image_is_secure(hdr);
+	u64 otp_secure_bits = fuse_read_u64(EFUSE_LINE_SECURE_BOOT);
+	int otp_secure_boot = otp_secure_bits & 0x1;
+	unsigned int otp_boot_device = (otp_secure_bits >> 8) & 0x7;
+#endif
 #endif
 
 	for (mode = 0; boot_modes[mode].name; mode++) {
@@ -743,15 +872,42 @@ static int bubt_check_boot_mode(const struct bubt_dev *dst)
 		return -ENOEXEC;
 	}
 
-	if (strcmp(boot_modes[mode].name, dst->name) == 0)
-		return 0;
+	if (strcmp(boot_modes[mode].name, dst->name) != 0) {
+		printf("Error: image meant to be booted from \"%s\", not \"%s\"!\n",
+		       boot_modes[mode].name, dst->name);
+		return -ENOEXEC;
+	}
 
-	printf("Error: image meant to be booted from \"%s\", not \"%s\"!\n",
-	       boot_modes[mode].name, dst->name);
-	return -ENOEXEC;
-#else
-	return 0;
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_3700)
+	if (otp_secure_bits == (u64)-1) {
+		printf("Error: cannot read OTP secure bits\n");
+		return -ENOEXEC;
+	} else {
+		if (otp_secure_boot && !is_secure) {
+			printf("Error: secure boot is enabled in OTP but image does not have secure boot header!\n");
+			return -ENOEXEC;
+		} else if (!otp_secure_boot && is_secure) {
+#if defined(CONFIG_ARMADA_3700)
+			/*
+			 * Armada 3700 BootROM rejects trusted image when secure boot is not enabled.
+			 * Armada 385 BootROM accepts image with secure boot header also when secure boot is not enabled.
+			 */
+			printf("Error: secure boot is disabled in OTP but image has secure boot header!\n");
+			return -ENOEXEC;
 #endif
+		} else if (otp_boot_device && otp_boot_device != id) {
+			for (secure_mode = 0; boot_modes[secure_mode].name; secure_mode++) {
+				if (boot_modes[secure_mode].id == otp_boot_device)
+					break;
+			}
+			printf("Error: boot source is set to \"%s\" in OTP but image is for \"%s\"!\n",
+			       boot_modes[secure_mode].name ?: "unknown", dst->name);
+			return -ENOEXEC;
+		}
+	}
+#endif
+#endif
+	return 0;
 }
 
 static int bubt_verify(const struct bubt_dev *dst)

configs/dockstar_defconfig

@@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
 CONFIG_SYS_KWD_CONFIG="board/Seagate/dockstar/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2

configs/dreamplug_defconfig

@@ -3,6 +3,9 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
 CONFIG_SYS_KWD_CONFIG="board/Marvell/dreamplug/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2

configs/goflexhome_defconfig

@@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
 CONFIG_SYS_KWD_CONFIG="board/Seagate/goflexhome/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2

configs/iconnect_defconfig

@@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
 CONFIG_SYS_KWD_CONFIG="board/iomega/iconnect/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2

configs/pogo_e02_defconfig

@@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
 CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_e02/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2

configs/sheevaplug_defconfig

@@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
 CONFIG_SYS_KWD_CONFIG="board/Marvell/sheevaplug/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2

configs/turris_omnia_defconfig

@@ -33,6 +33,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
+CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -103,6 +104,7 @@ CONFIG_PINCTRL_ARMADA_38X=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_ARMADA38X=y
 CONFIG_SCSI=y
+CONFIG_SERIAL_PROBE_ALL=y
 CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y

include/configs/turris_mox.h

@@ -36,6 +36,7 @@
 	"bootm 0x5800000"
 
 #define CONFIG_EXTRA_ENV_SETTINGS				\
+	"fdt_addr=0x4c00000\0"					\
 	"scriptaddr=0x4d00000\0"				\
 	"pxefile_addr_r=0x4e00000\0"				\
 	"fdt_addr_r=0x4f00000\0"				\

tools/kwboot.c

@@ -84,7 +84,7 @@ static unsigned char kwboot_msg_debug[] = {
 #define KWBOOT_MSG_RSP_TIMEO	50 /* ms */
 
 /* Defines known to work on Armada XP */
-#define KWBOOT_MSG_RSP_TIMEO_AXP	1000 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO_AXP	10 /* ms */
 
 /*
  * Xmodem Transfers

tools/termios_linux.h

@@ -29,6 +29,7 @@
 #include <errno.h>
 #include <sys/ioctl.h>
 #include <sys/types.h>
+#include <asm/ioctls.h>
 #include <asm/termbits.h>
 
 #if defined(BOTHER) && defined(TCGETS2)