Commit graph

789 commits

Author SHA1 Message Date
Marek Behún
26f7a76ef9 pci: pci_mvebu: debug rd/wr config as other drivers do
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
241d763618 pci: pci_mvebu: cosmetic fix
Write bdf address in a same way in mvebu_pcie_read/write_config.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
201958af10 pci: pci_mvebu: use dev_seq instead of static variable
PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Pali Rohár
cba6edd68b arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.

This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.

Linux has this code too.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Vasut
06183ac5f5 pci: renesas: Fix BAR mapping on Gen3
Because the first PCIExAR(n) register is configured with the mapping,
It is the second PCIExAR(n) register that must be written with 0, not
the last one. Update the n from 4 to 1 to select the correct register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-02-20 22:38:28 +01:00
Marek Vasut
b169ef1798 pci: renesas: Make map address and mask power of two on Gen3
Both the map address and mask must be power of two per documentation,
adjust the code accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-02-20 22:38:28 +01:00
Marek Vasut
b9616d8f90 pci: renesas: Add root bus handling on Gen3
Add code to access the PCIe root bus space and configure it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-02-20 22:38:28 +01:00
Nicolas Saenz Julienne
c709243ee0 pci: pcie-brcmstb: Fix inbound window configurations
So far we've assumed a fixed configuration for inbound windows as we had
a single user for this controller. But the controller's DMA constraints
were improved starting with BCM2711's B1 revision of the SoC, notably
available in CM4 and Pi400. They allow for wider inbound windows. We can
now cover the whole address space, whereas before we where limited to
the lower 3GB.

This information is passed to us through DT's 'dma-ranges' property and
it's specially important for us to honor it since some interactions with
the board's co-processor assume we're doing so (specifically the XHCI
firmware load operation, which is handled by the co-processor after
u-boot has correctly configured the PCIe controller).

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-02-18 11:56:25 +01:00
Nicolas Saenz Julienne
85f3fddbcc pci: brcmstb: Cleanup controller state before handover
Make sure we handover the PCIe controller in a clean state. Some of the
devices hanging from the PCIe bus might need to be properly reset
through #PERST in order for Linux to be able to initialize them.

This is specially important in order to properly initialize Raspberry Pi
4 B and 400's USB chip.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-02-18 11:56:25 +01:00
Tom Rini
2ae80437fb Merge branch '2021-02-02-drop-asm_global_data-when-unused'
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-15 10:16:45 -05:00
Tom Rini
e14d5762de Merge git://git.denx.de/u-boot-marvell
- Espressobin: Set default env values at runtime (Pali)
- Espressobin: Set the maximum slave SPI speed to 40MHz (Pali)
- theadorable: PCIe test code enhancement and early deemphasis
  enabling (Stefan)
- pci_mvebu: Disable config access to PCI host bridge ports (Stefan)
- mv_sdhci: parse device-tree entry (Baruch)
2021-02-08 10:55:51 -05:00
Hou Zhiqiang
d167667d1b pci: kconfig: layerscape: Change LX2162A PCIe node compatible string
LX2162A is not like LX2160A which has different PCIe controller
in rev1 and rev2 silicon. It supports only one configuration of
PCIe controller, which is same as LS2088A. So update PCIe
compatible string same as LS2088A.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Tested-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Hou Zhiqiang
584107337b pci: layerscape: Remove the shadow SVR definitions
This patch moves the SVR definitions to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Stefan Roese
6a2fa284ae pci: pci_mvebu: Disable config access to PCI host bridge ports
This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.

While updating the Armada XP based theadorable to the latest mainline
and testing it with the DM PCI driver I noticed, that the PCI root
bridge was being configured incorrectly. Resulting in the PCIe Intel
WiFi was not working correctly in Linux. With this patch applied, all
PCIe devices work without any issues in Linux again.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
2021-02-08 08:53:14 +01:00
Simon Glass
4d7bab1adb dm: pci: Correct use of wrong flag name
Update a driver that uses the incorrect flag. Add a comment to hopefully
prevent furture mistakes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03 03:38:41 -07:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Stefan Roese
a7a029d14d pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more)
This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as
it is not configured for any board (any more). With this removal, some
PCI related files get cleaned up a bit.

Additional, dm_pciauto_setup_device() is now static, as it's not
referenced from any code outside of this C file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-27 17:03:16 -05:00
Pali Rohár
279b573657 arm64: a37xx: pci: Fix printing debug messages
Value pcie->dev in function pcie_advk_probe() is not initialized yet
so use dev as argument for dev_dbg()/dev_warn().

Function pcie_advk_wait_pio() itself prints error message on failure
so do not print duplicate error message in caller.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27 13:12:51 +01:00
Phil Sutter
ba8ae03eab pci: pci_mvebu: Define an IO region as well
Configure an IO region and window for PNP identical to how MEM region is
set up. Linux does this only if the DT defines a pcie-io-aperture
property for the SOC, but since all supported boards do this should not
be needed.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27 07:29:43 +01:00
Phil Sutter
c1b1263b16 pci: Make auto-config code a little more robust
On my DS414, some PCI devices return odd values when probing BAR sizes.
An obvious case is all-ones response, the Linux driver
(drivers/pci/probe.c) catches those explicitly and a comment explains
that either bit 0 or bit 1 must be clear (depending on MEM or IO type).
Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break
size calculation due to the "middle" zeroes. Mitigate that copying more
or less what Linux does and do a "find least bit set".

Signed-off-by: Phil Sutter <phil@nwl.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-27 07:29:43 +01:00
Shawn Lin
9ddc0787bd pci: Add Rockchip dwc based PCIe controller driver
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 12:00:45 +08:00
Ovidiu Panait
b9f6d0f7db common: board_r: Drop initr_pci wrapper
Add a return value to pci_init and use it directly in the post-relocation
init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Tom Rini
b11f634b1c Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
 dtoc: Tidy up and add more tests
 ns16550 code clean-up
 x86 and sandbox minor fixes for of-platdata
 dtoc prepration for adding build-time instantiation
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Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next

Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
2021-01-05 22:34:43 -05:00
Tom Rini
720620e691 Prepare v2021.01-rc5
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Merge tag 'v2021.01-rc5' into next

Prepare v2021.01-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05 16:20:26 -05:00
Simon Glass
7d14ee443c dm: core: Use dev_has_ofnode() instead of dev_of_valid()
We have two functions which do the same thing. Standardise on
dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in
normal operation: it is either null or missing.

Also move the functions into one place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05 12:24:41 -07:00
Simon Glass
2462139fdd dm: core: Rename sqq to seq_
Now that the sequence-numbering migration is complete, rename this member
back to seq_, adding an underscore to indicate it is internal to driver
model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05 12:24:41 -07:00
Simon Glass
0fd3d91152 dm: Use access methods for dev/uclass private data
Most drivers use these access methods but a few do not. Update them.

In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
2021-01-05 12:24:40 -07:00
Pali Rohár
0eb0eb4ab2 Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"
This reverts commit 828d326216.

This change revers code which asserting PERST# signal when unloading
driver. Driver's remove callback is still there as it is used for other
functionality.

Asserting PERST# signal prior booting kernel is causing that A3720 boards
(Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and
4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900)
and anymore. When PERST# signal is not asserted these cards are detected
correctly. As this is regression for existing stable Linux kernel versions
revert this problematic change in U-Boot.

To make cards working with OpenWRT 4.14 kernel it is needed to disable link
training prior booting kernel, which is already done in driver's remove
callback.

Described issue is in Linux kernel pci aardvark driver which is (hopefully)
fixed in latest upstream versions. Latest upstream versions should be able
to initialize PCIe bus and detects cards independently of the link training
and PERST# signal state.

So with this change, U-Boot on A3720 boards should be able to boot OpenWRT
4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-12-28 09:42:06 +01:00
Simon Glass
a133e2179a dm: core: Update uclass_find_next_free_req_seq() for new scheme
This function current deals with req_seq which is deprecated. Update it to
use the new sequence numbers, putting them above existing aliases. Rename
the function to make this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Simon Glass
42f3663a3f pci: Update to use new sequence numbers
Now that we know the sequence number at bind time, there is no need for
special-case code in dm_pci_hose_probe_bus().

Note: the PCI_CAP_ID_EA code may need a look, but there are no test
failures so I have left it as is.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Simon Glass
8b85dfc675 dm: Avoid accessing seq directly
At present various drivers etc. access the device's 'seq' member directly.
This makes it harder to change the meaning of that member. Change access
to go through a function instead.

The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Simon Glass
8a8d24bdf1 dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
b012ff1f1b dm: treewide: Update 'auto' declarations to be on one line
Fix up the code style for those declarations that should now fit onto one
line, which is all of them that currently do not.

This is needed for dtoc to detect the structs correctly, at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
d1998a9fde dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
c69cda25c9 dm: treewide: Rename dev_get_platdata() to dev_get_plat()
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Simon Glass
734206dda1 dm: core: Rename device_bind_ofnode() to device_bind()
This is the standard function to use when binding devices. Drop the
'_ofnode' suffix to make this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 07:58:18 -07:00
Hou Zhiqiang
ee7c1225e3 pci: layerscape: fix a dead loop issue
Fixes: commit 8ec619f8fd ("pci: layerscape: Fixup PCIe EP
	mode DT nodes for LX2160A rev2")

This added the PCIe EP nodes fixup of LX2160A, but it
didn't update the condition value when there isn't a
property 'apio-wins'.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Fixed checkpatch error]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Meenakshi Aggarwal
3a187cff7a armv8: lx2162a: Add Soc changes to support LX2162A
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.

LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
1255f8bc36 pci: ls_pcie_g4: Add size check for config resource
resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
49df7c9086 pci: layerscape: Add size check for config resource
resource "config" is required to have minimum 8KB space
as per hardware documentation.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
eac364416c pci: ls_pcie_g4: Print pcie controller number starting from 1
Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
2020-12-10 13:56:38 +05:30
Wasim Khan
b6c6a245bf pci: layerscape: Update print of pcie controller
Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
[Trimmed subject]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:38 +05:30
Hou Zhiqiang
0205beb156 dm: pci: fsl: Correct the workaround of erratum A-007815
The register to enable/disable the write-permission of DBI RO
registers should be accessed via the CFG_ADDR/CFG_DATA registers
instead of accessing directly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Laurentiu Tudor
2a5bbb13cc pci: layerscape: add a way of specifying additional iommu mappings
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more static scenarios such as hardwired PCI endpoints
that get initialized later in the system setup) that would allow
two things:
 - for a SRIOV capable PCI EP identified by its B.D.F specify
   the maximum number of VFs that will ever be created for it
 - for hot-plug case, specify the B.D.F with which the device
   will show up on the PCI bus
More details can be found in the included documentation:
  arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Laurentiu Tudor
f4cd963325 pci: layerscape: move pci node search in a common function
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Laurentiu Tudor
1f46e6790a pci: layerscape: move per-pci device fdt fixup in a function
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:08 +05:30
Tom Rini
b7e7831e5d Merge branch 'next'
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 14:10:59 -04:00
Tom Rini
253388acd6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes related to PCIe, pfe, xfi, gpio, reset, vid, env, and usb on
  layerscape products
2020-09-25 12:55:06 -04:00
Hou Zhiqiang
8ec619f8fd pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Pali Rohár
5f50b88ab6 arm64: a37xx: pci: Disable link training when unloading driver
As required by PCI Express spec a delay for at least 100ms after
de-asserting PERST# signal is needed before link training is enabled.

Linux kernels prior to 5.8 version do not automatically disable link
training before de-asserting PERST# signal, therefore this requirement is
not fulfilled.

Above requirement is needed for proper detection of some Compex PCIe WiFi
cards. Otherwise Linux kernel cannot detect it.

To allow using those PCIe cards with older Linux kernel versions booted by
U-Boot compiled with U-Boot a37xx pci driver, disable link training in
U-Boot when unloading this pci driver.

Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver
when booting Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-24 10:14:06 +02:00
Michael Walle
b7585aa9b1 pci: layerscape: Fix spurious writes and panic
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI
root devices are layerscape PCIe controllers. Unfortunately, this is not
true for the LS1028A. There is one additional static PCI root complex
(this contains the networking devices) which has nothing to do with the
layerscape PCIe controllers. On recent U-Boot versions this results in
the following panic:

"Synchronous Abort" handler, esr 0x96000044
elr: 000000009602fa04 lr : 000000009602f9f4 (reloc)
elr: 00000000fbd73a04 lr : 00000000fbd739f4
x0 : 0080000002000101 x1 : 0000000000000000
x2 : 00000000fbde9000 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0
x8 : 0000000000000002 x9 : 000000000000000c
x10: 00000000ffffffe8 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000a2c
x14: 00000000fbb3d2cc x15: 00000000ffffffff
x16: 0000000000010000 x17: 0000000000000000
x18: 00000000fbb3fda0 x19: 0000000000000800
x20: 0000000000000000 x21: 00000001f0000000
x22: 0000000000000800 x23: 0000000000000009
x24: 00000000fbdc3c1b x25: 00000000fbdc28e5
x26: 00000000fbdcc008 x27: 00000000fbdc16e2
x28: 000000000f000000 x29: 00000000fbb3d3a0

Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814)
Resetting CPU ...

This bug already existed in former versions, but the spurious write was
never trapped, because the destination address was a valid address (by
pure luck).

Make sure the PCI root is actually one of the expected PCIe layerscape
controllers by matching its compatible string.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23 19:33:44 +05:30
Chuanjia Liu
9250d0bad5 PCI: mediatek: Release the resource when PCIe enable port fail
On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-10 15:32:09 -04:00
Chuanjia Liu
df85e9576c PCI: mediatek: Release the resource when PCIe enable port fail
On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-10 11:17:46 -04:00
Tom Rini
314b9b4a38 Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next 2020-09-07 14:31:00 -04:00
Pali Rohár
835d969c1f arm64: a37xx: pci: Depends on DM_GPIO
For proper initialization of aardvark pci driver it is required to
de-assert reset GPIO. So depeneds on DM_GPIO option.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
828d326216 arm64: a37xx: pci: Assert PERST# signal when unloading driver
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.

DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.

Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.

Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
563b85bd88 arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Michal Simek
a261fdce38 pci: kconfig: Setup proper dependency for PCIE_ROCKCHIP
There is missing dependency for PCIE_ROCKCHIP which selects
PHY_ROCKCHIP_PCIE which directly depends on ARCH_ROCKCHIP.

WARNING: unmet direct dependencies detected for PHY_ROCKCHIP_PCIE
  Depends on [n]: ARCH_ROCKCHIP [=n]
  Selected by [y]:
  - PCIE_ROCKCHIP [=y] && PCI [=y]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-27 11:20:33 -04:00
Stefan Roese
dfaf6a5797 CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
Since commit 86cf1c8285 ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
commit 999a772d9f ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
It makes no sense to still carry code that is guarded with
"#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
all these unreferenced code paths.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-26 09:19:16 +02:00
Suneel Garapati
638d705a54 pci: Add PCI controller driver for OcteonTX / TX2
Adds support for PCI ECAM/PEM controllers found on OcteonTX
or OcteonTX2 SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
f0c369284d pci: pci-uclass: Check validity of ofnode
Add check if the referenced ofnode is valid.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
a3fac3f395 pci: pci-uclass: Add support for Alternate-RoutingID capability
If ARI capability is found on device, use it to update next function
number in bus scan and also helps to skip unnecessary bdf scans.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
51eeae91c5 pci: pci-uclass: Add VF BAR map support for Enhanced Allocation
Makes dm_pci_map_bar API available to map BAR for Virtual function
PCI devices which support Enhanced Allocation.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
b8852dcfcb pci: pci-uclass: Add support for Single-Root I/O Virtualization
SR-IOV - Single Root I/O Virtualization
PF - Physical Function VF - Virtual Function

If SR-IOV capability is present, use it to initialize Virtual Function
PCI device instances. pci_sriov_init function will read SR-IOV
registers to create VF devices under the PF PCI device and also bind
driver if available. This function needs to be invoked from Physical
function device driver which expects VF device support, creating
minimal impact on existing framework.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
636cc1773a pci: pci-uclass: Add support for Enhanced Allocation in Bridges
If Enhanced Allocation capability is present in bridges, use it
to read the fixed sub-ordinate bus number.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
4cf56ec07f pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
bc30140d20 pci: pci-uclass: Make DT subnode parse optional
Parse subnode DT properties only if parent node is valid.
Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode
from dev_for_each_subnode.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Suneel Garapati
b3699a13a6 pci: pci-uclass: Fix incorrect argument in map_physmem
Fix argument ordering for map_physmem() called in dm_pci_map_ea_bar().
Additinally minor spelling correction.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
e002474158 pci: pci-uclass: Dynamically allocate the PCI regions
Instead of using a fixed length pre-allocated array of regions, this
patch moves to dynamically allocating the regions based on the number
of available regions plus the necessary regions for DRAM banks.

Since MAX_PCI_REGIONS is not needed any more, its removed completely
with this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
3b7cd265b8 pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always set
Since the migration to Kconfig, CONFIG_NR_DRAM_BANKS is configured for
all boards. Hence we can remove the conditional compilation and the code
path that will never get compiled.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Chuanjia Liu
91ee45d806 PCI: mediatek: Add PCIe support for MT7622
This patch adds PCIe support for the Mediatek MT7622 SOC.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-19 17:37:37 -04:00
Srinath Mannam
4848704aef drivers: pcie: add Broadcom IPROC PCIe RC driver
Add support for IPROC PAXC PCIe RC driver.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 09:43:21 -04:00
Rayagonda Kokatanur
143eb5b1ca drivers: pci: add api to get dma regions
Add api to get dma regions.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-08-14 09:43:21 -04:00
Simon Glass
51a4a857b3 pci: Drop dm.h inclusion from header file
The layerscape header should not include dm.h so remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Hou Zhiqiang
ed188aa886 pci: layerscape: Add specific config entry for RC and EP mode driver
Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
4085e3a46a pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2
Add the PCIe EP mode support for lx2160a-v2 platform.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
80b5a662b7 pci: layerscape: Modify the ls_pcie_dump_atu function
Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
83bf32e680 pci_ep: layerscape: Add the SRIOV VFs of PF support
Add the INBOUND configuration for VFs of PF.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
78c56b29fc pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
15ce1fadf7 pci_ep: layerscape: Add the workaround for errata A-009460
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
c5174a52c2 pcie_ep: layerscape: Add the multiple function support
Add the multiple function support for Layerscape platform, some PEXs
of Layerscaple platform have more than one PF.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
118e58e26e pci: layerscape: Split the EP and RC driver
Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Jagan Teki
ad415c80a5 pci: rockchip: Drop legacy PHY driver
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:49 +08:00
Jagan Teki
ce920e0e56 pci: rockchip: Switch to generic-phy
Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:47 +08:00
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Tom Rini
3113c84ba2 - add support for PCI and XHCI for RPi4 (64 bit only)
- optionally reset XHCI device on registration
 - enable USB_KEYBOARD for rpi_4_defconfig
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Merge tag 'rpi-next-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi

- add support for PCI and XHCI for RPi4 (64 bit only)
- optionally reset XHCI device on registration
- enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10 14:31:22 -04:00
Sylwester Nawrocki
7b1c3f6f65 pci: Add driver for Broadcom BCM2711 SoC PCIe controller
This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is used.

The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10 11:49:28 +02:00
Sylwester Nawrocki
b6687e19f9 pci: Move some PCIe register offset definitions to a common header
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09 15:46:12 +02:00
Simon Glass
0938767da1 video: pci: Set up the copy framebuffer
When using a copy framebuffer we need to tell the video subsystem its
address. U-Boot's normally allocated framebuffer is used as the working
buffer, but nothing is displayed until it is copied to the copy
framebuffer.

For this to work the video driver must request that a framebuffer be
allocated separately from the hardware framebuffer, so add a check for
that.

Also add a log category so that logging appears correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09 12:33:24 +08:00
Tom Rini
8214791daa pci: rockchip: Mark inline functions as static inline
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.

Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-01 11:48:05 -04:00
Mark Kettenis
dbc5e28604 pci: Make Rockchip PCIe voltage regulators optional
The vpcie*-supply properties are optional and these are absent on
boards like the ROCKPro64 and Firefly RK3399 where the voltage is
supplied by always-on regulators that are already enabled upon
boot.  Make these regulators optional and properly check their
presence before attempting to enable them.

Makes PCIe work on un U-Boot on the boards mentioned above.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2020-05-29 17:59:49 +08:00
Jagan Teki
89f2fa0b5e pci: Add Rockchip PCIe PHY controller driver
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.

The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.

Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.

Example:

grf: syscon@ff770000 {
   compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
   reg = <0x0 0xff770000 0x0 0x10000>;
   #address-cells = <1>;
   #size-cells = <1>;

   pcie_phy: pcie-phy {
       compatible = "rockchip,rk3399-pcie-phy";
       clocks = <&cru SCLK_PCIEPHY_REF>;
       clock-names = "refclk";
       #phy-cells = <1>;
       resets = <&cru SRST_PCIEPHY>;
       drive-impedance-ohm = <50>;
       reset-names = "phy";
       status = "disabled";
   };
};

Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Jagan Teki
99d59069c0 pci: Add Rockchip PCIe controller driver
Add Rockchip PCIe controller driver for rk3399 platform.

Driver support Gen1 by operating as a Root complex.

Thanks to Patrick for initial work.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-22 20:53:20 +08:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
52f2423804 common: Drop bootstage.h from common header
Move this fairly uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Trevor Woerner
18138ab203 rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Simon Glass
f1f4438218 pci: Avoid auto-config when chain loading
When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:40:16 +08:00
Simon Glass
3cabcf966d x86: Move acpi_s3.h to include/acpi/
This header relates to ACPI and we are about to add some more ACPI
headers. Move this one into a new directory so they are together.

The header inclusion in pci_rom.c is not specific to x86 anymore, so drop
the #ifdef CONFIG_X86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16 14:36:28 +08:00
Simon Glass
9ece4b090f pci: Adjust dm_pci_read_bar32() to return errors correctly
At present if reading a BAR returns 0xffffffff then the value is masked
and a different value is returned. This makes it harder to detect the
problem when debugging.

Update the function to avoid masking in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-04-16 14:36:28 +08:00
Simon Glass
d8c7fb5036 dm: pci: Allow disabling auto-config for a device
Add a means to avoid configuring a device when needed. Add an explanation
of why this is useful to the binding file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16 14:36:28 +08:00
Vladimir Oltean
f83567e0c0 pci-host-ecam-generic: access config space independent of system-wide bus id
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.

Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.

Fixes: 3675cb044e ("PCI: Add driver for a 'pci-host-ecam-generic' host controller")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:11:56 +05:30
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
61b29b8268 dm: core: Require users of devres to include the header
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
194fca9130 dm: pci: Update a few more interfaces for const udevice *
Tidy up a few places where const * should be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
c4e72c4ad8 dm: pci: Update the PCI read_config() method to const dev *
At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Wasim Khan
9c2969e92c pci: layerscape: device tree fixup based on SoC and
lx2160a rev1 requires layerscape_gen4 device tree fixup and
lx2160a rev2 requires layerscape device tree fixup.
Add device tree fixup for lx2160a based on SoC and Version.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Wasim Khan
d20eb7a6db pci: layerscape: Move streamId allocation to common device tree fixup
Move streamId allocation to layerscape common device tree fixup.
Calculate streamId based on SoC variant.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Wasim Khan
1185b229cc pci: layerscape: Common device tree fixup for NXP SoCs
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Hou Zhiqiang
282d992e1a pci: layerscape: Fix the BARs disable function
There is not any difference for disabling BARs in RC mode
between PCIe controllers with and without SRIOV.

Fixes: 80afc63fc3 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Hou Zhiqiang
f8203e3bb5 pci: layerscape: Fix the disabling of Expansion ROM BAR
The software will still get non-zero Expansion ROM BAR size
even when the BAR_EN bit is cleared. The BAR_EN bit of
register EXP_ROM_BAR_MASK_RC is not working as expected,
so this patch changes to mask all the bits.

Fixes: 80afc63fc3 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Simon Glass
35a3f871fc common: Move ll_boot_init() to init.h
This is an init-related function so belongs in that file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:28 -05:00
Simon Glass
4886287ee4 pci: Print a warning if the bus is accessed before probing
It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Tom Rini
d8a3f5259a New for 2020.04
---------------
 
 - New boards
 	Embedded Artists COM board
 	Xea Board
 - Switch to DM:
 	Aristainetos boards
 	Toradex colibri (DM_ETH)
 	iCubox
 	GE bx50v3
 	mx7dsabre (DM_ETH)
 	cx9020
 - New features:
 	Bootaux with elf files
 	Default SYS_THUMB_BUILD for i.MX6/7
 - Fixes:
 	DHCOM i.MX6 PDK
 	Engicam
 	i.MX8M tools (imx8m_image)
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
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Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
2020-01-07 08:45:43 -05:00
Marek Vasut
c5773ccdca pci: imx: Add iMX6SX compatible
The driver works fine with iMX6SX, add the missing compatible string.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-01-07 10:26:56 +01:00
Pankaj Bansal
63618e71e8 pci: layerscape: Manage PCIe EP compatible string via Kconfig
The ep node device tree name is governed by these bindings:
https://github.com/torvalds/linux/blob/master/Documentation/
devicetree/bindings/pci/layerscape-pci.txt#L24

As per above the ep compatible node contains platform name.
Therefore, define the ep node compatible as CONFIG to find the
pcie ep node in device tree during device tree fixup.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02 14:36:57 +05:30
Pankaj Bansal
ba7c966c0f pci: layerscape: move PCIE related CONFIG to PCI Kconfig
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02 14:36:57 +05:30
Wasim Khan
7cd4272821 armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160A
Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM
for lx2160a.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
0b964b03b0 pci: layerscape_gen4: Suffix API names with _ls_gen4
Update API names for layerscape gen4 fixup.
Suffix layerscape_gen4 fixup API names with _ls_gen4.
This is required to organize device tree fixup in common, layerscape
and layerscape_gen4 specific code.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
485304af96 pci: layerscape: Suffix API names with _ls
Suffix layerscape fixup API names with _ls.
This is required to organize device tree fixup in common,
layerscape and layerscape_gen4 specific code.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
c81b1ea7b0 pci: layerscape: Add stream_id_cur field to ls_pcie structure
Add stream_id_cur field to ls_pcie structure and initialize
it with 0 for all pcie controllers. This field will be used
for streamId calculation.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
5ff7b84084 drivers/pci : enable pcie_layerscape code for lx2160a rev2
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Simon Glass
6dd4b01432 dm: pci: Move pci_get_devfn() into a common file
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.

To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.

Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Simon Glass
2206ac248a dm: pci: Allow delaying auto-config until after relocation
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.

This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Simon Glass
bcee8d6764 dm: gpio: Allow control of GPIO uclass in SPL
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Michael Walle
a6cd597a78 drivers: pci: ignore disabled devices
PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-05 10:28:38 -05:00
Tom Rini
923e211f8d pci: Only link pci_rom.o in some cases
The content of pci_rom.c is only used in a few cases.  Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 08:43:24 -05:00
Simon Glass
2cf431c228 common: Move pci_init_board() out of common.h
This function can be dropped when all boards use driver model for PCI. For
now, move it into init.h with a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:25 -05:00
Tom Rini
0b73ef0c02 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI
2019-11-11 14:19:04 -05:00
Pankaj Bansal
05c81d98e4 pci: layerscape: Only set EP CFG READY bit
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.

While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.

Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
liu hao
e3aafef4cf arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>

Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-07 18:01:13 -05:00
Heiko Schocher
b61cbbdcab pci: add DM based mpc85xx driver
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-06 16:30:19 +05:30
Tom Rini
9189d6f1e9 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Remember the device being emulated for Sandbox PCI
- Update Kconfig options for FSP 1.0
- Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
2019-10-12 10:52:48 -04:00
Ryder Lee
42d37450e5 pci: mediatek: add PCIe controller support for MT7623
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11 10:09:58 -04:00
Simon Glass
6498fda140 sandbox: pci: Remember the device being emulated
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:15 +08:00
Simon Glass
75d8f49481 sandbox: pci: Create a new sandbox_pci_read_bar() function
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:48 +08:00
Simon Glass
a827ba910c x86: pci: Drop the first parameter in pci_x86_r/w_config()
This parameter is needed by the PCI driver-mode interface but is always
NULL on x86. There are a number of calls to this function so it makes
sense to minimise the parameters.

Adjust the x86 function to omit the first parameter, and introduce stub
functions to handle the conversion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
49a0f8cc96 x86: Move acpi_s3.h to a common location
At present this hedaer is only available on x86. To allow sandbox to use
it for testing, move it to a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
6a73cf3d8f pci: Show a message if PCI autoconfig fails
At present this fails silently which can be confusing since some devices
on the PCI bus may not work correctly. Show a message in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add a '\n' in the PCI autoconfig fail message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:42 +08:00
Simon Glass
f365152a55 pci: Add more debug detail when resources are exhausted
If PCI auto-config runs out of memory, show a few more details to help
diagnose the problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: change %x to %llx to avoid build warnings on some platforms]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:42 +08:00
Simon Glass
90c668605f pci: Disable autoconfig in SPL
At present U-Boot runs autoconfig in SPL but this is best left to U-Boot
proper. For TPL and SPL we can normally used fixed BARs and save code size
and time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:42 +08:00
Simon Glass
0911569b28 pci: Show the result of binding a device
Update the debugging info a little to show the result of trying to bind
a PCI device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:42 +08:00
Simon Glass
be0d8fa452 pci: sandbox: Probe PCI emulation devices when used
At present PCI emulation devices are not probed before use, since they
used to be children of the device that used them, and children cannot be
probed before their parents.

Now that PCI emulation devices are attached to the root node, we can
simply probe them, and avoid using the internal function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:41 +08:00
Simon Glass
9b69ba4a78 pci: sandbox: Move the emulators into their own node
Sandbox pci works using emulation drivers which are currently children of
the pci device:

	pci-controller {
		pci@1f,0 {
			compatible = "pci-generic";
			reg = <0xf800 0 0 0 0>;
			emul@1f,0 {
				compatible = "sandbox,swap-case";
			};
		};
	};

In this case the emulation device is attached to pci device on address
f800 (device 1f, function 0) and provides the swap-case functionality.

However this is not ideal, since every device on a PCI bus has a child
device. This is only really the case for sandbox, but we want to avoid
special-case code for sandbox.

Worse, child devices cannot be probed before their parents. This forces
us to use 'find' rather than 'get' to obtain the emulator device. In fact
the emulator devices are never probed. There is code in
sandbox_pci_emul_post_probe() which tries to track when emulators are
active, but at present this does not work.

A better approach seems to be to add a separate node elsewhere in the
device tree, an 'emulation parent'. This could be given a bogus address
(such as -1) to hide the emulators away from the 'pci' command, but it
seems better to keep it at the root node to avoid such hacks.

Then we can use a phandle to point from the device to the correct
emulator, and only on sandbox. The code to find an emulator does not
interfere with normal pci operation.

Add a new UCLASS_PCI_EMUL_PARENT uclass which allows finding an emulator
given a bus, and finding a bus given an emulator. Update the existing
device trees and the code for finding an emulator.

This brings PCI emulators more into line with I2C.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix 3 typos in the commit message;
        encode bus number in the labels of swap_case_emul nodes;
        mention commit 4345998ae9 in sandbox_pci_get_emul()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:41 +08:00
Simon Glass
07f2f58b94 x86: fsp: Create a common fsp_support.h header
Many support functions are common between FSP1 and FSP2. Add a new header
to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove forward declarations in fsp_support.h]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:53:41 +08:00
Simon Glass
8331188615 x86: Rename existing FSP code to fsp1
Since there is now a new version of the FSP and it is incompatible with
the existing version, move the code into an fsp1 directory. This will
allow us to put FSP v2 code into an fsp2 directory.

Add a Kconfig which defines which version is in use.

Some of the code in this new fsp1/ directory is generic across both FSPv1
and FSPv2. Future patches will address this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:50:08 +08:00
Marek Vasut
72c2f4acd7 pci: sh7751: Convert to DM and DT probing
Convert the SH7751 PCI driver to DM and add DT probing.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2019-09-02 17:38:43 +02:00
Hou Zhiqiang
92e025c6e1 dm: pcie_fsl: Add MPC8548 PCIe support
Add compatible string for MPC8548 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:47 +05:30
Hou Zhiqiang
5274459628 dm: pcie_fsl: Add P5040 PCIe support
Add compatible string for P5040 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:47 +05:30
Hou Zhiqiang
7b7e4e1b7e dm: pcie_fsl: Add P4080 PCIe support
Add compatible string for P4080 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
096d5f8015 dm: pcie_fsl: Add P3041 PCIe support
Add compatible string for P3041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
1a92802e32 dm: pcie_fsl: Add P2041 PCIe support
Add compatible string for P2041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:46 +05:30
Hou Zhiqiang
ba827365f7 dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs
Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Hou Zhiqiang
4392ddbbbb dm: pcie_fsl: Add T104x PCIe support
Add compatible string for T104x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Hou Zhiqiang
a8c79f6189 dm: pcie_fsl: Add T102x PCIe support
Add compatible string for T102x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Hou Zhiqiang
9acc038b39 dm: pcie_fsl: Add T4240 PCIe support
Add compatible string for T4240 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:45 +05:30
Hou Zhiqiang
fbcb2ff5c6 dm: pcie_fsl: Fix the calculation of controller index
The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe240000) and stride (0x10000)
to calculate the controller's index.

Fix it by adding the related info to the driver data
structure.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:44 +05:30
Hou Zhiqiang
d18d06ac35 dm: pcie_fsl: Fix the Class Code fixup function
The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.

So add the Class Code fixup for the block revision < 3.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:44 +05:30
Hou Zhiqiang
adc983b4d6 dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef
This can avoid build error:
The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only
defined on the platforms that select the CONFIG_FOO, while
it's not defined on platforms that do not select the
CONFIG_FOO.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28 13:47:44 +05:30
Tom Rini
88c7a0a8c2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Various improvements to Keymile boards - mostly DT conversation
  (Pascal & Holger)
- Removal of now unsupported Keymile boards (Pascal & Holger)
- Small MVEBU PCI fix (Marek)
- Turris Omnia defconfig update (Marek)
- Misc Allied Telesis defconfig updates (Chris)
2019-08-12 23:03:44 -04:00
Tom Rini
9c6115822e Merge branch '2019-08-11-ti-imports'
- More DaVinci updates and fixes
- PCIe support on am65x
- Watchdog converted to DM
- Assorted other bugfixes
2019-08-12 18:47:53 -04:00
Sekhar Nori
03c396bb5f pcie: ti: add driver for AM65x PCIe RC
Add driver supporting PCIe root-complex available
on TI's AM65x SoC.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:39 -04:00
Marek Behún
193a1e9f19 pci: pci_mvebu: set BAR0 after memory space is set
The non-DM version of this driver used to set BAR0 register after the
calls to pci_set_region.
I found out that for some strange reason the ath10k driver in kernel
fails to work if this is done the other way around.
I know that Linux's driver should not depend on how U-Boot does things,
but for some strange reason it does and this seems to be the simplest
solution. Fix it since it caused regressions on Omnia.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 13:59:31 +02:00
Simon Glass
7b51b576d6 env: Move env_get() to env.h
Move env_get() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Ley Foon Tan
d44f793207 pci: intel: Fix configuration type based on secondary number
This fix issue when access config from PCIe switch.

The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.

The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11 16:43:41 -04:00
Ley Foon Tan
bf9b9813ad pci: intel: Fix error when enumerating multi-function PCIe device
Hardware return completion status non-zero when read from non exist
function in multi-function PCIe device. Return error will cause PCIe
enumeration fail.

Change it to return 0 and return value 0xffffffff when error.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11 16:43:41 -04:00
Ley Foon Tan
d0e52c6f29 pci: intel: Increase TLP polling counter
Some PCIe devices require longer time to response.
Increase polling counter to 20000 (~100ms).

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11 16:43:41 -04:00
Marek Behún
60ee60944b pci: ensure enumeration of all devices in pci_init
Use the uclass_first_device_check and uclass_next_device_check functions
instead of uclass_first_device and uclass_next_device in pci_init. This
ensures that all PCI devices are tried to be probed. Currently if a
device fails to probe, the enumeration stops and the devices which come
after the failed device are not probed.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-12 21:07:58 -04:00
Alex Marginean
b8e1f8270c drivers: pci: add API to issue FLR on a PCI function if supported
Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function,
if FLR is supported.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Alex Marginean
0b143d8ab2 drivers: pci: add map_bar support for Enhanced Allocation
Makes dm_pci_map_bar API available for integrated PCI devices that
support Enhanced Allocation instead of the original PCI BAR mechanism.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Bin Meng
5fafd7e35f pci: Avoid assigning PCI resources that are below 0x1000
commit b7598a43f2 ("[PATCH] Avoid assigning PCI resources from
zero address") only moved the bus lower address to 0x1000 if the
given bus start address is zero. The comment said 0x1000 is a
reasonable starting value, hence we'd better apply the same
adjustment when the given bus start address is below 0x1000.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-21 10:07:11 -04:00
Hou Zhiqiang
b89e3d9250 dm: pci: add Freescale PowerPC PCIe driver
Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20 10:44:45 +05:30
Marek Vasut
a11c0f44b7 pci: imx: Add DM and DT support
Add DM support and support for probing the iMX PCI driver from DT.
The legacy non-DM support is retained, however shall be removed once
DM PCI is the only option remaining.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marek Vasut
d2cc2e86f8 pci: imx: Pass driver private data around
Pass the driver private data around the driver as much as possible, instead
of having it as a static global variable. This is done in preparation for
the DM conversion, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marek Vasut
90f87fb525 pci: imx: Fix potential 64bit memory access clamping
The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marek Vasut
33f794be36 pci: imx: Factor out hard-coded register base addresses
Pull out hard-coded register base addresses into driver private
structure in preparation for DM conversion. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Tom Rini
c18b103657 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
2019-05-26 20:18:20 -04:00
Hou Zhiqiang
1d341bc4b6 pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
07ce19f5e9 pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Marek Vasut
776abedef4 pci: renesas: Add RCar Gen3 PCIe controller driver
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs.
The PCIe on Gen3 is used both to connect external PCIe peripherals.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21 22:15:31 +02:00
Mario Six
904c47fc7d mpc83xx: Make distinct caddy2 config
vme8349.h contains two separate boards: The vme8349 itself, and the
caddy2 board. The caddy2 board is chosen by setting certain config
variables. Create a proper config file for the caddy2 board to make
Kconfig migration easier.

Furthermore, simplify the vme8349 and caddy2 configs by keeping only the
options necessary for each board.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20 13:50:34 +02:00
Mario Six
c2a446048e vme8349: Migrate to CONFIG_TARGET_VME8349
CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace
CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20 13:50:34 +02:00
Mario Six
d5cfa4aa5d mpc83xx: Introduce ARCH_MPC834*
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20 13:50:34 +02:00
Simon Glass
6c456516e2 x86: Support PCI VGA ROM when TPL is used
When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:16 +08:00
Thierry Reding
d94d9aa675 pci: Add boundary check for hose->regions
Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Stefan Roese
0df62e8da8 pci: pci_mvebu: Add comment about missing of_n_addr_cells() call
This patch adds a comment to explain the use of the hardcoded value for
the number of address cells in mvebu_get_tgt_attr(). This should help to
rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in
general.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Simon Glass
11503be448 pci: Don't export pci_hose_config_device()
This function is not used outside this file so make it static.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:21:44 +08:00
Baruch Siach
6664a0e5f3 pcie: designware: mvebu: fix reset release polarity
The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.

Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Tom Rini
bdac5e18a8 Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me
- Move Armada XP / 38x LCD driver to DM_VIDEO from me
- Add uDPU board (Armada-3720) from Vladimir

[trini: Fix warning in pci-uclass.c by removing ret from
	pci_uclass_child_post_bind as it no longer calls functions with
        a return code to catch.]
Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05 12:29:59 -05:00
Stefan Roese
94f453ea38 pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.

To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05 14:22:38 +01:00
Stefan Roese
b52142004f pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-05 14:22:24 +01:00
Xiaowei Bao
59a557f360 pci: layerscape: Add the dts fixup for EP and RC
Add the dts fixup when PCI controller work diffferent mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:40 -08:00
Xiaowei Bao
87e0d2b9ac pci: layerscape: Do not scan when PEX work in EP mode
Don't scan the bus when the PEX work in EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:33 -08:00
Xiaowei Bao
5bd3c9d556 pci: layerscape: Modify the EP and RC mode judge method
Modify the RC and EP mode judge method, save the mode as a variable,
the variable will be used by other function.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:28 -08:00
Simon Glass
06696ebe67 video: Allow driver to specify the line length
At present line_length is always calculated in video_post_probe(). But
some hardware may use a different line length, e.g. with a 1366-wide
display.

Allow the driver to set this value if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-12-03 19:09:44 +01:00
Hou Zhiqiang
2a87f7fdd5 dm/pci: Change the first CFG read to Vendor ID in enumeration
As the PCIe specification recommend reading the Vendor ID register
to determine if a Function is present, read the Vendor ID of a
non-existent Function must not result in system error, so we'd better
make the first CFG read to Vendor ID instead of Header Type register
in the PCIe enumeration.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-20 19:14:22 -07:00
Bin Meng
a8c5f8d3d0 dm: pci: Add APIs to find next capability and extended capability
This introduces two new APIs dm_pci_find_next_capability() and
dm_pci_find_next_ext_capability() to get PCI capability address
and PCI express extended capability address for a given PCI device
starting from a given offset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Marek Vasut
02e4d38d87 pci: Support parsing PCI controller DT subnodes
The PCI controller can have DT subnodes describing extra properties
of particular PCI devices, ie. a PHY attached to an EHCI controller
on a PCI bus. This patch parses those DT subnodes and assigns a node
to the PCI device instance, so that the driver can extract details
from that node and ie. configure the PHY using the PHY subsystem.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-20 15:23:38 -04:00
Simon Glass
595aac9824 pci: Add a little more debugging to pci_rom
Add some logging on failure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-09 04:40:27 -06:00
Masahiro Yamada
dee37fc99d Remove <inttypes.h> includes and PRI* usages in printf() entirely
In int-ll64.h, we always use the following typedefs:

  typedef unsigned int         u32;
  typedef unsigned long        uintptr_t;
  typedef unsigned long long   u64;

This does not need to match to the compiler's <inttypes.h>.
Do not include it.

The use of PRI* makes the code super-ugly.  You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:17 -04:00
Marek Vasut
313360b13f pci: rmobile: Filter out device 1 and 2
Only PCI device 1 and 2 is populated on the R-Car Gen2 internal
PCIe controller. Ignore all other devices. This fix prevents a
duplication of OHCI controller response on slot 0 and 1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-08-28 11:01:52 +02:00
Tom Rini
b8a1f47be3 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-08-13 12:34:55 -04:00
Joakim Tjernlund
6ce83fb3d6 FSL PCI: Configure PCIe reference ratio
Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.

This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-08 08:23:48 -07:00
Bin Meng
dac01fd89d dm: pci: Add APIs to find capability and extended capability
This introduces two new APIs dm_pci_find_capability() and
dm_pci_find_ext_capability() to get PCI capability address and
PCI express extended capability address for a given PCI device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
841f3216c2 pci: sandbox: emul: Rename priv structure
We have "struct sandbox_pci_priv" in pci_sandbox driver. To avoid
confusion, rename the emul's priv to "struct sandbox_pci_emul_priv".

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
4345998ae9 pci: sandbox: Support dynamically binding device driver
At present all emulated sandbox pci devices must be present in the
device tree in order to be used. The real world pci uclass driver
supports pci device driver matching, and we should add such support
on sandbox too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
ed698aa7de dm: pci: Assign correct driver data when binding a driver
The correct driver data comes from the matching 'id' instead of
'find_id' in pci_find_and_bind_driver().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
b3f96b4f99 pci: sandbox: emul: Fix the call to pci_bus_find_devfn()
With the newly added test cases for PCI configuration access, we get:

  => ut dm pci_busdev
  Test: dm_test_pci_busdev: pci.c
  test/dm/pci.c:49, dm_test_pci_busdev(): SANDBOX_PCI_VENDOR_ID == vendor:
  Expected 4660, got 65535
  Test: dm_test_pci_busdev: pci.c (flat tree)
  test/dm/pci.c:49, dm_test_pci_busdev(): SANDBOX_PCI_VENDOR_ID == vendor:
  Expected 4660, got 65535
  Failures: 2

The bug only shows up when bus number is not equal to zero. This is
caused by the plain find_devfn parameter is passed to function call
pci_bus_find_devfn(), inside which find_devfn is compared to devfn
in the device's pplat structure. However pplat->devfn does not carry
the bus number. Fix this by passing find_devfn with bus number masked.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
64e45f73bd dm: pci: Fix scanning multi-function device
The flag to control whether to scan multi-function device during
enumeration should be cleared at the beginning of each iteration
if the device's function number equals to zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
1f6b08b969 dm: pci: Extract vendor/device id in child_post_bind()
Currently only devfn is extracted in child_post_bind(). Now that
we have the live-tree version API to look up PCI vendor and device
id from the compatible string, let's extract and save them too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Christian Gmeiner
6f95d89c71 dm: pci: Use a 1:1 mapping for bus <-> phy addresses
If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.

This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Christian Gmeiner
f2825f6ec0 dm: pci: Make ranges dt property optional
If we use U-Boot as coreboot payload with a generic dts without
any ranges specified we fail in pci pre_probe and our pci bus
is not usable.

So convert decode_regions(..) into a void function and do the simple
error handling there.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message and checkpatch warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Tuomas Tynkkynen
d71975ae6e PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources
Currently, if we happen to allocate an address requiring 64 bits to a
device only supporting 32-bit BARs, the address eventually gets silently
truncated to 32 bits. Avoid this by adding a new flag to
pciauto_region_allocate() to bail out in such situations.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
ed12a89d07 PCI: Add newlines to debug prints in pci_auto_common.c
All of the debug output from this file is squished to one line. Fix
it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
52ba907328 PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set
Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with
the 'highmem=off' parameter passed to QEMU's virt machine. The reason is
that when 'highmem' is not disabled, QEMU appends 64-bit a memory
resource to the PCI controller's regions property in DT in addition to
the 32-bit PCI memory window in low memory. And the current DT parsing
code picks the last (thus the 64-bit one) memory resource, whose address
eventually gets silently truncated to 32 bits because
CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break.

Avoid this problem by ignoring memory regions whose addresses are above
the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Marcel Ziswiler
355560d588 pci: tegra: introduce weak tegra_pcie_board_port_reset() function
Introduce a weak tegra_pcie_board_port_reset() function by default
calling the existing tegra_pcie_port_reset() function. Additionally add
a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe
port index if required. This allows overriding the PCIe port reset
functionality from board specific code as e.g. required for Apalis T30
and Apalis TK1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:21 -07:00
Mario Six
e097ce4304 pci: Don't use pci_indirect when DM is active
Declaration of indirect PCI bridges is not compatible with DM: Both
define PCI operations, but in different ways. Hence, don't use indirect
bridges if DM is active.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08 18:50:23 -04:00
Ley Foon Tan
7c45862f22 pci: intel: Add Intel FPGA PCIe controller driver
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in
rootport mode only, the EP mode is not supported. The driver is tested
with the Intel e1000e NIC driver.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-08 09:07:35 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Bin Meng
611309383d pci: video: Only print out when everything is OK
If video initialization fails, the "Video:" output message will be
mixed with the next console log. Change to print out such message
only when everything is OK, which improves the boot log readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-16 22:38:52 +08:00
Tom Rini
f3b623fa52 Merge git://git.denx.de/u-boot-marvell 2018-03-30 18:18:22 -04:00
Wilson Ding
e51f2b14c4 arm64: a37xx: pci: add support for aardvark pcie driver
This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30 12:52:49 +02:00
Igal Liberman
b8478fcd04 dm: pcie: designware: add correct ATU handling
Currently, ATU (address translation unit) implementation doesn't
support translate addresses > 32 bits.

This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.

Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30 12:52:48 +02:00
Bin Meng
ee1109bb45 dm: pci: Avoid setting a PCI region that has 0 size
It makes no sense to set a PCI region that has 0 size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30 16:05:08 +08:00
Bin Meng
1eaf7800b6 dm: pci: Check board information pointer in decode_regions()
PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.

With this commit, Intel Galileo board boots again.

Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30 16:05:08 +08:00
Masahiro Yamada
b08c8c4870 libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -> include/linux/libfdt.h
  include/libfdt_env.h     -> include/linux/libfdt_env.h

and replaces include directives:
  #include <libfdt.h>      -> #include <linux/libfdt.h>
  #include <libfdt_env.h>  -> #include <linux/libfdt_env.h>

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-05 10:16:28 -05:00
Bernhard Messerklinger
664758c3dd pci: Fix decode regions for memory banks
Since memory banks may not be located behind each other we need to add
them separately.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2018-02-23 10:40:50 -05:00
Marek Vasut
5f14f7d783 pci: rmobile: Add RCar Gen2 PCIe controller driver
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-01-27 20:38:53 +01:00
Koen Vandeputte
f57263ee9b drivers: pci: imx: fix enumeration logic error
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.

This means that theoretically, the highest bus reachable downstream is
bus 1.

Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.

Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
2018-01-12 14:28:04 +01:00
Peng Fan
67b71df277 pci: imx: request gpio before use
Before use GPIO, we need to request gpio first. Free gpio after use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-12 14:28:04 +01:00
Tuomas Tynkkynen
55acf49eab PCI: Drop CONFIG_TSI108_PCI
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-01-10 08:05:49 -05:00
Paul Burton
c5bf161fac Update Paul Burton's email address
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Minghuan Lian
3977dcd559 dm: pci: change bus number register setting compliant with Linux
This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-17 10:53:45 -05:00
VlaoMao
49b23e035d pci: mvebu: Increase size of PCIe default mapping
Increase size PCI memory mapping from 32MiB to 128MiB.

Signed-off-by: VlaoMao <vlaomao@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-16 11:43:15 +01:00
Sven-Ola Tuecke
b2915ba25e drivers: pci: imx: fix imx_pcie_remove function
We have at least a minor count of boards, that failed to re-initialize
PCI express in the Linux kernel. Typical failure rate is 20% on affected
boards. This is mitigated by commit 6ecbe13756 ("drivers: pci: imx:
add imx_pcie_remove function").

However, at least on some i.MX6 custom boards, when calling
assert_core_reset() as part of the first-time PCIe init, read access
to PCIE_PL_PFLR simply hangs. Surround this readl() with
imx_pcie_fix_dabt_handler() does not help. For this reason, the forced
LTSSM detection is only used on the second assert_core_reset() that is
called shorly before starting the Linux kernel.

Signed-off-by: Sven-Ola Tuecke <sven-ola.tuecke@numberfour.eu>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: David Müller <d.mueller@elsoft.ch>
2017-10-12 17:56:28 +02:00
Tuomas Tynkkynen
3675cb044e PCI: Add driver for a 'pci-host-ecam-generic' host controller
QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:28:12 -04:00
Tuomas Tynkkynen
e434a90ec4 pci: layerscape: Use pci_generic_mmap_{read, write}_config
Use the new helpers to avoid boilerplate in the driver.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:27:41 -04:00
Tuomas Tynkkynen
75e3feac1b pci: xilinx: Use pci_generic_mmap_{read, write}_config()
Use the new helper function to avoid boilerplate in the driver.

Note that this changes __raw_writel et al. to writel. AFAICT this is
no problem because:

- The Linux driver for the same hardware uses the non-__raw variants as
  well (via pci_generic_config_write()).
- This driver seems to be used only on MIPS so far, where the __raw and
  non-__raw accessors are the same.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:27:41 -04:00
Tuomas Tynkkynen
badb99220a pci: Add helper for implementing memory-mapped config space accesses
This sort of pattern for implementing memory-mapped PCI config space
accesses appears in U-Boot twice already, and a third user is coming up.
So add helper functions to avoid code duplication, similar to how Linux
has pci_generic_config_write and pci_generic_config_read.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:27:40 -04:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Bharat Bhushan
4b97a82442 pci: layerscape: Fixup iommu-map for LS208xA
Commit 0aaa1a9 added support for LS208xA devices but fixing
iommu-map property is missing. This patch adds support for
fixing iommu-map.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:42:29 -07:00
Tuomas Tynkkynen
44913a185f pci: Remove unnecessary 'default n' from Kconfig
'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:56 -04:00
Tuomas Tynkkynen
93b1431f1a pci: layerscape: Remove unused field 'hose' from struct ls_pcie
This field is no longer used since the DM conversion. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00
Tuomas Tynkkynen
be0105bc1e pci: tegra: Remove unused field 'hose' from struct tegra_pcie
This field is no longer used since the DM conversion. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00
Tuomas Tynkkynen
bee278de81 pci: xilinx: Remove unused field 'hose' from struct xilinx_pcie
This field has never been used as the driver has been DM-based since the
beginning. Drop it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22 07:39:55 -04:00