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pci: xilinx: Use pci_generic_mmap_{read, write}_config()
Use the new helper function to avoid boilerplate in the driver. Note that this changes __raw_writel et al. to writel. AFAICT this is no problem because: - The Linux driver for the same hardware uses the non-__raw variants as well (via pci_generic_config_write()). - This driver seems to be used only on MIPS so far, where the __raw and non-__raw accessors are the same. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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1 changed files with 7 additions and 46 deletions
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@ -41,7 +41,7 @@ static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
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/**
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* pcie_xilinx_config_address() - Calculate the address of a config access
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* @pcie: Pointer to the PCI controller state
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* @udev: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @paddress: Pointer to the pointer to write the calculates address to
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@ -55,9 +55,10 @@ static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
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*
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* Return: 0 on success, else -ENODEV
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*/
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static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf,
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static int pcie_xilinx_config_address(struct udevice *udev, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct xilinx_pcie *pcie = dev_get_priv(udev);
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int func = PCI_FUNC(bdf);
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@ -101,29 +102,8 @@ static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct xilinx_pcie *pcie = dev_get_priv(bus);
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void *address;
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int err;
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err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
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if (err < 0) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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switch (size) {
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case PCI_SIZE_8:
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*valuep = __raw_readb(address);
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return 0;
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case PCI_SIZE_16:
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*valuep = __raw_readw(address);
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return 0;
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case PCI_SIZE_32:
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*valuep = __raw_readl(address);
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return 0;
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default:
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return -EINVAL;
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}
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return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
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bdf, offset, valuep, size);
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}
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/**
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@ -144,27 +124,8 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct xilinx_pcie *pcie = dev_get_priv(bus);
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void *address;
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int err;
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err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
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if (err < 0)
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return 0;
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switch (size) {
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case PCI_SIZE_8:
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__raw_writeb(value, address);
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return 0;
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case PCI_SIZE_16:
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__raw_writew(value, address);
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return 0;
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case PCI_SIZE_32:
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__raw_writel(value, address);
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return 0;
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default:
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return -EINVAL;
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}
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return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
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bdf, offset, value, size);
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}
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/**
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