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pci: pci-uclass: Add support for Single-Root I/O Virtualization
SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Suneel Garapati
Stefan Roese
parent
636cc1773a
commit
b8852dcfcb
3 changed files with 162 additions and 0 deletions
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@ -53,6 +53,16 @@ config PCI_REGION_MULTI_ENTRY
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region type. This helps to add support for SoC's like OcteonTX/TX2
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where every peripheral is on the PCI bus.
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config PCI_SRIOV
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bool "Enable Single Root I/O Virtualization support for PCI"
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depends on PCI || DM_PCI
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default n
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help
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Say Y here if you want to enable PCI Single Root I/O Virtualization
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capability support. This helps to enumerate Virtual Function devices
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if available on a PCI Physical Function device and probe for
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applicable drivers.
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config PCIE_ECAM_GENERIC
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bool "Generic ECAM-based PCI host controller support"
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default n
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@ -1586,6 +1586,120 @@ int dm_pci_flr(struct udevice *dev)
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return 0;
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}
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#if defined(CONFIG_PCI_SRIOV)
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int pci_sriov_init(struct udevice *pdev, int vf_en)
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{
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u16 vendor, device;
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struct udevice *bus;
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struct udevice *dev;
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pci_dev_t bdf;
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u16 ctrl;
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u16 num_vfs;
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u16 total_vf;
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u16 vf_offset;
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u16 vf_stride;
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int vf, ret;
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int pos;
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pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
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if (!pos) {
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debug("Error: SRIOV capability not found\n");
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return -ENOENT;
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}
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
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if (vf_en > total_vf)
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vf_en = total_vf;
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dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
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ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
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dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
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if (num_vfs > vf_en)
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num_vfs = vf_en;
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
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dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
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bdf = dm_pci_get_bdf(pdev);
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pci_get_bus(PCI_BUS(bdf), &bus);
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if (!bus)
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return -ENODEV;
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bdf += PCI_BDF(0, 0, vf_offset);
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for (vf = 0; vf < num_vfs; vf++) {
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struct pci_child_platdata *pplat;
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ulong class;
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pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
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&class, PCI_SIZE_16);
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debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
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bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
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/* Find this device in the device tree */
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ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
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if (ret == -ENODEV) {
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struct pci_device_id find_id;
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memset(&find_id, '\0', sizeof(find_id));
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find_id.vendor = vendor;
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find_id.device = device;
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find_id.class = class;
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ret = pci_find_and_bind_driver(bus, &find_id,
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bdf, &dev);
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if (ret)
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return ret;
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}
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/* Update the platform data */
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pplat = dev_get_parent_platdata(dev);
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pplat->devfn = PCI_MASK_BUS(bdf);
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pplat->vendor = vendor;
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pplat->device = device;
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pplat->class = class;
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pplat->is_virtfn = true;
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pplat->pfdev = pdev;
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pplat->virtid = vf * vf_stride + vf_offset;
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debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
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__func__, dev->seq, dev->name, PCI_DEV(bdf),
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PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
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bdf += PCI_BDF(0, 0, vf_stride);
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}
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return 0;
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}
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int pci_sriov_get_totalvfs(struct udevice *pdev)
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{
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u16 total_vf;
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int pos;
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pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
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if (!pos) {
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debug("Error: SRIOV capability not found\n");
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return -ENOENT;
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}
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dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
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return total_vf;
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}
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#endif /* SRIOV */
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UCLASS_DRIVER(pci) = {
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.id = UCLASS_PCI,
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.name = "pci",
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@ -493,6 +493,17 @@
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#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
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#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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/* Single Root I/O Virtualization Registers */
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
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#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
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#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
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#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
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#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
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#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
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#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
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#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
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#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
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/* Include the ID list */
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@ -890,12 +901,20 @@ struct udevice;
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* @vendor: PCI vendor ID (see pci_ids.h)
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* @device: PCI device ID (see pci_ids.h)
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* @class: PCI class, 3 bytes: (base, sub, prog-if)
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* @is_virtfn: True for Virtual Function device
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* @pfdev: Handle to Physical Function device
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* @virtid: Virtual Function Index
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*/
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struct pci_child_platdata {
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int devfn;
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unsigned short vendor;
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unsigned short device;
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unsigned int class;
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/* Variables for CONFIG_PCI_SRIOV */
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bool is_virtfn;
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struct udevice *pfdev;
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int virtid;
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};
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/* PCI bus operations */
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@ -1208,6 +1227,25 @@ int pci_generic_mmap_read_config(
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ulong *valuep,
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enum pci_size_t size);
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#if defined(CONFIG_PCI_SRIOV)
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/**
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* pci_sriov_init() - Scan Virtual Function devices
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*
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* @pdev: Physical Function udevice handle
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* @vf_en: Number of Virtual Function devices to enable
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* @return 0 on success, -ve on error
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*/
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int pci_sriov_init(struct udevice *pdev, int vf_en);
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/**
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* pci_sriov_get_totalvfs() - Get total available Virtual Function devices
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*
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* @pdev: Physical Function udevice handle
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* @return count on success, -ve on error
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*/
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int pci_sriov_get_totalvfs(struct udevice *pdev);
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#endif
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#ifdef CONFIG_DM_PCI_COMPAT
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/* Compatibility with old naming */
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static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
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