We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
The declarations should not be in common.h. Move them to the arch-specific
headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>
Loading PPA in SPL puts the rest of U-Boot (including RAM version
loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded,
PSCI is available.
Signed-off-by: York Sun <york.sun@nxp.com>
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Layerscape Chassis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation
as they are behind SMMU.
This patch defines the stream-ids for Chassis-2 devices. DPAA1 is
reserved for future use.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared
same stream-id partitioning. This patch rewords the definition to
support all these SOCs.
Also have changes in description about iommu-map property updates
in PCI node.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The stream ID allocation for Chasis 3.0 devices can be shared among
LS1088, LS2088 and LS2080.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.
So Avoid RCWSR28 register hard-coding.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Moved the ifdef into ppa.h and removed the duplicated macros.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@nxp.com>
Cc: Alison Wang <b18965@freescale.com>
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different
Add new function adjust_vdd() for LSCH3 compliant SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun <york.sun@nxp.com>
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.
Signed-off-by: York Sun <york.sun@nxp.com>
This moves all of the current ARM errata from various header files and in to
Kconfig. This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config. We now just select these once at the higher level in Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.
The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.
If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.
Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.
The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.
This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Clear the content to zero and the ECC error bit of OCRAM1/2.
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For the function alloc_stream_ids() append_mmu_masters() and
fdt_fixup_smmu_pcie() there are no related definitions and they
are never called. So the patch removes the unnecessary declares.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT
in Kconfig. Drop this macro for LSCH2 and remove from white list.
Signed-off-by: York Sun <york.sun@nxp.com>
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.
Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: York Sun <york.sun@nxp.com>
