u-boot/arch/arm/include/asm/arch-fsl-layerscape
York Sun ef9a5fd864 armv8: fsl-layerscape: Fix "cpu status" command
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.

Tested on LS2080ARDB and LS1043ARDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-10-06 09:56:57 -07:00
..
clock.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
config.h Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig option 2016-09-26 08:53:07 -07:00
cpu.h armv8: fsl_lsch2: Add LS1046A SoC support 2016-07-26 09:02:23 -07:00
fdt.h armv8/ls1043aqds: add LS1043AQDS board support 2015-11-30 09:11:10 -08:00
fsl_serdes.h fsl: serdes: ensure accessing the initialized maps of serdes protocol 2016-09-14 14:06:49 -07:00
immap_lsch2.h armv8: fsl-lsch2: enable snoopable sata read and write 2016-10-06 09:52:59 -07:00
immap_lsch3.h armv8: ls2080a: Remove debug server support 2016-09-14 14:07:19 -07:00
imx-regs.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
ls2080a_stream_id.h armv8: ls2080a: update stream ID partitioning info 2016-03-21 12:42:12 -07:00
mmu.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
mp.h armv8: fsl-layerscape: Fix "cpu status" command 2016-10-06 09:56:57 -07:00
ns_access.h fsl: csu: add an API to set R/W permission to PCIe 2016-09-14 14:07:08 -07:00
ppa.h ARMv8/layerscape: Add FSL PPA support 2016-07-19 11:33:53 -07:00
soc.h armv8: fsl-lsch2: enable snoopable sata read and write 2016-10-06 09:52:59 -07:00
speed.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00