Commit graph

80061 commits

Author SHA1 Message Date
Pali Rohár
20fb58fc5a board: freescale: p1_p2_rdb_pc: Implement board_reset()
Do board reset via CPLD's system reset register.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Pali Rohár
ae0e7ee886 board: freescale: p1_p2_rdb_pc: Enable TDM function only for P1010
TDM function is supported only on P1010. P2020 does not have PMUXCR_TDM_ENA
register, so do not enable it.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Pali Rohár
549bb6b237 powerpc: mpc85xx: Fix compilation with CONFIG_WDT
When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to
conflicting functions like watchdog_reset(). So disable compilation of
mpc85xx watchdog_reset() function when CONFIG_WDT is enabled.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Pali Rohár
26f6f7188b powerpc: dts: p2020: Define ecm, memory and guts nodes
Copy definition of these nodes from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Pali Rohár
f0bb612d5b powerpc: dts: p2020: Define DMA nodes
Copy definition of DMA nodes from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Pali Rohár
99f17774b7 powerpc: dts: p2020: Define crypto node
Copy definition of crypto node from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Pali Rohár
1cb0f98f91 powerpc: dts: p2020: Define MPIC nodes
Copy definition of MPIC nodes from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Sean Anderson
bcb3dae325 ARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDB
These frequency calculations depend on the RCW format, which is not
dependent on any particular board. Switch to using ARCH symbols instead
of TARGET.

This whole function could probably use less ifdefs, but for now just do
a minimal conversion.

Fixes: 24cb6f2295 ("fsl-layerscape: Add fsl_esdhc peripheral clock support")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:26 +08:00
Sean Anderson
7041601141 arch: layerscape: Add SFP binding
This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:26 +08:00
Sean Anderson
f99068a8b1 ARM: dts: ls1021a: update the clockgen node
QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).

This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:26 +08:00
Sean Anderson
2645bc0e12 arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.

The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.

The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.

I suggest using the following procedure for programming:

1. Override the fuses you wish to program
   => fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
   => fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
   write-protect bit you will usually want to write it last anyway.
   => fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
   => fuse read 0 2 4

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:25 +08:00
Tom Rini
98c4828740 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next 2022-06-16 09:27:43 -04:00
Peng Fan
e8780d2380 imx: phycore_imx8mm/p: clean up board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
2022-06-14 21:33:14 +02:00
Peng Fan
4152ea24f2 imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-06-14 21:33:14 +02:00
Peng Fan
722e2b9a2b imx: imx8mp_rsb7320a1: enable wdog driver model in SPL
Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
ae75489c48 imx: imx8mn_var_som: clean up board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
2022-06-14 21:33:14 +02:00
Peng Fan
cbda080ae9 imx: imx8mn-beacon: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
6692cd967d imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
333a6fa12f imx: engicam-imx8mm: drop unused macro
Drop unused WDOG macro

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-06-14 21:33:14 +02:00
Peng Fan
2d7f40cad5 imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
ee106eda7e imx: imx8mm_beacon: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:13 +02:00
Peng Fan
ca3369df71 configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE
CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace
CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop
CONFIG_SPL_ABORT_ON_RAW_IMAGE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:13 +02:00
Peng Fan
0a16da8079 imx: kontron-sl-mx8mm: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-06-14 21:33:13 +02:00
Peng Fan
bb9e14cfd0 imx: imx8mn_var_som: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:33:13 +02:00
Peng Fan
64d118b27f imx: imx8m[m/p]_phycore: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:33:13 +02:00
Peng Fan
4ebb9a5898 imx: imx8mm_icore: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:33:13 +02:00
Peng Fan
37750505b9 imx: imx8mm-cl-iot-gate: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:33:13 +02:00
Peng Fan
d35130fef8 imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn_beacon
2022-06-14 21:33:13 +02:00
Peng Fan
0e1b54247d imx: drop CONFIG_MXC_UART_BASE
Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL,
the legacy macro no need to be defined.

Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Soeren Moch <smoch@web.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2022-06-14 21:33:13 +02:00
Tom Rini
a87a6fcd20 Merge branch '2022-06-10-assorted-platform-updates' into next
- TI J721E hyperflash support, TI OMAP3 updates, TI AM654 updates,
  TI AM62 initial support, Broadcom bcmbca 47622 SoC support, NPCM7xx
  pinctrl and rng drivers, Synquacer updates
2022-06-10 16:02:42 -04:00
Vignesh Raghavendra
e16aac3b73 doc: ti: Add readme for AM62x SK
Add info of boot flow and build steps for AM62x SK.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2022-06-10 13:37:33 -04:00
Vignesh Raghavendra
2d257d9279 configs: Add configs for AM62x SK
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for
A53 SPL and U-Boot support.

To keep the changes to minimum. Only UART And SD boot related configs
are included. This should serve as good starting point for new board
bringup with AM62x.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[trini: Migrate a number of CONFIG symbols, have re-tested]
Tested-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:33 -04:00
Nishanth Menon
3e48d37f48 arm: dts: Add support for AM62-SK
AM62 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM625 SoC. It supports the following interfaces:
* 2 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display
* x1 Headphone Jack
* x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x4 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 20-pin header for Programmable Realtime Unit (PRU) IO pins
* 15-pin CSI header

Add basic support for AM62-SK.

To keep the changes to minimum. Only UART And SD are supported at the
moment. This should serve as good example for adding new board support
based on AM62x SoC

Schematics: https://www.ti.com/lit/zip/sprr448

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:33 -04:00
Suman Anna
900349b7dd board: ti: Introduce the basic files to support AM62 SK board
Add basic support for AM62 SK. This has 2GB DDR.
Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from
BSS and does not step on BSS section

Add only the bare minimum required to support UART and SD.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:33 -04:00
Suman Anna
1b2f4697c0 arm: dts: Introduce base AM62 SoC dtsi files
Introduce the basic AM62 SoC description dtsi files describing most
peripherals as per kernel dts.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:33 -04:00
Vignesh Raghavendra
7e9e386773 firmware: ti_sci_static_data: add static DMA chan data
Add range of DMA channels available for R5 SPL usage before DM firmware
is loaded.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:32 -04:00
Vignesh Raghavendra
720d37ff27 dma: ti: Add PSIL data for AM62x DMASS
Add PSIL data for AM62x SoC.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:32 -04:00
Suman Anna
4b8903a999 arm: mach-k3: am62: Introduce autogenerated SoC data
Introduce autogenerated SoC data support clk and device data for the
AM62. Hook it upto to power-domain and clk frameworks of U-Boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:32 -04:00
Suman Anna
d98e860051 arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.

Some highlights of this SoC are:

* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
  Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
  OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
  resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
  in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
  interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
  external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
  1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
  Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
  enabling battery powered system design.

AM625 is the first device of the family. Add DT bindings for the same.

More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:32 -04:00
Suman Anna
4298ee7e40 soc: ti: k3-socinfo: Add entry for AM62X SoC family
Add support for AM62x SoC identification.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:32 -04:00
Suman Anna
8a6d273343 dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
Add pinctrl macros for AM62x SoCs. These macro definitions are similar
to that of previous platforms, but adding new definitions to avoid any
naming confusions in the SoC dts files.

checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses

However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
 done for other similar platforms.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
ed6d781469 drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC
The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-10 13:37:32 -04:00
Jim Liu
866eab1d28 rng: nuvoton: Add NPCM7xx rng driver
Add Nuvoton BMC NPCM750 rng driver.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
b5d3625f27 configs: am65_evm_r5_usb*_defconfig: Sync the checks for size of image and stack from generic r5 defconfig
Sync the configs required for enabling checks for size of image and stack
from generic r5 defconfig file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
36dafd8045 arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
750d8470cb arm: dts: k3-am654-r5-base-board: Fix the dt properties in usb0 instance
For dfu boot mode, the clocks property needs to be deleted and dr_mode
needs to be set to peripheral. Therefore, add the required fixes for the
same.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-06-10 13:37:32 -04:00
Masahisa Kojima
f81aaa0b33 spi: synquacer: simplify tx completion checking
There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10 13:37:32 -04:00
Masahisa Kojima
de9f2c9c2e spi: synquacer: DMSTART bit must not be set while transferring
DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10 13:37:32 -04:00
Masahisa Kojima
88d50ed8a1 spi: synquacer: wait until slave is deselected
synquacer_cs_set() function does not wait the chip select
is deasserted when the driver sets the DMSTOP to deselect
the slave.
This commit checks the Slave Select Released(SRS) bit to wait
until the slave is deselected.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10 13:37:32 -04:00
Masahisa Kojima
29d382b94e spi: synquacer: busy variable must be initialized before use
"busy" variable is ORed without being initialized,
must be zeroed before use.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10 13:37:32 -04:00