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imx: imx8mm-cl-iot-gate: Enable DM_SERIAL

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Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Peng Fan 2022-06-11 20:20:56 +08:00 committed by Stefano Babic
parent d35130fef8
commit 37750505b9
4 changed files with 4 additions and 12 deletions
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12
board/compulab/imx8mm-cl-iot-gate/spl.c
View file

@ -83,14 +83,8 @@ int board_fit_config_name_match(const char *name)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@ -103,8 +97,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
@ -155,8 +147,6 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -166,6 +156,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);

1
configs/imx8mm-cl-iot-gate-optee_defconfig
View file

@ -121,6 +121,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/imx8mm-cl-iot-gate_defconfig
View file

@ -124,6 +124,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

2
include/configs/imx8mm-cl-iot-gate.h
View file

@ -134,8 +134,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2