mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 08:59:33 +00:00
Merge branch '2022-06-10-assorted-platform-updates' into next
- TI J721E hyperflash support, TI OMAP3 updates, TI AM654 updates, TI AM62 initial support, Broadcom bcmbca 47622 SoC support, NPCM7xx pinctrl and rng drivers, Synquacer updates
This commit is contained in:
Tom Rini
commit
a87a6fcd20
85 changed files with 7352 additions and 31 deletions
11
MAINTAINERS
11
MAINTAINERS
|
|
@ -206,6 +206,17 @@ F: drivers/pinctrl/broadcom/
|
|||
F: configs/rpi_*
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||||
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
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||||
|
||||
ARM BROADCOM BCMBCA
|
||||
M: Anand Gore <anand.gore@broadcom.com>
|
||||
M: William Zhang <william.zhang@broadcom.com>
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||||
M: Kursad Oney <kursad.oney@broadcom.com>
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||||
M: Joel Peshkin <joel.peshkin@broadcom.com>
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||||
S: Maintained
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||||
F: arch/arm/mach-bcmbca/
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F: board/broadcom/bcmbca/
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F: configs/bcm947622_defconfig
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||||
F: include/configs/bcm947622.h
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||||
|
||||
ARM BROADCOM BCMSTB
|
||||
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
|
||||
S: Maintained
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||||
|
|
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|||
|
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@ -718,6 +718,11 @@ config ARCH_BCMSTB
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|||
This enables support for Broadcom ARM-based set-top box
|
||||
chipsets, including the 7445 family of chips.
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||||
|
||||
config ARCH_BCMBCA
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||||
bool "Broadcom broadband chip family"
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select DM
|
||||
select OF_CONTROL
|
||||
|
||||
config TARGET_VEXPRESS_CA9X4
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bool "Support vexpress_ca9x4"
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||||
select CPU_V7A
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||||
|
|
@ -2187,6 +2192,8 @@ source "arch/arm/mach-at91/Kconfig"
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|||
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||||
source "arch/arm/mach-bcm283x/Kconfig"
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||||
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||||
source "arch/arm/mach-bcmbca/Kconfig"
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||||
|
||||
source "arch/arm/mach-bcmstb/Kconfig"
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||||
|
||||
source "arch/arm/mach-davinci/Kconfig"
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||||
|
|
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|||
|
|
@ -59,6 +59,7 @@ machine-$(CONFIG_ARCH_APPLE) += apple
|
|||
machine-$(CONFIG_ARCH_ASPEED) += aspeed
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||||
machine-$(CONFIG_ARCH_AT91) += at91
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||||
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
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||||
machine-$(CONFIG_ARCH_BCMBCA) += bcmbca
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machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
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machine-$(CONFIG_ARCH_DAVINCI) += davinci
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machine-$(CONFIG_ARCH_EXYNOS) += exynos
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|
|
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|||
|
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@ -1154,6 +1154,9 @@ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
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|||
|
||||
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
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||||
|
||||
dtb-$(CONFIG_BCM47622) += \
|
||||
bcm947622.dtb
|
||||
|
||||
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
|
||||
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
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||||
|
||||
|
|
@ -1195,6 +1198,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
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k3-am642-sk.dtb \
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||||
k3-am642-r5-sk.dtb
|
||||
|
||||
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
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k3-am625-r5-sk.dtb
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||||
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||||
dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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||||
mt7623a-unielec-u7623-02-emmc.dtb \
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||||
|
|
|
|||
126
arch/arm/dts/bcm47622.dtsi
Normal file
126
arch/arm/dts/bcm47622.dtsi
Normal file
|
|
@ -0,0 +1,126 @@
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|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
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||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
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||||
#include <dt-bindings/interrupt-controller/irq.h>
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||||
|
||||
/ {
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compatible = "brcm,bcm47622", "brcm,bcmbca";
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#address-cells = <1>;
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#size-cells = <1>;
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||||
|
||||
interrupt-parent = <&gic>;
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||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
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||||
enable-method = "psci";
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||||
};
|
||||
CA7_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
CA7_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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arm,cpu-registers-not-fw-configured;
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||||
};
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||||
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||||
pmu: pmu {
|
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compatible = "arm,cortex-a7-pmu";
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||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>,
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||||
<&CA7_2>, <&CA7_3>;
|
||||
};
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||||
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||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
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||||
clock-frequency = <200000000>;
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||||
};
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||||
uart_clk: uart-clk {
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||||
compatible = "fixed-factor-clock";
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||||
#clock-cells = <0>;
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||||
clocks = <&periph_clk>;
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||||
clock-div = <4>;
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||||
clock-mult = <1>;
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||||
};
|
||||
};
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||||
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||||
psci {
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compatible = "arm,psci-0.2";
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||||
method = "smc";
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||||
cpu_off = <1>;
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||||
cpu_on = <2>;
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||||
};
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||||
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||||
axi@81000000 {
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||||
compatible = "simple-bus";
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||||
#address-cells = <1>;
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||||
#size-cells = <1>;
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||||
ranges = <0 0x81000000 0x818000>;
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||||
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||||
gic: interrupt-controller@1000 {
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||||
compatible = "arm,cortex-a7-gic";
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||||
#interrupt-cells = <3>;
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||||
#address-cells = <0>;
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interrupt-controller;
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||||
reg = <0x1000 0x1000>,
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||||
<0x2000 0x2000>;
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||||
};
|
||||
};
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||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
30
arch/arm/dts/bcm947622.dts
Normal file
30
arch/arm/dts/bcm947622.dts
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm47622.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM947622 Reference Board";
|
||||
compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
11
arch/arm/dts/k3-am62-ddr.dtsi
Normal file
11
arch/arm/dts/k3-am62-ddr.dtsi
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am64-ddr.dtsi"
|
||||
&memorycontroller {
|
||||
power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
|
||||
<&k3_pds 55 TI_SCI_PD_SHARED>;
|
||||
clocks = <&k3_clks 170 0>, <&k3_clks 16 4>;
|
||||
};
|
||||
533
arch/arm/dts/k3-am62-main.dtsi
Normal file
533
arch/arm/dts/k3-am62-main.dtsi
Normal file
|
|
@ -0,0 +1,533 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC Family Main Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_main {
|
||||
oc_sram: sram@70000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x70000000 0x00 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x70000000 0x10000>;
|
||||
};
|
||||
|
||||
gic500: interrupt-controller@1800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
|
||||
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
|
||||
<0x01 0x00000000 0x00 0x2000>, /* GICC */
|
||||
<0x01 0x00010000 0x00 0x1000>, /* GICH */
|
||||
<0x01 0x00020000 0x00 0x2000>; /* GICV */
|
||||
/*
|
||||
* vcpumntirq:
|
||||
* virtual CPU interface maintenance interrupt
|
||||
*/
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gic_its: msi-controller@1820000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x00 0x01820000 0x00 0x10000>;
|
||||
socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
main_conf: syscon@100000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x00100000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x00100000 0x20000>;
|
||||
|
||||
phy_gmii_sel: phy@4044 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4044 0x8>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
dmss: bus@48000000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges;
|
||||
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
|
||||
|
||||
ti,sci-dev-id = <25>;
|
||||
|
||||
secure_proxy_main: mailbox@4d000000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x00 0x4d000000 0x00 0x80000>,
|
||||
<0x00 0x4a600000 0x00 0x80000>,
|
||||
<0x00 0x4a400000 0x00 0x80000>;
|
||||
interrupt-names = "rx_012";
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
inta_main_dmss: interrupt-controller@48000000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x00 0x48000000 0x00 0x100000>;
|
||||
#interrupt-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <28>;
|
||||
ti,interrupt-ranges = <4 68 36>;
|
||||
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
|
||||
};
|
||||
|
||||
main_bcdma: dma-controller@485c0100 {
|
||||
compatible = "ti,am64-dmss-bcdma";
|
||||
reg = <0x00 0x485c0100 0x00 0x100>,
|
||||
<0x00 0x4c000000 0x00 0x20000>,
|
||||
<0x00 0x4a820000 0x00 0x20000>,
|
||||
<0x00 0x4aa40000 0x00 0x20000>,
|
||||
<0x00 0x4bc00000 0x00 0x100000>;
|
||||
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <3>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <26>;
|
||||
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
|
||||
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
|
||||
};
|
||||
|
||||
main_pktdma: dma-controller@485c0000 {
|
||||
compatible = "ti,am64-dmss-pktdma";
|
||||
reg = <0x00 0x485c0000 0x00 0x100>,
|
||||
<0x00 0x4a800000 0x00 0x20000>,
|
||||
<0x00 0x4aa00000 0x00 0x40000>,
|
||||
<0x00 0x4b800000 0x00 0x400000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <30>;
|
||||
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
|
||||
<0x24>, /* CPSW_TX_CHAN */
|
||||
<0x25>, /* SAUL_TX_0_CHAN */
|
||||
<0x26>; /* SAUL_TX_1_CHAN */
|
||||
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
|
||||
<0x11>, /* RING_CPSW_TX_CHAN */
|
||||
<0x12>, /* RING_SAUL_TX_0_CHAN */
|
||||
<0x13>; /* RING_SAUL_TX_1_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
|
||||
<0x2b>, /* CPSW_RX_CHAN */
|
||||
<0x2d>, /* SAUL_RX_0_CHAN */
|
||||
<0x2f>, /* SAUL_RX_1_CHAN */
|
||||
<0x31>, /* SAUL_RX_2_CHAN */
|
||||
<0x33>; /* SAUL_RX_3_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
|
||||
<0x2c>, /* FLOW_CPSW_RX_CHAN */
|
||||
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
|
||||
<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
|
||||
};
|
||||
};
|
||||
|
||||
dmsc: system-controller@44043000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
mbox-names = "rx", "tx";
|
||||
mboxes= <&secure_proxy_main 12>,
|
||||
<&secure_proxy_main 13>;
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x00 0x44043000 0x00 0xfe0>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
main_pmx0: pinctrl@f4000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x00 0xf4000 0x00 0x2ac>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 146 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 152 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 153 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 154 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 155 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 156 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 158 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_i2c0: i2c@20000000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20000000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 102 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c1: i2c@20010000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20010000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 103 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c2: i2c@20020000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20020000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 104 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c3: i2c@20030000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 172 0>;
|
||||
};
|
||||
|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 173 0>;
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 174 0>;
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <3>;
|
||||
ti,interrupt-ranges = <0 32 16>;
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <190>, <191>, <192>,
|
||||
<193>, <194>, <195>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <87>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 77 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio1: gpio@601000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00601000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <180>, <181>, <182>,
|
||||
<183>, <184>, <185>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <88>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 78 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
sdhci0: mmc@fa10000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
assigned-clocks = <&k3_clks 57 6>;
|
||||
assigned-clock-parents = <&k3_clks 57 8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
ti,trm-icp = <0x2>;
|
||||
bus-width = <8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x9>;
|
||||
ti,otap-del-sel-hs200 = <0x6>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@fa00000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci2: mmc@fa20000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
};
|
||||
|
||||
fss: bus@fc00000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x00 0x0fc00000 0x00 0x70000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ospi0: spi@fc40000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x00 0x0fc40000 0x00 0x100>,
|
||||
<0x05 0x00000000 0x01 0x00000000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
clocks = <&k3_clks 75 7>;
|
||||
assigned-clocks = <&k3_clks 75 7>;
|
||||
assigned-clock-parents = <&k3_clks 75 8>;
|
||||
assigned-clock-rates = <166666666>;
|
||||
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g: ethernet@8000000 {
|
||||
compatible = "ti,am642-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x00 0x08000000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
assigned-clocks = <&k3_clks 13 3>;
|
||||
assigned-clock-parents = <&k3_clks 13 11>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_pktdma 0xc600 15>,
|
||||
<&main_pktdma 0xc601 15>,
|
||||
<&main_pktdma 0xc602 15>,
|
||||
<&main_pktdma 0xc603 15>,
|
||||
<&main_pktdma 0xc604 15>,
|
||||
<&main_pktdma 0xc605 15>,
|
||||
<&main_pktdma 0xc606 15>,
|
||||
<&main_pktdma 0xc607 15>,
|
||||
<&main_pktdma 0x4600 15>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
||||
"tx7", "rx";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-efuse = <&wkup_conf 0x200>;
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
reg = <2>;
|
||||
ti,mac-only;
|
||||
label = "port2";
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 13 1>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@2a000000 {
|
||||
compatible = "ti,am64-hwspinlock";
|
||||
reg = <0x00 0x2a000000 0x00 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mailbox0_cluster0: mailbox@29000000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29000000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
};
|
||||
56
arch/arm/dts/k3-am62-mcu.dtsi
Normal file
56
arch/arm/dts/k3-am62-mcu.dtsi
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_pmx0: pinctrl@4084000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x00 0x04084000 0x00 0x88>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@4900000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04900000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b00000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b10000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
};
|
||||
41
arch/arm/dts/k3-am62-wakeup.dtsi
Normal file
41
arch/arm/dts/k3-am62-wakeup.dtsi
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
wkup_conf: syscon@43000000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x43000000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x43000000 0x20000>;
|
||||
|
||||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_uart0: serial@2b300000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x2b300000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@2b200000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x02b200000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 4>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
105
arch/arm/dts/k3-am62.dtsi
Normal file
105
arch/arm/dts/k3-am62.dtsi
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM62 SoC Family
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM625 SoC";
|
||||
compatible = "ti,am625";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f0000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
|
||||
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
|
||||
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
|
||||
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
|
||||
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
|
||||
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
|
||||
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
|
||||
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
|
||||
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
|
||||
|
||||
/* Wakeup Domain Range */
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
||||
};
|
||||
|
||||
cbass_wakeup: bus@2b000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am62-main.dtsi"
|
||||
#include "k3-am62-mcu.dtsi"
|
||||
#include "k3-am62-wakeup.dtsi"
|
||||
140
arch/arm/dts/k3-am625-r5-sk.dts
Normal file
140
arch/arm/dts/k3-am625-r5-sk.dts
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* AM625 SK dts file for R5 SPL
|
||||
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am625-sk.dts"
|
||||
#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
|
||||
#include "k3-am62-ddr.dtsi"
|
||||
|
||||
#include "k3-am625-sk-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
remoteproc0 = &sysctrler;
|
||||
remoteproc1 = &a53_0;
|
||||
serial0 = &wkup_uart0;
|
||||
serial3 = &main_uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
a53_0: a53@0 {
|
||||
compatible = "ti,am654-rproc";
|
||||
reg = <0x00 0x00a90000 0x00 0x10>;
|
||||
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
||||
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
|
||||
resets = <&k3_reset 135 0>;
|
||||
clocks = <&k3_clks 61 0>;
|
||||
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 61 2>;
|
||||
assigned-clock-rates = <200000000>, <1200000000>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-proc-id = <32>;
|
||||
ti,sci-host-id = <10>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
dm_tifs: dm-tifs {
|
||||
compatible = "ti,j721e-dm-sci";
|
||||
ti,host-id = <36>;
|
||||
ti,secure-host;
|
||||
mbox-names = "rx", "tx";
|
||||
mboxes= <&secure_proxy_main 22>,
|
||||
<&secure_proxy_main 23>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
<&secure_proxy_main 0>;
|
||||
mbox-names = "rx", "tx", "notify";
|
||||
ti,host-id = <35>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
sa3_secproxy: secproxy@44880000 {
|
||||
u-boot,dm-spl;
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "rt", "scfg", "target_data";
|
||||
reg = <0x00 0x44880000 0x00 0x20000>,
|
||||
<0x0 0x44860000 0x0 0x20000>,
|
||||
<0x0 0x43600000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>;
|
||||
mbox-names = "tx", "rx", "boot_notify";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
wkup_uart0_pins_default: wkup-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
|
||||
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
|
||||
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
|
||||
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
|
||||
>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
|
||||
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
|
||||
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
|
||||
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
|
||||
>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
/* WKUP UART0 is used for DM firmware logs */
|
||||
&wkup_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
status = "okay";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
/* Main UART1 is used for TIFS firmware logs */
|
||||
&main_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
status = "okay";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
100
arch/arm/dts/k3-am625-sk-u-boot.dtsi
Normal file
100
arch/arm/dts/k3-am625-sk-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Common AM625 SK dts file for SPLs
|
||||
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
|
||||
timer1: timer@2400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x00 0x2400000 0x00 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <25000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&dmss {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_conf {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&chipid {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_uart0_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&mcu_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_mmc1_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
150
arch/arm/dts/k3-am625-sk.dts
Normal file
150
arch/arm/dts/k3-am625-sk.dts
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* AM625 SK: https://www.ti.com/lit/zip/sprr448
|
||||
*
|
||||
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am625.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am625-sk", "ti,am625";
|
||||
model = "Texas Instruments AM625 SK";
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
|
||||
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
|
||||
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
|
||||
AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
|
||||
AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
|
||||
AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
|
||||
AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
|
||||
AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* WKUP UART0 is used by DM firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* Main UART1 is used by TIFS firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
103
arch/arm/dts/k3-am625.dtsi
Normal file
103
arch/arm/dts/k3-am625.dtsi
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC family in Quad core configuration
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruiv7
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
2189
arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
Normal file
2189
arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -198,7 +198,7 @@
|
|||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_pins_default>;
|
||||
dr_mode = "host";
|
||||
dr_mode = "peripheral";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -309,6 +309,7 @@
|
|||
&dwc3_0 {
|
||||
status = "okay";
|
||||
u-boot,dm-spl;
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
|
|
|
|||
|
|
@ -192,6 +192,22 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&hbmc {
|
||||
u-boot,dm-spl;
|
||||
|
||||
flash@0,0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&hbmc_mux {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
u-boot,dm-spl;
|
||||
|
||||
|
|
@ -208,6 +224,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mcu_fss0_hpb0_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_gpio_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&mcu_fss0_ospi1_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -213,6 +213,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
wkup_gpio_pins_default: wkup-gpio-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
|
||||
|
|
@ -381,6 +387,11 @@
|
|||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_gpio_pins_default>;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss1_pins_default>;
|
||||
|
|
|
|||
|
|
@ -170,12 +170,30 @@
|
|||
};
|
||||
|
||||
fss: fss@47000000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x47000000 0x0 0x100>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
hbmc_mux: hbmc-mux {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4 0x2>; /* HBMC select */
|
||||
};
|
||||
|
||||
hbmc: hyperbus@47034000 {
|
||||
compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
|
||||
reg = <0x0 0x47034000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
assigned-clocks = <&k3_clks 102 0>;
|
||||
assigned-clock-rates = <250000000>;
|
||||
};
|
||||
|
||||
ospi0: spi@47040000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
|
|
|
|||
|
|
@ -129,6 +129,31 @@
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
|
||||
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
|
||||
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
|
||||
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
|
||||
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
|
||||
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
|
||||
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
|
||||
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
|
||||
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
|
||||
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
|
||||
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
|
||||
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
||||
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
||||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
};
|
||||
|
||||
wkup_gpio_pins_default: wkup-gpio-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
|
||||
|
|
@ -207,6 +232,11 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_gpio_pins_default>;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ clocks;
|
||||
|
|
@ -307,6 +337,21 @@
|
|||
};
|
||||
};
|
||||
|
||||
&hbmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
<0x0 0x50000000 0x0 0x8000000>;
|
||||
ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
|
||||
<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
|
|
|||
|
|
@ -150,6 +150,25 @@
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
|
||||
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
|
||||
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
|
||||
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
|
||||
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
|
||||
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
|
||||
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
|
||||
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
|
||||
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
|
||||
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
|
||||
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
|
||||
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
||||
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
||||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
|
||||
|
|
@ -167,6 +186,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
&hbmc {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
||||
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
|
||||
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
|
|
|||
17
arch/arm/mach-bcmbca/Kconfig
Normal file
17
arch/arm/mach-bcmbca/Kconfig
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2022 Broadcom Ltd
|
||||
#
|
||||
|
||||
if ARCH_BCMBCA
|
||||
|
||||
config BCM47622
|
||||
bool "Support for Broadcom 47622 Family"
|
||||
select SYS_ARCH_TIMER
|
||||
select CPU_V7A
|
||||
select DM_SERIAL
|
||||
select PL01X_SERIAL
|
||||
|
||||
endif
|
||||
|
||||
source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
|
||||
6
arch/arm/mach-bcmbca/Makefile
Normal file
6
arch/arm/mach-bcmbca/Makefile
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2022 Broadcom Ltd
|
||||
#
|
||||
|
||||
obj-$(CONFIG_BCM47622) += bcm47622/
|
||||
17
arch/arm/mach-bcmbca/bcm47622/Kconfig
Normal file
17
arch/arm/mach-bcmbca/bcm47622/Kconfig
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2022 Broadcom Ltd
|
||||
#
|
||||
|
||||
if BCM47622
|
||||
|
||||
config TARGET_BCM947622
|
||||
bool "Broadcom 47622 Reference Board"
|
||||
depends on ARCH_BCMBCA
|
||||
|
||||
config SYS_SOC
|
||||
default "bcm47622"
|
||||
|
||||
source "board/broadcom/bcmbca/Kconfig"
|
||||
|
||||
endif
|
||||
5
arch/arm/mach-bcmbca/bcm47622/Makefile
Normal file
5
arch/arm/mach-bcmbca/bcm47622/Makefile
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2022 Broadcom Ltd
|
||||
#
|
||||
obj- += dummy.o
|
||||
|
|
@ -16,6 +16,9 @@ config SOC_K3_J721S2
|
|||
config SOC_K3_AM642
|
||||
bool "TI's K3 based AM642 SoC Family Support"
|
||||
|
||||
config SOC_K3_AM625
|
||||
bool "TI's K3 based AM625 SoC Family Support"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
|
|
@ -26,6 +29,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
|
|||
default 0x80000 if SOC_K3_AM6
|
||||
default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
|
||||
default 0x1c0000 if SOC_K3_AM642
|
||||
default 0x3c000 if SOC_K3_AM625
|
||||
help
|
||||
Describes the total size of the MCU or OCMC MSRAM present on
|
||||
the SoC in use. This doesn't specify the total size of SPL as
|
||||
|
|
@ -37,6 +41,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
|
|||
default 0x58000 if SOC_K3_AM6
|
||||
default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
|
||||
default 0x180000 if SOC_K3_AM642
|
||||
default 0x38000 if SOC_K3_AM625
|
||||
help
|
||||
Describes the maximum size of the image that ROM can download
|
||||
from any boot media.
|
||||
|
|
@ -61,6 +66,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
|
|||
default 0x41cffbfc if SOC_K3_J721E
|
||||
default 0x41cfdbfc if SOC_K3_J721S2
|
||||
default 0x701bebfc if SOC_K3_AM642
|
||||
default 0x43c3f290 if SOC_K3_AM625
|
||||
help
|
||||
Address at which ROM stores the value which determines if SPL
|
||||
is booted up by primary boot media or secondary boot media.
|
||||
|
|
@ -129,6 +135,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
|
|||
config K3_SYSFW_IMAGE_SIZE_MAX
|
||||
int "Amount of memory dynamically allocated for loading SYSFW blob"
|
||||
depends on K3_LOAD_SYSFW
|
||||
default 163840 if SOC_K3_AM625
|
||||
default 278000
|
||||
help
|
||||
Amount of memory (in bytes) reserved through dynamic allocation at
|
||||
|
|
@ -160,7 +167,7 @@ config K3_ATF_LOAD_ADDR
|
|||
|
||||
config K3_DM_FW
|
||||
bool "Separate DM firmware image"
|
||||
depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
|
||||
depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
|
||||
default y
|
||||
help
|
||||
Enabling this will indicate that the system has separate DM
|
||||
|
|
@ -171,6 +178,7 @@ config K3_DM_FW
|
|||
|
||||
source "board/ti/am65x/Kconfig"
|
||||
source "board/ti/am64x/Kconfig"
|
||||
source "board/ti/am62x/Kconfig"
|
||||
source "board/ti/j721e/Kconfig"
|
||||
source "board/siemens/iot2050/Kconfig"
|
||||
source "board/ti/j721s2/Kconfig"
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
|
|||
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
|
||||
obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
|
||||
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
|
||||
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o am62x/
|
||||
obj-$(CONFIG_ARM64) += arm64-mmu.o
|
||||
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
|
||||
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
|
||||
|
|
|
|||
271
arch/arm/mach-k3/am625_init.c
Normal file
271
arch/arm/mach-k3/am625_init.c
Normal file
|
|
@ -0,0 +1,271 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* AM625: SoC specific initialization
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*/
|
||||
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/sysfw-loader.h>
|
||||
#include "common.h"
|
||||
#include <dm.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/pinctrl.h>
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
|
||||
/*
|
||||
* This uninitialized global variable would normal end up in the .bss section,
|
||||
* but the .bss is cleared between writing and reading this variable, so move
|
||||
* it to the .data section.
|
||||
*/
|
||||
u32 bootindex __section(".data");
|
||||
static struct rom_extended_boot_data bootdata __section(".data");
|
||||
|
||||
static void store_boot_info_from_rom(void)
|
||||
{
|
||||
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
||||
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
|
||||
sizeof(struct rom_extended_boot_data));
|
||||
}
|
||||
|
||||
static void ctrl_mmr_unlock(void)
|
||||
{
|
||||
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
|
||||
|
||||
/* Unlock all CTRL_MMR0 module registers */
|
||||
mmr_unlock(CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 4);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 6);
|
||||
|
||||
/* Unlock all MCU_CTRL_MMR0 module registers */
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
|
||||
|
||||
/* Unlock PADCFG_CTRL_MMR padconf registers */
|
||||
mmr_unlock(PADCFG_MMR0_BASE, 1);
|
||||
mmr_unlock(PADCFG_MMR1_BASE, 1);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
#if defined(CONFIG_CPU_V7R)
|
||||
setup_k3_mpu_regions();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cannot delay this further as there is a chance that
|
||||
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
||||
*/
|
||||
store_boot_info_from_rom();
|
||||
|
||||
ctrl_mmr_unlock();
|
||||
|
||||
/* Init DM early */
|
||||
spl_early_init();
|
||||
|
||||
/*
|
||||
* Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
|
||||
* MAIN_UART1 modules and continue regardless of the result of pinctrl.
|
||||
* Do this without probing the device, but instead by searching the
|
||||
* device that would request the given sequence number if probed. The
|
||||
* UARTs will be used by the DM firmware and TIFS firmware images
|
||||
* respectively and the firmware depend on SPL to initialize the pin
|
||||
* settings.
|
||||
*/
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
|
||||
if (!ret)
|
||||
pinctrl_select_state(dev, "default");
|
||||
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
|
||||
if (!ret)
|
||||
pinctrl_select_state(dev, "default");
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
#ifdef CONFIG_K3_EARLY_CONS
|
||||
/*
|
||||
* Allow establishing an early console as required for example when
|
||||
* doing a UART-based boot. Note that this console may not "survive"
|
||||
* through a SYSFW PM-init step and will need a re-init in some way
|
||||
* due to changing module clock frequencies.
|
||||
*/
|
||||
early_console_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_K3_LOAD_SYSFW)
|
||||
/*
|
||||
* Configure and start up system controller firmware. Provide
|
||||
* the U-Boot console init function to the SYSFW post-PM configuration
|
||||
* callback hook, effectively switching on (or over) the console
|
||||
* output.
|
||||
*/
|
||||
ret = is_rom_loaded_sysfw(&bootdata);
|
||||
if (!ret)
|
||||
panic("ROM has not loaded TIFS firmware\n");
|
||||
|
||||
k3_sysfw_loader(true, NULL, NULL);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Force probe of clk_k3 driver here to ensure basic default clock
|
||||
* configuration is always done.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(ti_clk),
|
||||
&dev);
|
||||
if (ret)
|
||||
printf("Failed to initialize clk-k3!\n");
|
||||
}
|
||||
|
||||
/* Output System Firmware version info */
|
||||
k3_sysfw_print_ver();
|
||||
|
||||
#if defined(CONFIG_K3_AM64_DDRSS)
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret)
|
||||
panic("DRAM init failed: %d\n", ret);
|
||||
#endif
|
||||
}
|
||||
|
||||
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
||||
{
|
||||
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
||||
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
switch (boot_device) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT)
|
||||
return MMCSD_MODE_EMMCBOOT;
|
||||
return MMCSD_MODE_FS;
|
||||
|
||||
case BOOT_DEVICE_MMC2:
|
||||
return MMCSD_MODE_FS;
|
||||
|
||||
default:
|
||||
return MMCSD_MODE_RAW;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 __get_backup_bootmedia(u32 devstat)
|
||||
{
|
||||
u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
|
||||
MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
|
||||
u32 bkup_bootmode_cfg =
|
||||
(devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
switch (bkup_bootmode) {
|
||||
case BACKUP_BOOT_DEVICE_UART:
|
||||
return BOOT_DEVICE_UART;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_USB:
|
||||
return BOOT_DEVICE_USB;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_ETHERNET:
|
||||
return BOOT_DEVICE_ETHERNET;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_MMC:
|
||||
if (bkup_bootmode_cfg)
|
||||
return BOOT_DEVICE_MMC2;
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_SPI:
|
||||
return BOOT_DEVICE_SPI;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_I2C:
|
||||
return BOOT_DEVICE_I2C;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_DFU:
|
||||
if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
|
||||
return BOOT_DEVICE_USB;
|
||||
return BOOT_DEVICE_DFU;
|
||||
};
|
||||
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
static u32 __get_primary_bootmedia(u32 devstat)
|
||||
{
|
||||
u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
|
||||
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
switch (bootmode) {
|
||||
case BOOT_DEVICE_OSPI:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_QSPI:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_XSPI:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_SPI:
|
||||
return BOOT_DEVICE_SPI;
|
||||
|
||||
case BOOT_DEVICE_ETHERNET_RGMII:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_ETHERNET_RMII:
|
||||
return BOOT_DEVICE_ETHERNET;
|
||||
|
||||
case BOOT_DEVICE_EMMC:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
||||
case BOOT_DEVICE_MMC:
|
||||
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
|
||||
return BOOT_DEVICE_MMC2;
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
||||
case BOOT_DEVICE_DFU:
|
||||
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
|
||||
return BOOT_DEVICE_USB;
|
||||
return BOOT_DEVICE_DFU;
|
||||
|
||||
case BOOT_DEVICE_NOBOOT:
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
return bootmode;
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
||||
u32 bootmedia;
|
||||
|
||||
if (bootindex == K3_PRIMARY_BOOTMODE)
|
||||
bootmedia = __get_primary_bootmedia(devstat);
|
||||
else
|
||||
bootmedia = __get_backup_bootmedia(devstat);
|
||||
|
||||
debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
|
||||
__func__, devstat, bootmedia, bootindex);
|
||||
|
||||
return bootmedia;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
6
arch/arm/mach-k3/am62x/Makefile
Normal file
6
arch/arm/mach-k3/am62x/Makefile
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
|
||||
obj-y += clk-data.o
|
||||
obj-y += dev-data.o
|
||||
366
arch/arm/mach-k3/am62x/clk-data.c
Normal file
366
arch/arm/mach-k3/am62x/clk-data.c
Normal file
|
|
@ -0,0 +1,366 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* AM62X specific clock platform data
|
||||
*
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Dave Gerlach <d-gerlach@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include "k3-clk.h"
|
||||
|
||||
static const char * const gluelogic_hfosc0_clkout_parents[] = {
|
||||
NULL,
|
||||
NULL,
|
||||
"osc_24_mhz",
|
||||
"osc_25_mhz",
|
||||
"osc_26_mhz",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
|
||||
"board_0_mmc0_clklb_out",
|
||||
"board_0_mmc0_clk_out",
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
|
||||
"board_0_mmc1_clklb_out",
|
||||
"board_0_mmc1_clk_out",
|
||||
};
|
||||
|
||||
static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
|
||||
"board_0_ospi0_dqs_out",
|
||||
"board_0_ospi0_lbclko_out",
|
||||
};
|
||||
|
||||
static const char * const main_usb0_refclk_sel_out0_parents[] = {
|
||||
"gluelogic_hfosc0_clkout",
|
||||
"postdiv4_16ff_main_0_hsdivout8_clk",
|
||||
};
|
||||
|
||||
static const char * const main_usb1_refclk_sel_out0_parents[] = {
|
||||
"gluelogic_hfosc0_clkout",
|
||||
"postdiv4_16ff_main_0_hsdivout8_clk",
|
||||
};
|
||||
|
||||
static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
|
||||
"gluelogic_hfosc0_clkout",
|
||||
"hsdiv4_16fft_main_0_hsdivout0_clk",
|
||||
};
|
||||
|
||||
static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
|
||||
"gluelogic_hfosc0_clkout",
|
||||
"hsdiv4_16fft_mcu_0_hsdivout0_clk",
|
||||
};
|
||||
|
||||
static const char * const clkout0_ctrl_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_2_hsdivout1_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout1_clk",
|
||||
};
|
||||
|
||||
static const char * const clk_32k_rc_sel_out0_parents[] = {
|
||||
"gluelogic_rcosc_clk_1p0v_97p65k",
|
||||
"hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
|
||||
"clk_32k_rc_sel_div_clkout",
|
||||
"gluelogic_lfosc0_clkout",
|
||||
};
|
||||
|
||||
static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_2_hsdivout5_clk",
|
||||
"postdiv4_16ff_main_0_hsdivout6_clk",
|
||||
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||
NULL,
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
|
||||
"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_0_hsdivout5_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||
};
|
||||
|
||||
static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_0_hsdivout5_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||
};
|
||||
|
||||
static const char * const main_gtcclk_sel_out0_parents[] = {
|
||||
"postdiv4_16ff_main_2_hsdivout5_clk",
|
||||
"postdiv4_16ff_main_0_hsdivout6_clk",
|
||||
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||
NULL,
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
|
||||
"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_0_hsdivout1_clk",
|
||||
"postdiv1_16fft_main_1_hsdivout5_clk",
|
||||
};
|
||||
|
||||
static const char * const wkup_clkout_sel_out0_parents[] = {
|
||||
"gluelogic_hfosc0_clkout",
|
||||
"gluelogic_lfosc0_clkout",
|
||||
"hsdiv4_16fft_main_0_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_1_hsdivout2_clk",
|
||||
"postdiv4_16ff_main_2_hsdivout9_clk",
|
||||
"clk_32k_rc_sel_out0",
|
||||
"gluelogic_rcosc_clkout",
|
||||
"gluelogic_hfosc0_clkout",
|
||||
};
|
||||
|
||||
static const char * const wkup_clksel_out0_parents[] = {
|
||||
"hsdiv1_16fft_main_15_hsdivout0_clk",
|
||||
"hsdiv4_16fft_mcu_0_hsdivout0_clk",
|
||||
};
|
||||
|
||||
static const char * const main_usart0_fclk_sel_out0_parents[] = {
|
||||
"usart_programmable_clock_divider_out0",
|
||||
"hsdiv4_16fft_main_1_hsdivout1_clk",
|
||||
};
|
||||
|
||||
static const struct clk_data clk_list[] = {
|
||||
CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
|
||||
CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
|
||||
CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
|
||||
CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
|
||||
CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
|
||||
CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
|
||||
CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
|
||||
CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
|
||||
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
|
||||
CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
|
||||
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||
CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
|
||||
CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
|
||||
CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
|
||||
CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
|
||||
CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
|
||||
CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
|
||||
CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
|
||||
CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
|
||||
CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
|
||||
CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
|
||||
CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
|
||||
CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
|
||||
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
|
||||
CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
|
||||
CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
|
||||
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
|
||||
CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
|
||||
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
|
||||
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
|
||||
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
|
||||
CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
|
||||
CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
|
||||
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
|
||||
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
|
||||
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
|
||||
CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
|
||||
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
|
||||
CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
|
||||
CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
|
||||
CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
|
||||
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
|
||||
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
|
||||
CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
|
||||
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
|
||||
};
|
||||
|
||||
static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
|
||||
DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
|
||||
DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||
DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
|
||||
DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
|
||||
DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
|
||||
DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
|
||||
DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
|
||||
DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
|
||||
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
|
||||
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||
DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
|
||||
DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
|
||||
DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
|
||||
DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
|
||||
DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
|
||||
DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
|
||||
DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
|
||||
DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
|
||||
DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||
DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
|
||||
DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
|
||||
DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
|
||||
DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
|
||||
DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
|
||||
DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||
DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
|
||||
DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
|
||||
DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||
DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(61, 9, "wkup_clksel_out0"),
|
||||
DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
|
||||
DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
|
||||
DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
|
||||
DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
|
||||
DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
|
||||
DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
|
||||
DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
|
||||
DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
|
||||
DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
|
||||
DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
|
||||
DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(95, 2, "wkup_clksel_out0"),
|
||||
DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
|
||||
DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
|
||||
DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
|
||||
DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
|
||||
DEV_CLK(107, 0, "wkup_clksel_out0"),
|
||||
DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
|
||||
DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
|
||||
DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
|
||||
DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
|
||||
DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
|
||||
DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
|
||||
DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
|
||||
DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 20, "clkout0_ctrl_out0"),
|
||||
DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||
DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
|
||||
DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
|
||||
DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
|
||||
DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
|
||||
DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
|
||||
DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
|
||||
DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
|
||||
DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
|
||||
DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
|
||||
DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
|
||||
DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
|
||||
DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
|
||||
DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
|
||||
DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
|
||||
DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
|
||||
DEV_CLK(161, 10, "board_0_tck_out"),
|
||||
DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
|
||||
DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
|
||||
DEV_CLK(162, 10, "board_0_tck_out"),
|
||||
DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
|
||||
DEV_CLK(170, 1, "board_0_tck_out"),
|
||||
DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
};
|
||||
|
||||
const struct ti_k3_clk_platdata am62x_clk_platdata = {
|
||||
.clk_list = clk_list,
|
||||
.clk_list_cnt = 90,
|
||||
.soc_dev_clk_data = soc_dev_clk_data,
|
||||
.soc_dev_clk_data_cnt = 137,
|
||||
};
|
||||
78
arch/arm/mach-k3/am62x/dev-data.c
Normal file
78
arch/arm/mach-k3/am62x/dev-data.c
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* AM62X specific device platform data
|
||||
*
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Dave Gerlach <d-gerlach@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-dev.h"
|
||||
|
||||
static struct ti_psc soc_psc_list[] = {
|
||||
[0] = PSC(0, 0x04000000),
|
||||
[1] = PSC(1, 0x00400000),
|
||||
};
|
||||
|
||||
static struct ti_pd soc_pd_list[] = {
|
||||
[0] = PSC_PD(0, &soc_psc_list[1], NULL),
|
||||
[1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
|
||||
[2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
|
||||
[3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
|
||||
[4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]),
|
||||
};
|
||||
|
||||
static struct ti_lpsc soc_lpsc_list[] = {
|
||||
[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
|
||||
[1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]),
|
||||
[3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]),
|
||||
[4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||
[5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]),
|
||||
[6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
|
||||
[12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]),
|
||||
[13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]),
|
||||
[14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]),
|
||||
[15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
|
||||
};
|
||||
|
||||
static struct ti_dev soc_dev_list[] = {
|
||||
PSC_DEV(16, &soc_lpsc_list[0]),
|
||||
PSC_DEV(77, &soc_lpsc_list[0]),
|
||||
PSC_DEV(61, &soc_lpsc_list[0]),
|
||||
PSC_DEV(95, &soc_lpsc_list[0]),
|
||||
PSC_DEV(107, &soc_lpsc_list[0]),
|
||||
PSC_DEV(170, &soc_lpsc_list[1]),
|
||||
PSC_DEV(177, &soc_lpsc_list[2]),
|
||||
PSC_DEV(55, &soc_lpsc_list[3]),
|
||||
PSC_DEV(178, &soc_lpsc_list[4]),
|
||||
PSC_DEV(179, &soc_lpsc_list[5]),
|
||||
PSC_DEV(57, &soc_lpsc_list[6]),
|
||||
PSC_DEV(58, &soc_lpsc_list[7]),
|
||||
PSC_DEV(161, &soc_lpsc_list[8]),
|
||||
PSC_DEV(162, &soc_lpsc_list[9]),
|
||||
PSC_DEV(75, &soc_lpsc_list[10]),
|
||||
PSC_DEV(102, &soc_lpsc_list[11]),
|
||||
PSC_DEV(146, &soc_lpsc_list[11]),
|
||||
PSC_DEV(13, &soc_lpsc_list[12]),
|
||||
PSC_DEV(166, &soc_lpsc_list[13]),
|
||||
PSC_DEV(135, &soc_lpsc_list[14]),
|
||||
PSC_DEV(136, &soc_lpsc_list[15]),
|
||||
};
|
||||
|
||||
const struct ti_k3_pd_platdata am62x_pd_platdata = {
|
||||
.psc = soc_psc_list,
|
||||
.pd = soc_pd_list,
|
||||
.lpsc = soc_lpsc_list,
|
||||
.devs = soc_dev_list,
|
||||
.num_psc = 2,
|
||||
.num_pd = 5,
|
||||
.num_lpsc = 16,
|
||||
.num_devs = 21,
|
||||
};
|
||||
|
|
@ -127,8 +127,8 @@ static int fixup_usb_boot(void)
|
|||
* before the dwc3 bind takes place
|
||||
*/
|
||||
ret = fdt_find_and_setprop((void *)gd->fdt_blob,
|
||||
"/interconnect@100000/dwc3@4000000/usb@10000",
|
||||
"dr_mode", "host", 11, 0);
|
||||
"/bus@100000/dwc3@4000000/usb@10000",
|
||||
"dr_mode", "host", 5, 0);
|
||||
if (ret)
|
||||
printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
|
||||
ret);
|
||||
|
|
|
|||
|
|
@ -222,7 +222,7 @@ struct mm_region *mem_map = j721s2_mem_map;
|
|||
|
||||
#endif /* CONFIG_SOC_K3_J721S2 */
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM642
|
||||
#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625))
|
||||
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
||||
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
|
||||
|
||||
|
|
@ -261,4 +261,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
|
|||
};
|
||||
|
||||
struct mm_region *mem_map = am64_mem_map;
|
||||
#endif /* CONFIG_SOC_K3_AM642 */
|
||||
#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */
|
||||
|
|
|
|||
75
arch/arm/mach-k3/include/mach/am62_hardware.h
Normal file
75
arch/arm/mach-k3/include/mach/am62_hardware.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* K3: AM62 SoC definitions, structures etc.
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_AM62_HARDWARE_H
|
||||
#define __ASM_ARCH_AM62_HARDWARE_H
|
||||
|
||||
#include <config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/bitops.h>
|
||||
#endif
|
||||
|
||||
#define PADCFG_MMR0_BASE 0x04080000
|
||||
#define PADCFG_MMR1_BASE 0x000f0000
|
||||
#define CTRL_MMR0_BASE 0x00100000
|
||||
#define MCU_CTRL_MMR0_BASE 0x04500000
|
||||
#define WKUP_CTRL_MMR0_BASE 0x43000000
|
||||
|
||||
#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
|
||||
|
||||
/* Primary Bootmode MMC Config macros */
|
||||
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
|
||||
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
|
||||
#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
|
||||
#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
|
||||
|
||||
/* Primary Bootmode USB Config macros */
|
||||
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
|
||||
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
|
||||
|
||||
/* Backup Bootmode USB Config macros */
|
||||
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
|
||||
|
||||
/*
|
||||
* The CTRL_MMR0 memory space is divided into several equally-spaced
|
||||
* partitions, so defining the partition size allows us to determine
|
||||
* register addresses common to those partitions.
|
||||
*/
|
||||
#define CTRL_MMR0_PARTITION_SIZE 0x4000
|
||||
|
||||
/*
|
||||
* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
|
||||
* shared register definitions. The same registers are also used for
|
||||
* PADCFG_MMR lock/kick-mechanism.
|
||||
*/
|
||||
#define CTRLMMR_LOCK_KICK0 0x1008
|
||||
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
|
||||
#define CTRLMMR_LOCK_KICK1 0x100c
|
||||
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
||||
|
||||
#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
|
||||
#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
|
||||
#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
|
||||
|
||||
#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
|
||||
#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
|
||||
|
||||
#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
|
||||
|
||||
/* Use Last 2K as Scratch pad */
|
||||
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000
|
||||
|
||||
#endif /* __ASM_ARCH_AM62_HARDWARE_H */
|
||||
48
arch/arm/mach-k3/include/mach/am62_spl.h
Normal file
48
arch/arm/mach-k3/include/mach/am62_spl.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_AM62_SPL_H_
|
||||
#define _ASM_ARCH_AM62_SPL_H_
|
||||
|
||||
/* Primary BootMode devices */
|
||||
#define BOOT_DEVICE_RAM 0x00
|
||||
#define BOOT_DEVICE_OSPI 0x01
|
||||
#define BOOT_DEVICE_QSPI 0x02
|
||||
#define BOOT_DEVICE_SPI 0x03
|
||||
#define BOOT_DEVICE_CPGMAC 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RGMII 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RMII 0x05
|
||||
#define BOOT_DEVICE_I2C 0x06
|
||||
#define BOOT_DEVICE_UART 0x07
|
||||
#define BOOT_DEVICE_MMC 0x08
|
||||
#define BOOT_DEVICE_EMMC 0x09
|
||||
|
||||
#define BOOT_DEVICE_USB 0x2A
|
||||
#define BOOT_DEVICE_DFU 0x0A
|
||||
#define BOOT_DEVICE_GPMC_NAND 0x0B
|
||||
#define BOOT_DEVICE_GPMC_NOR 0x0C
|
||||
#define BOOT_DEVICE_XSPI 0x0E
|
||||
#define BOOT_DEVICE_NOBOOT 0x0F
|
||||
|
||||
/* U-Boot used aliases */
|
||||
#define BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BOOT_DEVICE_MMC2 0x08
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
/* Invalid */
|
||||
#define BOOT_DEVICE_MMC2_2 0x1F
|
||||
|
||||
/* Backup BootMode devices */
|
||||
#define BACKUP_BOOT_DEVICE_DFU 0x01
|
||||
#define BACKUP_BOOT_DEVICE_UART 0x03
|
||||
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BACKUP_BOOT_DEVICE_MMC 0x05
|
||||
#define BACKUP_BOOT_DEVICE_SPI 0x06
|
||||
#define BACKUP_BOOT_DEVICE_I2C 0x07
|
||||
#define BACKUP_BOOT_DEVICE_USB 0x09
|
||||
|
||||
#define K3_PRIMARY_BOOTMODE 0x0
|
||||
|
||||
#endif /* _ASM_ARCH_AM62_SPL_H_ */
|
||||
|
|
@ -22,6 +22,10 @@
|
|||
#include "am64_hardware.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM625
|
||||
#include "am62_hardware.h"
|
||||
#endif
|
||||
|
||||
/* Assuming these addresses and definitions stay common across K3 devices */
|
||||
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
|
||||
#define JTAG_ID_VARIANT_SHIFT 28
|
||||
|
|
|
|||
|
|
@ -21,4 +21,9 @@
|
|||
#ifdef CONFIG_SOC_K3_AM642
|
||||
#include "am64_spl.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM625
|
||||
#include "am62_spl.h"
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARCH_SPL_H_ */
|
||||
|
|
|
|||
|
|
@ -346,6 +346,25 @@ static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t len)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(NOR_SUPPORT)
|
||||
static void *get_sysfw_hf_addr(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
fdt_addr_t addr;
|
||||
int ret;
|
||||
|
||||
ret = uclass_find_first_device(UCLASS_MTD, &dev);
|
||||
if (ret)
|
||||
return NULL;
|
||||
|
||||
addr = dev_read_addr_index(dev, 1);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return NULL;
|
||||
|
||||
return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
|
||||
}
|
||||
#endif
|
||||
|
||||
void k3_sysfw_loader(bool rom_loaded_sysfw,
|
||||
void (*config_pm_pre_callback)(void),
|
||||
void (*config_pm_done_callback)(void))
|
||||
|
|
@ -413,6 +432,15 @@ void k3_sysfw_loader(bool rom_loaded_sysfw,
|
|||
CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
|
||||
break;
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(NOR_SUPPORT)
|
||||
case BOOT_DEVICE_HYPERFLASH:
|
||||
sysfw_spi_base = get_sysfw_hf_addr();
|
||||
if (!sysfw_spi_base)
|
||||
ret = -ENODEV;
|
||||
k3_sysfw_spi_copy(sysfw_load_address, sysfw_spi_base,
|
||||
CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
|
||||
break;
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(YMODEM_SUPPORT)
|
||||
case BOOT_DEVICE_UART:
|
||||
#ifdef CONFIG_K3_EARLY_CONS
|
||||
|
|
|
|||
17
board/broadcom/bcmbca/Kconfig
Normal file
17
board/broadcom/bcmbca/Kconfig
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2022 Broadcom Ltd
|
||||
#
|
||||
|
||||
config SYS_BOARD
|
||||
default "bcmbca"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "broadcom"
|
||||
|
||||
if TARGET_BCM947622
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "bcm947622"
|
||||
|
||||
endif
|
||||
5
board/broadcom/bcmbca/Makefile
Normal file
5
board/broadcom/bcmbca/Makefile
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2022 Broadcom Ltd
|
||||
|
||||
obj-y += board.o
|
||||
35
board/broadcom/bcmbca/board.c
Normal file
35
board/broadcom/bcmbca/board.c
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
if (fdtdec_setup_mem_size_base() != 0)
|
||||
puts("fdtdec_setup_mem_size_base() has failed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
fdtdec_setup_memory_banksize();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
59
board/ti/am62x/Kconfig
Normal file
59
board/ti/am62x/Kconfig
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
# Suman Anna <s-anna@ti.com>
|
||||
|
||||
choice
|
||||
prompt "TI K3 AM62x based boards"
|
||||
optional
|
||||
|
||||
config TARGET_AM625_A53_EVM
|
||||
bool "TI K3 based AM625 EVM running on A53"
|
||||
select ARM64
|
||||
select SOC_K3_AM625
|
||||
|
||||
config TARGET_AM625_R5_EVM
|
||||
bool "TI K3 based AM625 EVM running on R5"
|
||||
select CPU_V7R
|
||||
select SYS_THUMB_BUILD
|
||||
select K3_LOAD_SYSFW
|
||||
select SOC_K3_AM625
|
||||
select RAM
|
||||
select SPL_RAM
|
||||
select K3_DDRSS
|
||||
imply SYS_K3_SPL_ATF
|
||||
|
||||
endchoice
|
||||
|
||||
if TARGET_AM625_A53_EVM
|
||||
|
||||
config SYS_BOARD
|
||||
default "am62x"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "ti"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "am62x_evm"
|
||||
|
||||
source "board/ti/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_AM625_R5_EVM
|
||||
|
||||
config SYS_BOARD
|
||||
default "am62x"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "ti"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "am62x_evm"
|
||||
|
||||
config SPL_LDSCRIPT
|
||||
default "arch/arm/mach-omap2/u-boot-spl.lds"
|
||||
|
||||
source "board/ti/common/Kconfig"
|
||||
|
||||
endif
|
||||
8
board/ti/am62x/MAINTAINERS
Normal file
8
board/ti/am62x/MAINTAINERS
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
AM62x BOARD
|
||||
M: Dave Gerlach <d-gerlach@ti.com>
|
||||
M: Tom Rini <trini@konsulko.com>
|
||||
S: Maintained
|
||||
F: board/ti/am62x/
|
||||
F: include/configs/am62x_evm.h
|
||||
F: configs/am62x_evm_r5_defconfig
|
||||
F: configs/am62x_evm_a53_defconfig
|
||||
8
board/ti/am62x/Makefile
Normal file
8
board/ti/am62x/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
# Suman Anna <s-anna@ti.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += evm.o
|
||||
39
board/ti/am62x/evm.c
Normal file
39
board/ti/am62x/evm.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Board specific initialization for AM62x platforms
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <spl.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <env.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = 0x80000000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
/* Bank 0 declares the memory available in the DDR low region */
|
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->bd->bi_dram[0].size = 0x80000000;
|
||||
gd->ram_size = 0x80000000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -159,6 +159,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
|
|||
int misc_init_r(void)
|
||||
{
|
||||
twl4030_power_init();
|
||||
twl4030_power_mmc_init(0);
|
||||
|
||||
#if defined(CONFIG_SMC911X)
|
||||
setup_net_chip();
|
||||
|
|
@ -247,10 +248,3 @@ static void reset_net_chip(void)
|
|||
gpio_set_value(rst_gpio, 1);
|
||||
}
|
||||
#endif /* CONFIG_SMC911X */
|
||||
|
||||
#if defined(CONFIG_MMC)
|
||||
void board_mmc_power_init(void)
|
||||
{
|
||||
twl4030_power_mmc_init(0);
|
||||
}
|
||||
#endif /* CONFIG_MMC */
|
||||
|
|
|
|||
|
|
@ -109,11 +109,12 @@ int board_fit_config_name_match(const char *name)
|
|||
static void __maybe_unused detect_enable_hyperflash(void *blob)
|
||||
{
|
||||
struct gpio_desc desc = {0};
|
||||
char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
|
||||
|
||||
if (dm_gpio_lookup_name("6", &desc))
|
||||
if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc))
|
||||
return;
|
||||
|
||||
if (dm_gpio_request(&desc, "6"))
|
||||
if (dm_gpio_request(&desc, hypermux_sel_gpio))
|
||||
return;
|
||||
|
||||
if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
|
||||
|
|
@ -132,7 +133,8 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||
#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
|
||||
defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
|
||||
void spl_perform_fixups(struct spl_image_info *spl_image)
|
||||
{
|
||||
detect_enable_hyperflash(spl_image->fdt_addr);
|
||||
|
|
@ -490,6 +492,41 @@ int board_late_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static int __maybe_unused detect_SW3_1_state(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) {
|
||||
struct gpio_desc desc = {0};
|
||||
int ret;
|
||||
char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
|
||||
|
||||
ret = dm_gpio_lookup_name(hypermux_sel_gpio, &desc);
|
||||
if (ret) {
|
||||
printf("error getting GPIO lookup name: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dm_gpio_request(&desc, hypermux_sel_gpio);
|
||||
if (ret) {
|
||||
printf("error requesting GPIO: %d\n", ret);
|
||||
goto err_free_gpio;
|
||||
}
|
||||
|
||||
ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
|
||||
if (ret) {
|
||||
printf("error setting direction flag of GPIO: %d\n", ret);
|
||||
goto err_free_gpio;
|
||||
}
|
||||
|
||||
ret = dm_gpio_get_value(&desc);
|
||||
if (ret < 0)
|
||||
printf("error getting value of GPIO: %d\n", ret);
|
||||
|
||||
err_free_gpio:
|
||||
dm_gpio_free(desc.dev, &desc);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
|
||||
|
|
@ -522,4 +559,18 @@ void spl_board_init(void)
|
|||
printf("ESM PMIC init failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&
|
||||
IS_ENABLED(CONFIG_HBMC_AM654)) {
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = detect_SW3_1_state();
|
||||
if (ret == 1) {
|
||||
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
||||
DM_DRIVER_GET(hbmc_am654),
|
||||
&dev);
|
||||
if (ret)
|
||||
debug("Failed to probe hyperflash\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
76
configs/am62x_evm_a53_defconfig
Normal file
76
configs/am62x_evm_a53_defconfig
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SOC_K3_AM625=y
|
||||
CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
|
||||
CONFIG_TARGET_AM625_A53_EVM=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_SPL_MAX_SIZE=0x58000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x80a00000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_TI_SCI=y
|
||||
CONFIG_TI_SCI_PROTOCOL=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ADMA=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_TI_K3=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_TI_SCI=y
|
||||
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
98
configs/am62x_evm_r5_defconfig
Normal file
98
configs/am62x_evm_r5_defconfig
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x9000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SOC_K3_AM625=y
|
||||
CONFIG_TARGET_AM625_R5_EVM=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk"
|
||||
CONFIG_SPL_TEXT_BASE=0x43c00000
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x40000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x58000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x43c37800
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x5000
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
|
||||
CONFIG_SPL_EARLY_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_REMOTEPROC=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_SPL_CLK_CCF=y
|
||||
CONFIG_SPL_CLK_K3_PLL=y
|
||||
CONFIG_SPL_CLK_K3=y
|
||||
CONFIG_TI_SCI_PROTOCOL=y
|
||||
CONFIG_DA8XX_GPIO=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ADMA=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_GENERIC is not set
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_POWER_DOMAIN=y
|
||||
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_TI_K3=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_SPL_TIMER=y
|
||||
CONFIG_OMAP_TIMER=y
|
||||
CONFIG_LIB_RATIONAL=y
|
||||
CONFIG_SPL_LIB_RATIONAL=y
|
||||
|
|
@ -16,6 +16,8 @@ CONFIG_SPL_TEXT_BASE=0x41c00000
|
|||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x7ec00
|
||||
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
|
|
@ -25,10 +27,13 @@ CONFIG_SPL_LOAD_FIT=y
|
|||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
|
||||
CONFIG_SPL_MAX_SIZE=0x58000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x41c7effc
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0xc00
|
||||
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@ CONFIG_SPL_TEXT_BASE=0x41c00000
|
|||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x7ec00
|
||||
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
|
|
@ -24,10 +26,13 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc
|
|||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
|
||||
CONFIG_SPL_MAX_SIZE=0x58000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x41c7effc
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0xc00
|
||||
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
|
|
|
|||
21
configs/bcm947622_defconfig
Normal file
21
configs/bcm947622_defconfig
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_BCMBCA=y
|
||||
CONFIG_SYS_TEXT_BASE=0x01000000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_BCM47622=y
|
||||
CONFIG_TARGET_BCM947622=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
|
||||
CONFIG_IDENT_STRING=" Broadcom BCM47622"
|
||||
CONFIG_SYS_LOAD_ADDR=0x01000000
|
||||
CONFIG_ENV_VARS_UBOOT_CONFIG=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_CLK=y
|
||||
|
|
@ -29,6 +29,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
|
|||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
|
|
@ -47,7 +48,9 @@ CONFIG_SPL_ENV_SUPPORT=y
|
|||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
|
|
@ -100,6 +103,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
|
|||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ CONFIG_SPL_LOAD_FIT=y
|
|||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
|
|
@ -49,7 +50,9 @@ CONFIG_SPL_ENV_SUPPORT=y
|
|||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
|
|
@ -72,6 +75,7 @@ CONFIG_CMD_REMOTEPROC=y
|
|||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
|
|
@ -84,6 +88,8 @@ CONFIG_SPL_DM=y
|
|||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -112,6 +118,13 @@ CONFIG_MMC_SDHCI=y
|
|||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_HBMC_AM654=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y
|
|||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
|
|
@ -10,6 +11,7 @@ CONFIG_SOC_K3_J721E=y
|
|||
CONFIG_TARGET_J721E_A72_EVM=y
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0x680000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
|
|
@ -30,6 +32,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
|
|||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_SPL_MAX_SIZE=0xc0000
|
||||
|
|
@ -45,7 +48,9 @@ CONFIG_SPL_ENV_SUPPORT=y
|
|||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||
|
|
@ -90,6 +95,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
|
|||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ CONFIG_SPL=y
|
|||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
|
||||
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run envboot; run distro_bootcmd"
|
||||
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then setenv boot mmc; setenv addr_fit 0x8b000000; run update_to_fit; run mmcboot; fi; run envboot; run distro_bootcmd"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
|
|
@ -55,7 +55,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
|
|
@ -63,8 +66,8 @@ CONFIG_SPL_OF_TRANSLATE=y
|
|||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_SYS_I2C_LEGACY=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
|
|
|
|||
231
doc/board/ti/am62x_sk.rst
Normal file
231
doc/board/ti/am62x_sk.rst
Normal file
|
|
@ -0,0 +1,231 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||
.. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com>
|
||||
|
||||
Texas Instruments AM62 Platforms
|
||||
================================
|
||||
|
||||
Introduction:
|
||||
-------------
|
||||
The AM62 SoC family is the follow on AM335x built on the K3 Multicore
|
||||
SoC architecture platform, providing ultra-low-power modes, dual
|
||||
display, multi-sensor edge compute, security and other BOM-saving
|
||||
integrations. The AM62 SoC targets a broad market to enable
|
||||
applications such as Industrial HMI, PLC/CNC/Robot control, Medical
|
||||
Equipment, Building Automation, Appliances and more.
|
||||
|
||||
Some highlights of this SoC are:
|
||||
|
||||
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
|
||||
Pin-to-pin compatible options for single and quad core are available.
|
||||
* Cortex-M4F for general-purpose or safety usage.
|
||||
* Dual display support, providing 24-bit RBG parallel interface and
|
||||
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
|
||||
resolution.
|
||||
* Selectable GPU support, up to 8GFLOPS, providing better user experience
|
||||
in 3D graphic display case and Android.
|
||||
* PRU(Programmable Realtime Unit) support for customized programmable
|
||||
interfaces/IOs.
|
||||
* Integrated Giga-bit Ethernet switch supporting up to a total of two
|
||||
external ports (TSN capable).
|
||||
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
|
||||
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
|
||||
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
|
||||
* Dedicated Centralized System Controller for Security, Power, and
|
||||
Resource Management.
|
||||
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
|
||||
enabling battery powered system design.
|
||||
|
||||
More details can be found in the Technical Reference Manual:
|
||||
https://www.ti.com/lit/pdf/spruiv7
|
||||
|
||||
Boot Flow:
|
||||
----------
|
||||
Below is the pictorial representation of boot flow:
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
| TIFS | Main R5 | A53 |
|
||||
+------------------------------------------------------------------------+
|
||||
| +--------+ | | |
|
||||
| | Reset | | | |
|
||||
| +--------+ | | |
|
||||
| : | | |
|
||||
| +--------+ | +-----------+ | |
|
||||
| | *ROM* |----------|-->| Reset rls | | |
|
||||
| +--------+ | +-----------+ | |
|
||||
| | | | : | |
|
||||
| | ROM | | : | |
|
||||
| |services| | : | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | | *R5 ROM* | | |
|
||||
| | | | +-------------+ | |
|
||||
| | |<---------|---|Load and auth| | |
|
||||
| | | | | tiboot3.bin | | |
|
||||
| +--------+ | +-------------+ | |
|
||||
| | |<---------|---| Load sysfw | | |
|
||||
| | | | | part to TIFS| | |
|
||||
| | | | | core | | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | : | |
|
||||
| | | | : | |
|
||||
| | | | : | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | | *R5 SPL* | | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | | DDR | | |
|
||||
| | | | | config | | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | | Load | | |
|
||||
| | | | | tispl.bin | | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | | Load R5 | | |
|
||||
| | | | | firmware | | |
|
||||
| | | | +-------------+ | |
|
||||
| | |<---------|---| Start A53 | | |
|
||||
| | | | | and jump to | | |
|
||||
| | | | | DM fw image | | |
|
||||
| | | | +-------------+ | |
|
||||
| | | | | +-----------+ |
|
||||
| | |----------|-----------------------|---->| Reset rls | |
|
||||
| | | | | +-----------+ |
|
||||
| | TIFS | | | : |
|
||||
| |Services| | | +-----------+ |
|
||||
| | |<---------|-----------------------|---->|*ATF/OPTEE*| |
|
||||
| | | | | +-----------+ |
|
||||
| | | | | : |
|
||||
| | | | | +-----------+ |
|
||||
| | |<---------|-----------------------|---->| *A53 SPL* | |
|
||||
| | | | | +-----------+ |
|
||||
| | | | | | Load | |
|
||||
| | | | | | u-boot.img| |
|
||||
| | | | | +-----------+ |
|
||||
| | | | | : |
|
||||
| | | | | +-----------+ |
|
||||
| | |<---------|-----------------------|---->| *U-Boot* | |
|
||||
| | | | | +-----------+ |
|
||||
| | | | | | prompt | |
|
||||
| | |----------|-----------------------|-----+-----------+-----|
|
||||
| +--------+ | | |
|
||||
| | | |
|
||||
+------------------------------------------------------------------------+
|
||||
|
||||
- Here TIFS acts as master and provides all the critical services. R5/A53
|
||||
requests TIFS to get these services done as shown in the above diagram.
|
||||
|
||||
Sources:
|
||||
--------
|
||||
1. SYSFW:
|
||||
Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
|
||||
Branch: master
|
||||
|
||||
2. ATF:
|
||||
Tree: https://github.com/ARM-software/arm-trusted-firmware.git
|
||||
Branch: master
|
||||
|
||||
3. OPTEE:
|
||||
Tree: https://github.com/OP-TEE/optee_os.git
|
||||
Branch: master
|
||||
|
||||
4. U-Boot:
|
||||
Tree: https://source.denx.de/u-boot/u-boot
|
||||
Branch: master
|
||||
|
||||
5. TI Linux Firmware:
|
||||
Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
|
||||
Branch: ti-linux-firmware
|
||||
|
||||
Build procedure:
|
||||
----------------
|
||||
1. ATF:
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
$ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=lite SPD=opteed
|
||||
|
||||
2. OPTEE:
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
$ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- CROSS_COMPILE64=aarch64-none-linux-gnu-
|
||||
|
||||
3. U-Boot:
|
||||
|
||||
* 3.1 R5:
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am62x_evm_r5_defconfig O=/tmp/r5
|
||||
$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5
|
||||
$ cd <k3-image-gen>
|
||||
$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=<path to ti-linux-firmware>/ti-sysfw/ti-fs-firmware-am62x-gp.bin
|
||||
|
||||
Use the tiboot3.bin generated from last command
|
||||
|
||||
* 3.2 A53:
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
$ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig O=/tmp/a53
|
||||
$ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=<path to ATF dir>/build/k3/lite/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to ti-linux-firmware>/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53
|
||||
|
||||
Target Images
|
||||
--------------
|
||||
Copy the below images to an SD card and boot:
|
||||
- tiboot3.bin from step 3.1
|
||||
- tispl.bin, u-boot.img from 3.2
|
||||
|
||||
Image formats:
|
||||
--------------
|
||||
|
||||
- tiboot3.bin:
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
+-----------------------+
|
||||
| X.509 |
|
||||
| Certificate |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | R5 | |
|
||||
| | u-boot-spl.bin | |
|
||||
| | | |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| |TIFS with board cfg| |
|
||||
| | | |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | | |
|
||||
| | FIT header | |
|
||||
| | +---------------+ | |
|
||||
| | | | | |
|
||||
| | | DTB 1...N | | |
|
||||
| | +---------------+ | |
|
||||
| +-------------------+ |
|
||||
+-----------------------+
|
||||
|
||||
- tispl.bin
|
||||
|
||||
.. code-block:: text
|
||||
|
||||
+-----------------------+
|
||||
| |
|
||||
| FIT HEADER |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | A53 ATF | |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | A53 OPTEE | |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | R5 DM FW | |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | A53 SPL | |
|
||||
| +-------------------+ |
|
||||
| | | |
|
||||
| | SPL DTB 1...N | |
|
||||
| +-------------------+ |
|
||||
+-----------------------+
|
||||
|
|
@ -8,3 +8,4 @@ Texas Instruments
|
|||
|
||||
am335x_evm
|
||||
j721e_evm
|
||||
am62x_sk
|
||||
|
|
|
|||
|
|
@ -73,6 +73,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
|
|||
.family = "J721S2",
|
||||
.data = &j721s2_clk_platdata,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_K3_AM625
|
||||
{
|
||||
.family = "AM62X",
|
||||
.data = &am62x_clk_platdata,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,3 +7,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
|
|||
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
|
||||
k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
|
||||
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
|
||||
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
|
||||
|
|
|
|||
50
drivers/dma/ti/k3-psil-am62.c
Normal file
50
drivers/dma/ti/k3-psil-am62.c
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "k3-psil-priv.h"
|
||||
|
||||
#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
|
||||
{ \
|
||||
.thread_id = x, \
|
||||
.ep_config = { \
|
||||
.ep_type = PSIL_EP_NATIVE, \
|
||||
.pkt_mode = 1, \
|
||||
.needs_epib = 1, \
|
||||
.psd_size = 16, \
|
||||
.mapped_channel_id = ch, \
|
||||
.flow_start = flow_base, \
|
||||
.flow_num = flow_cnt, \
|
||||
.default_flow_id = flow_base, \
|
||||
}, \
|
||||
}
|
||||
|
||||
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
|
||||
static struct psil_ep am62_src_ep_map[] = {
|
||||
/* CPSW3G */
|
||||
PSIL_ETHERNET(0x4600, 19, 19, 16),
|
||||
};
|
||||
|
||||
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
|
||||
static struct psil_ep am62_dst_ep_map[] = {
|
||||
/* CPSW3G */
|
||||
PSIL_ETHERNET(0xc600, 19, 19, 8),
|
||||
PSIL_ETHERNET(0xc601, 20, 27, 8),
|
||||
PSIL_ETHERNET(0xc602, 21, 35, 8),
|
||||
PSIL_ETHERNET(0xc603, 22, 43, 8),
|
||||
PSIL_ETHERNET(0xc604, 23, 51, 8),
|
||||
PSIL_ETHERNET(0xc605, 24, 59, 8),
|
||||
PSIL_ETHERNET(0xc606, 25, 67, 8),
|
||||
PSIL_ETHERNET(0xc607, 26, 75, 8),
|
||||
};
|
||||
|
||||
struct psil_ep_map am62_ep_map = {
|
||||
.name = "am62",
|
||||
.src = am62_src_ep_map,
|
||||
.src_count = ARRAY_SIZE(am62_src_ep_map),
|
||||
.dst = am62_dst_ep_map,
|
||||
.dst_count = ARRAY_SIZE(am62_dst_ep_map),
|
||||
};
|
||||
|
|
@ -41,5 +41,6 @@ extern struct psil_ep_map am654_ep_map;
|
|||
extern struct psil_ep_map j721e_ep_map;
|
||||
extern struct psil_ep_map j721s2_ep_map;
|
||||
extern struct psil_ep_map am64_ep_map;
|
||||
extern struct psil_ep_map am62_ep_map;
|
||||
|
||||
#endif /* K3_PSIL_PRIV_H_ */
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
|
|||
soc_ep_map = &j721s2_ep_map;
|
||||
else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
|
||||
soc_ep_map = &am64_ep_map;
|
||||
else if (IS_ENABLED(CONFIG_SOC_K3_AM625))
|
||||
soc_ep_map = &am62_ep_map;
|
||||
}
|
||||
|
||||
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
|
||||
|
|
|
|||
|
|
@ -118,6 +118,19 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
|
|||
};
|
||||
#endif /* CONFIG_TARGET_J721S2_R5_EVM */
|
||||
|
||||
#if IS_ENABLED(CONFIG_SOC_K3_AM625)
|
||||
static struct ti_sci_resource_static_data rm_static_data[] = {
|
||||
/* BC channels */
|
||||
{
|
||||
.dev_id = 26,
|
||||
.subtype = 32,
|
||||
.range_start = 18,
|
||||
.range_num = 2,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
#endif /* CONFIG_SOC_K3_AM625 */
|
||||
|
||||
#else
|
||||
static struct ti_sci_resource_static_data rm_static_data[] = {
|
||||
{ },
|
||||
|
|
|
|||
|
|
@ -670,6 +670,10 @@ static const struct udevice_id am654_sdhci_ids[] = {
|
|||
.compatible = "ti,am64-sdhci-4bit",
|
||||
.data = (ulong)&sdhci_am64_4bit_drvdata,
|
||||
},
|
||||
{
|
||||
.compatible = "ti,am62-sdhci",
|
||||
.data = (ulong)&sdhci_am64_4bit_drvdata,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -353,6 +353,7 @@ source "drivers/pinctrl/mscc/Kconfig"
|
|||
source "drivers/pinctrl/mtmips/Kconfig"
|
||||
source "drivers/pinctrl/mvebu/Kconfig"
|
||||
source "drivers/pinctrl/nexell/Kconfig"
|
||||
source "drivers/pinctrl/nuvoton/Kconfig"
|
||||
source "drivers/pinctrl/nxp/Kconfig"
|
||||
source "drivers/pinctrl/renesas/Kconfig"
|
||||
source "drivers/pinctrl/rockchip/Kconfig"
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
|
|||
obj-$(CONFIG_ARCH_ATH79) += ath79/
|
||||
obj-$(CONFIG_PINCTRL_INTEL) += intel/
|
||||
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
|
||||
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
|
||||
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
|
||||
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
|
||||
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
|
||||
|
|
|
|||
7
drivers/pinctrl/nuvoton/Kconfig
Normal file
7
drivers/pinctrl/nuvoton/Kconfig
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config PINCTRL_NPCM7XX
|
||||
bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"
|
||||
depends on DM && PINCTRL_GENERIC && ARCH_NPCM7xx
|
||||
help
|
||||
Say Y here to enable pin controller and GPIO support
|
||||
for Nuvoton NPCM750/730/715/705 SoCs.
|
||||
4
drivers/pinctrl/nuvoton/Makefile
Normal file
4
drivers/pinctrl/nuvoton/Makefile
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
# Nuvoton pinctrl support
|
||||
|
||||
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
|
||||
1607
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
Normal file
1607
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -86,6 +86,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
|
|||
.family = "J721S2",
|
||||
.data = &j721s2_pd_platdata,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_K3_AM625
|
||||
{
|
||||
.family = "AM62X",
|
||||
.data = &am62x_pd_platdata,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ choice
|
|||
|
||||
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
|
||||
default K3_AM64_DDRSS if SOC_K3_AM642
|
||||
default K3_AM64_DDRSS if SOC_K3_AM625
|
||||
|
||||
config K3_J721E_DDRSS
|
||||
bool "Enable J721E DDRSS support"
|
||||
|
|
|
|||
|
|
@ -31,6 +31,13 @@ config RNG_MSM
|
|||
This driver provides support for the Random Number
|
||||
Generator hardware found on Qualcomm SoCs.
|
||||
|
||||
config RNG_NPCM
|
||||
bool "Nuvoton NPCM SoCs Random Number Generator support"
|
||||
depends on DM_RNG
|
||||
help
|
||||
Enable random number generator on NPCM SoCs.
|
||||
This unit can provide 750 to 1000 random bits per second
|
||||
|
||||
config RNG_OPTEE
|
||||
bool "OP-TEE based Random Number Generator support"
|
||||
depends on DM_RNG && OPTEE
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o
|
|||
obj-$(CONFIG_RNG_MESON) += meson-rng.o
|
||||
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
|
||||
obj-$(CONFIG_RNG_MSM) += msm_rng.o
|
||||
obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
|
||||
obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
|
||||
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
|
||||
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
|
||||
|
|
|
|||
156
drivers/rng/npcm_rng.c
Normal file
156
drivers/rng/npcm_rng.c
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2022 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <malloc.h>
|
||||
#include <rng.h>
|
||||
#include <uboot_aes.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define RNGCS_RNGE BIT(0)
|
||||
#define RNGCS_DVALID BIT(1)
|
||||
#define RNGCS_CLKP(range) ((0x0f & (range)) << 2)
|
||||
#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */
|
||||
|
||||
enum {
|
||||
RNG_CLKP_80_100_MHZ = 0x00, /*default */
|
||||
RNG_CLKP_60_80_MHZ = 0x01,
|
||||
RNG_CLKP_50_60_MHZ = 0x02,
|
||||
RNG_CLKP_40_50_MHZ = 0x03,
|
||||
RNG_CLKP_30_40_MHZ = 0x04,
|
||||
RNG_CLKP_25_30_MHZ = 0x05,
|
||||
RNG_CLKP_20_25_MHZ = 0x06,
|
||||
RNG_CLKP_5_20_MHZ = 0x07,
|
||||
RNG_CLKP_2_15_MHZ = 0x08,
|
||||
RNG_CLKP_9_12_MHZ = 0x09,
|
||||
RNG_CLKP_7_9_MHZ = 0x0A,
|
||||
RNG_CLKP_6_7_MHZ = 0x0B,
|
||||
RNG_CLKP_5_6_MHZ = 0x0C,
|
||||
RNG_CLKP_4_5_MHZ = 0x0D,
|
||||
RNG_CLKP_3_4_MHZ = 0x0E,
|
||||
RNG_NUM_OF_CLKP
|
||||
};
|
||||
|
||||
struct npcm_rng_regs {
|
||||
unsigned int rngcs;
|
||||
unsigned int rngd;
|
||||
unsigned int rngmode;
|
||||
};
|
||||
|
||||
struct npcm_rng_priv {
|
||||
struct npcm_rng_regs *regs;
|
||||
};
|
||||
|
||||
static struct npcm_rng_priv *rng_priv;
|
||||
|
||||
void npcm_rng_init(void)
|
||||
{
|
||||
struct npcm_rng_regs *regs = rng_priv->regs;
|
||||
int init;
|
||||
|
||||
/* check if rng enabled */
|
||||
init = readb(®s->rngcs);
|
||||
if ((init & RNGCS_RNGE) == 0) {
|
||||
/* init rng */
|
||||
writeb(RNGCS_CLKP(RNG_CLKP_20_25_MHZ) | RNGCS_RNGE, ®s->rngcs);
|
||||
writeb(RNGMODE_M1ROSEL_VAL, ®s->rngmode);
|
||||
}
|
||||
}
|
||||
|
||||
void npcm_rng_disable(void)
|
||||
{
|
||||
struct npcm_rng_regs *regs = rng_priv->regs;
|
||||
|
||||
/* disable rng */
|
||||
writeb(0, ®s->rngcs);
|
||||
writeb(0, ®s->rngmode);
|
||||
}
|
||||
|
||||
void srand(unsigned int seed)
|
||||
{
|
||||
/* no need to seed for now */
|
||||
}
|
||||
|
||||
int npcm_rng_read(struct udevice *dev, void *data, size_t max)
|
||||
{
|
||||
struct npcm_rng_regs *regs = rng_priv->regs;
|
||||
int i;
|
||||
int ret_val = 0;
|
||||
char *buf = data;
|
||||
|
||||
npcm_rng_init();
|
||||
|
||||
printf("NPCM HW RNG\n");
|
||||
/* Wait for RNG done (max bytes) */
|
||||
for (i = 0; i < max; i++) {
|
||||
/* wait until DVALID is set */
|
||||
while ((readb(®s->rngcs) & RNGCS_DVALID) == 0)
|
||||
;
|
||||
buf[i] = ((unsigned int)readb(®s->rngd) & 0x000000FF);
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
unsigned int rand_r(unsigned int *seedp)
|
||||
{
|
||||
struct npcm_rng_regs *regs = rng_priv->regs;
|
||||
int i;
|
||||
unsigned int ret_val = 0;
|
||||
|
||||
npcm_rng_init();
|
||||
|
||||
/* Wait for RNG done (4 bytes) */
|
||||
for (i = 0; i < 4 ; i++) {
|
||||
/* wait until DVALID is set */
|
||||
while ((readb(®s->rngcs) & RNGCS_DVALID) == 0)
|
||||
;
|
||||
ret_val |= (((unsigned int)readb(®s->rngd) & 0x000000FF) << (i * 8));
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
unsigned int rand(void)
|
||||
{
|
||||
return rand_r(NULL);
|
||||
}
|
||||
|
||||
static int npcm_rng_bind(struct udevice *dev)
|
||||
{
|
||||
rng_priv = calloc(1, sizeof(struct npcm_rng_priv));
|
||||
if (!rng_priv)
|
||||
return -ENOMEM;
|
||||
|
||||
rng_priv->regs = dev_remap_addr_index(dev, 0);
|
||||
if (!rng_priv->regs) {
|
||||
printf("Cannot find rng reg address, binding failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
printf("RNG: NPCM RNG module bind OK\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id npcm_rng_ids[] = {
|
||||
{ .compatible = "nuvoton,npcm845-rng" },
|
||||
{ .compatible = "nuvoton,npcm750-rng" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct dm_rng_ops npcm_rng_ops = {
|
||||
.read = npcm_rng_read,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(npcm_rng) = {
|
||||
.name = "npcm_rng",
|
||||
.id = UCLASS_RNG,
|
||||
.ops = &npcm_rng_ops,
|
||||
.of_match = npcm_rng_ids,
|
||||
.priv_auto = sizeof(struct npcm_rng_priv),
|
||||
.bind = npcm_rng_bind,
|
||||
};
|
||||
|
|
@ -15,6 +15,7 @@
|
|||
#define J7200 0xbb6d
|
||||
#define AM64X 0xbb38
|
||||
#define J721S2 0xbb75
|
||||
#define AM62X 0xbb7e
|
||||
|
||||
#define JTAG_ID_VARIANT_SHIFT 28
|
||||
#define JTAG_ID_VARIANT_MASK (0xf << 28)
|
||||
|
|
@ -49,6 +50,9 @@ static const char *get_family_string(u32 idreg)
|
|||
case J721S2:
|
||||
family = "J721S2";
|
||||
break;
|
||||
case AM62X:
|
||||
family = "AM62X";
|
||||
break;
|
||||
default:
|
||||
family = "Unknown Silicon";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,8 +45,11 @@
|
|||
#define RXF 0x20
|
||||
#define RXE 0x24
|
||||
#define RXC 0x28
|
||||
#define TFES 1
|
||||
#define TFLETE 4
|
||||
#define TSSRS 6
|
||||
#define RFMTE 5
|
||||
#define RSSRS 6
|
||||
|
||||
#define FAULTF 0x2c
|
||||
#define FAULTC 0x30
|
||||
|
|
@ -170,6 +173,11 @@ static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active)
|
|||
priv->rx_words = 16;
|
||||
read_fifo(priv);
|
||||
}
|
||||
|
||||
/* wait until slave is deselected */
|
||||
while (!(readl(priv->base + TXF) & BIT(TSSRS)) ||
|
||||
!(readl(priv->base + RXF) & BIT(RSSRS)))
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -275,7 +283,7 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct synquacer_spi_priv *priv = dev_get_priv(bus);
|
||||
u32 val, words, busy;
|
||||
u32 val, words, busy = 0;
|
||||
|
||||
val = readl(priv->base + FIFOCFG);
|
||||
val |= (1 << RX_FLUSH);
|
||||
|
|
@ -323,9 +331,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|||
writel(~0, priv->base + RXC);
|
||||
|
||||
/* Trigger */
|
||||
val = readl(priv->base + DMSTART);
|
||||
val |= BIT(TRIGGER);
|
||||
writel(val, priv->base + DMSTART);
|
||||
if (flags & SPI_XFER_BEGIN) {
|
||||
val = readl(priv->base + DMSTART);
|
||||
val |= BIT(TRIGGER);
|
||||
writel(val, priv->base + DMSTART);
|
||||
}
|
||||
|
||||
while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
|
||||
if (priv->rx_words)
|
||||
|
|
@ -336,13 +346,10 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|||
if (priv->tx_words) {
|
||||
write_fifo(priv);
|
||||
} else {
|
||||
u32 len;
|
||||
|
||||
do { /* wait for shifter to empty out */
|
||||
/* wait for shifter to empty out */
|
||||
while (!(readl(priv->base + TXF) & BIT(TFES)))
|
||||
cpu_relax();
|
||||
len = readl(priv->base + DMSTATUS);
|
||||
len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
|
||||
} while (tx_buf && len);
|
||||
|
||||
busy &= ~BIT(TXBIT);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
67
include/configs/am62x_evm.h
Normal file
67
include/configs/am62x_evm.h
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration header file for K3 AM625 SoC family
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_AM625_EVM_H
|
||||
#define __CONFIG_AM625_EVM_H
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#include <environment/ti/mmc.h>
|
||||
|
||||
/* DDR Configuration */
|
||||
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
|
||||
|
||||
#define PARTS_DEFAULT \
|
||||
/* Linux partitions */ \
|
||||
"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
|
||||
|
||||
/* U-Boot general configuration */
|
||||
#define EXTRA_ENV_AM625_BOARD_SETTINGS \
|
||||
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"findfdt=" \
|
||||
"setenv name_fdt ${default_device_tree};" \
|
||||
"setenv fdtfile ${name_fdt}\0" \
|
||||
"name_kern=Image\0" \
|
||||
"console=ttyS2,115200n8\0" \
|
||||
"args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 " \
|
||||
"${mtdparts}\0" \
|
||||
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
|
||||
|
||||
/* U-Boot MMC-specific configuration */
|
||||
#define EXTRA_ENV_AM625_BOARD_SETTINGS_MMC \
|
||||
"boot=mmc\0" \
|
||||
"mmcdev=1\0" \
|
||||
"bootpart=1:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"rd_spec=-\0" \
|
||||
"init_mmc=run args_all args_mmc\0" \
|
||||
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
|
||||
"get_overlay_mmc=" \
|
||||
"fdt address ${fdtaddr};" \
|
||||
"fdt resize 0x100000;" \
|
||||
"for overlay in $name_overlays;" \
|
||||
"do;" \
|
||||
"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
|
||||
"fdt apply ${dtboaddr};" \
|
||||
"done;\0" \
|
||||
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
|
||||
"${bootdir}/${name_kern}\0" \
|
||||
"get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
|
||||
"${bootdir}/${name_fit}\0" \
|
||||
"partitions=" PARTS_DEFAULT
|
||||
|
||||
/* Incorporate settings into the U-Boot environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
DEFAULT_LINUX_BOOT_ENV \
|
||||
DEFAULT_MMC_TI_ARGS \
|
||||
EXTRA_ENV_AM625_BOARD_SETTINGS \
|
||||
EXTRA_ENV_AM625_BOARD_SETTINGS_MMC
|
||||
|
||||
/* Now for the remaining common defines */
|
||||
#include <configs/ti_armv7_common.h>
|
||||
|
||||
#endif /* __CONFIG_AM625_EVM_H */
|
||||
14
include/configs/bcm947622.h
Normal file
14
include/configs/bcm947622.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __BCM947622_H
|
||||
#define __BCM947622_H
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
#define COUNTER_FREQUENCY 50000000
|
||||
#endif
|
||||
|
|
@ -17,6 +17,8 @@
|
|||
|
||||
/* DDR Configuration */
|
||||
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
|
||||
/* FLASH Configuration */
|
||||
#define CONFIG_SYS_FLASH_BASE 0x000000000
|
||||
|
||||
/* SPL Loader Configuration */
|
||||
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||
|
|
|
|||
|
|
@ -41,4 +41,7 @@
|
|||
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -174,6 +174,7 @@ struct ti_k3_clk_platdata {
|
|||
extern const struct ti_k3_clk_platdata j721e_clk_platdata;
|
||||
extern const struct ti_k3_clk_platdata j7200_clk_platdata;
|
||||
extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
|
||||
extern const struct ti_k3_clk_platdata am62x_clk_platdata;
|
||||
|
||||
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
|
||||
void __iomem *reg);
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ struct ti_k3_pd_platdata {
|
|||
extern const struct ti_k3_pd_platdata j721e_pd_platdata;
|
||||
extern const struct ti_k3_pd_platdata j7200_pd_platdata;
|
||||
extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
|
||||
extern const struct ti_k3_pd_platdata am62x_pd_platdata;
|
||||
|
||||
u8 ti_pd_state(struct ti_pd *pd);
|
||||
u8 lpsc_get_state(struct ti_lpsc *lpsc);
|
||||
|
|
|
|||
Loading…
Reference in a new issue