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imx: imx8m[m/p]_phycore: Enable DM_SERIAL

Browse source 
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Peng Fan 2022-06-11 20:20:58 +08:00 committed by Stefano Babic
parent 4ebb9a5898
commit 64d118b27f
6 changed files with 4 additions and 24 deletions
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12
board/phytec/phycore_imx8mm/spl.c
View file

@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name)
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@ -77,8 +71,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
@ -92,8 +84,6 @@ void board_init_f(ulong dummy)
board_early_init_f();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -103,6 +93,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
enable_tzc380();
/* DDR initialization */

8
board/phytec/phycore_imx8mp/spl.c
View file

@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name)
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@ -109,8 +103,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}

1
configs/phycore-imx8mm_defconfig
View file

@ -120,6 +120,7 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/phycore-imx8mp_defconfig
View file

@ -111,6 +111,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y

3
include/configs/phycore_imx8mm.h
View file

@ -72,7 +72,4 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#endif /* __PHYCORE_IMX8MM_H */

3
include/configs/phycore_imx8mp.h
View file

@ -72,7 +72,4 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
#endif /* __PHYCORE_IMX8MP_H */