When CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP is enabled, use a
GET_REPORT control transfer to retrieve the initial state of the
keyboard. This matches the technique used to poll the keyboard state.
This is useful since it eliminates the remaining use of interrupt
transfers from the USB keyboard driver, which allows it to work with
USB HCD that don't support interrupt transfers.
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This driver is meant to be used with any OHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
With the old order of initialization the hcor pointer has been setup to
the same address as Exynos EHCI base address (0x12110000 instead of
0x12110010).
Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI
HCCPBASE register without doing proper clock initialization before.
To fix this problem hcor initialization has been moved after USB PHY setup.
Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.
The rename is done automatically:
$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
`git grep "s3c_udc\.h" | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.
The rename is done automatically:
$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
`git grep s3c_udc_probe | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.
The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:
git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
while read line ; do
sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
done
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.
Signed-off-by: Marek Vasut <marex@denx.de>
The extern statements are useless, remove them. Also remove the
extern ... controller, which is completely useless.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining local s3c_*() functions
to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep0_*() functions to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_request to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_ep to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_dev_*_ep to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.
Signed-off-by: Marek Vasut <marex@denx.de>
Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_udc to struct dwc2_udc to make
things more obvious and clear.
Signed-off-by: Marek Vasut <marex@denx.de>
We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since it is
used by MDIO. For FMAN v3, MDIO uses dedicated controller, so we
can disable unused FM1-DTSEC1 MAC node to avoid being probed in
Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Remove verbose message for FMan port.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
[York Sun: Added commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
The MC version numbers provide no meaningful information
about binary interface compatibility, so remove the
check which refuses to start the MC unless a specific
version is found.
Version checking is supposed to be done at the individual
object level, and individual drivers are responsible
for their own version checking.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This fixes commit 1a37889b0a:
----------------------->8--------------------
eeprom: Pull out the RW loop
Unify the code for doing read/write into single function, since the
code for both the read and write is almost identical. This again
trims down the code duplication.
----------------------->8--------------------
where the same one routine is utilized for both EEPROM writing and
reading. The only difference was supposed to be a "read" flag which
in both cases was set with 1 somehow.
That lead to a missing delay in case of writing which lead to write
failure (in my case no data was written).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
This reverts commit e8f954a756, which
causes compiling errors on 32-bit hosts.
Acked-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
uintptr_t which is a typdef for unsigned long is needed for creating
pointers (32 or 64 bit depending on Core) from 32 bit variables
storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *),
compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: York Sun <yorksun@freescale.com>
As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
some memory from the end of ram, tracked by gd->ram_size. It is not
always the top of u-boot visible memory. Rewrite the macro with a
weak function to provide flexibility for complex calcuation. Legacy
use of this macro is still supported.
Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
