This patch corrects the base addresses for USB_PHY and USB_OTG.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds functions to enable/disable the power of USB
host controller for EXYNOS5.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This patch corrects the SYSREG structure.
We have removed the sysreg.h added in the previous patchset
version as the sysreg structure is already defined in system.h.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This reverts commit fa042186b9.
It causes build warnings like this:
cpu.c:48:1: warning: -fstack-usage not supported for this target
[enabled by default]
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
ARM: cache: Move the cp15 CR register read before flushing the cache.
ARM: introduce arch_early_init_r()
PXA: Enable CONFIG_PREBOOT on zipitz2
ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
No need to define CONFIG_ARCH_CPU_INIT.
add new board vl_ma2sc
MTD: SPEAr SMI: Add write support for length < 4 bytes
i2c: designware_i2c.c: Add support for the "i2c probe" command
rtc/m41t62: Add support for M41T82 with HT (Halt Update)
SPL: ARM: spear: Add SPL support for SPEAr600 platform
Makefile: Add u-boot.spr build target (SPEAr)
SPL: ARM: spear: Remove some objects from SPL build
SPL: lib/Makefile: Add crc32.c to SPL build
SPL: common/Makefile: Add image.c to SPL build
arm: Don't use printf() in SPL builds
GPIO: Add SPEAr GPIO driver
net: Multiple updates/enhancements to designware.c
cleanup/SPEAr: Define configuration flags more elegantly
cleanup/SPEAr: Remove unnecessary parenthesis
SPEAr: Correct SoC ID offset in misc configuration space
SPEAr: explicitly select clk src for UART
SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
SPEAr: Enable dcache for fast file transfer
SPEAr: Enable autoneg for ethernet
SPEAr: Enable udc and usb-console support only for usbtty configuration
SPEAr: Enable usb device high speed support
SPEAr: Initialize SNOR in early_board_init_f
SPEAr: Change the default environment variables
SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
SPEAr: Add configuration options for spear3xx and spear6xx boards
SPEAr: Add basic arch related support for SPEAr SoCs
SPEAr: Add interface information in initialization
SPEAr: Add macb driver support for spear310 and spear320
SPEAr: Configure network support for spear SoCs
SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
SPEAr: Eliminate dependency on Xloader table
SPEAr: Fix ARM relocation support
st_smi: Fixed page size for Winbond W25Q128FV flash
st_smi: Change timeout loop implementation
st_smi: Fix bug in flash_print_info()
st_smi: Change the flash probing method
st_smi: Removed no needed dependency on ST_M25Pxx_ID
st_smi: Fix smi read status
st_smi: Move status register read before modifying ctrl register
st_smi: Read status until timeout happens
st_smi: Enhance the error handling
st_smi: Change SMI timeout values
st_smi: Return error in case TFF is not set
st_smi: Add support for SPEAr SMI driver
mtd/NAND: Remove obsolete SPEAr specific NAND drivers
SPEAr: Configure FSMC driver for NAND interface
mtd/NAND: Add FSMC driver support
arm/km: remove calls to kw_gpio_* in board_early_init_f
arm/km: add implementation for read_dip_switch
arm/km: support the 2 PCIe fpga resets
arm/km: skip FPGA config when already configured
arm/km: redefine piggy 4 reg names to avoid conflicts
arm/km: cleanup km_kirkwood boards
arm/km: enable BOCO2 FPGA download support
arm/km: remove portl2.h and use km_kirkwood instead
arm/km: convert mgcoge3un target to km_kirkwood
arm/km: add kmcoge5un board support
arm/km: add kmnusa board support
arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
cm-t35: fix incorrect NAND_ECC layout selection
ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
ARM: OMAP4/5: Move USB pads to essential list.
ARM: OMAP4/5: Move USB clocks to essential group.
ARM: OMAP4/5: Move gpmc clocks to essential group.
ARM: OMAP4+: Move external phy initialisations to arch specific place.
omap4: Use a smaller M,N couple for IVA DPLL
da850/omap-l138: Enable auto negotiation in RMII mode
omap: am33xx: accomodate input clocks other than 24 Mhz
omap: emif: fix bug in manufacturer code test
omap: emif: deal with rams that return duplicate mr data on all byte lanes
OMAP4+: Force DDR in self-refresh after warm reset
OMAP4+: Handle sdram init after warm reset
ARM: OMAP3+: Detect reset type
arm: bugfix: Move vector table before jumping relocated code
Kirkwood: Add support for Ka-Ro TK71
arm/km: use spi claim bus to switch between SPI and NAND
arm/kirkwood: protect the ENV_SPI #defines
ARM: don't probe PHY address for LaCie boards
lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
lacie_kw: fix SDRAM banks number for net2big_v2
Kirkwood: add lschlv2 and lsxhl board support
net: add helper to generate random mac address
net: use common rand()/srand() functions
lib: add rand() function
kwboot: boot kirkwood SoCs over a serial link
kw_spi: add weak functions board_spi_claim/release_bus
kw_spi: support spi_claim/release_bus functions
kw_spi: backup and reset the MPP of the chosen CS pin
kirkwood: fix calls to kirkwood_mpp_conf
kirkwood: add save functionality kirkwood_mpp_conf function
km_arm: use filesize for erase in update command
arm/km: enable mii cmd
arm/km: remove CONFIG_RESET_PHY_R
arm/km: change maintainer for mgcoge3un
arm/km: fix wrong comment in SDRAM config for mgcoge3un
arm/km: use ARRAY_SIZE macro
arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
arm/km: add piggy mac adress offset for mgcoge3un
arm/km: add board type to boards.cfg
AT91SAM9*: Change kernel address in dataflash to match u-boot's size
ATMEL/PIO: Enable new feature of PIO on Atmel device
ehci-atmel: fix compiler warning
AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
Atmel : usb : add EHCI driver for Atmel SoC
Fix: AT91SAM9263 nor flash usage
Fix: broken boot message at serial line on AT91SAM9263-EK board
i.MX6 USDHC: Use the ESDHC clock
mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
i.MX28: Add function to adjust memory parameters
mx28evk: Fix PSWITCH key position
mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove unused CONFIG_MII_GASKET
mx6: Avoid writing to read-only bits in imximage.cfg
m28evk: use same notation to alloc the 128kB stack
...
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
powerpc/mpc85xx: Workaround for erratum CPU_A011
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
powerpc/P4080: Check SVR for CPU22 workaround
lib/powerpc: addrmap_phys_to_virt() should return a pointer
powerpc/85xx: clean up P1022DS board configuration header file
powerpc/85xx: fdt_set_phy_handle() should return an error code
powerpc/85xx: minor clean-ups to the P2020DS board header file
powerpc/p1010rdb: add readme document for p1010rdb
powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
powerpc/mpc85xx:Add debugger support for e500v2 SoC
powerpc/85xx:Fix NAND code base to support debugger
powerpc/85xx:Make debug exception vector accessible
powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
powerpc/p1010rdb: update mux config of p1010rdb board
powerpc/mpc85xx:Add BSC9131 RDB Support
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
powerpc/85xx: Add USB device-tree fixup for various platforms
Signed-off-by: Wolfgang Denk <wd@denx.de>
The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
int cleanup_before_linux(void)
{
...
...
dcache_disable();
v7_outer_cache_disable();
invalidate_dcache_all();
}
1) invalidate_dcache_all call expects that all the caches has been
flushed, invalidated and there are no dirty entries prior to its
execution. In the above sequence dcache_disable() flushes, invalidates
the caches and turns off the mmu. But after it cleanups the cache
and before the mmu is disabled there is a cp_delay() function which
has STR instruction. On certain cores like the cortex-a15, cache hit
and a write can happen to a cache line even when the dcache is
disabled. So the above mentioned STR instruction creates a dirty entry
after cleaning. The mmu gets disabled after this.
2) invalidate_dcache_all invalidates the cache lines. Again on
cores like cortex-a15, invalidate instruction flushes the dirty
line as well. So some times the dirty line from sequence 1
can corrupt the memory resulting in a crash.
Fixing this by moving the get_cr() and cp_delay() calls before
cleaning up the cache, thus avoiding the dirty entry.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Introduce arch_early_init_r() function, which can be useful for doing
early initialization after relocation has happened.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
No need to define CONFIG_ARCH_CPU_INIT.
All mx28 based boards should use arch_cpu_init().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
This patch adds SPL support for SPEAr600. Currently only SNOR
(Serial NOR) flash support is included. Other boot devices
(NAND, MMC, USB ...) may be added with later patches.
Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
raise() likes to call printf() if it is available, but in SPL builds it
either is not available, or adds a large chunk to the resulting image
size.
So don't call it even if it is available.
This change reduces SPL size from 10KB to 6.3KB on hawkboard, for
example, using generic relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
In SPEAr configuration files, unnecessary paranthesis are used in some
\#defines. Remove them as they serve no purpose
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Earlier, architecture specific init code was mixed with board initialization
code in board/spear/... This patch updates architecture support for SPEAr in
latest u-boot and prints the SoC information.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The
driver for this device is already supported by u-boot, so configuring
board configuration file and defining base addresses etc to make use
of the common driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Xloader table was used primarily to inform u-boot about the DDR size. However,
now the ddr size is calculated at runtime which eliminates any need for the
Xloader table. So removing this unnecessary code.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SMI is the serial memory interface controller provided by ST.
Earlier, a driver exists in the u-boot source code for the SMI IP. However, it
was specific to spear platforms. This commit converts the same driver to a more
generic driver. As a result, the driver files are renamed to st_smi.c and
st_smi.h and moved into drivers/mtd folder for reusability by other platforms
using smi controller peripheral.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since FSMC is a standard IP and it supports different memory interfaces, it
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
USB clocks will be required for fastboot, tftp
related functionalities. Move these clocks to
essential group inorder to have the functionality
working when non-essential clocks are not enabled.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
GPMC clocks are currently getting enabled as a part
non-essential clocks. This will be required during
NOR boot. Move this to essential group to keep the
functionality, when non-essential clocks are not
enabled.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
This reduced M,N couple corresponds to the advised value from
TI HW team.
Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.
Signed-off-by: Sebastien Jan <s-jan@ti.com>
The PLL setup values currently assume a 24 Mhz input clock.
This patch uses V_OSCK from the board config file to support boards
with different input clock rates.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so
Micron memory will not be detected!
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Some rams (Micron for example) return duplicate mr data on all byte lanes.
Users of the get_mr function currently don't deal with this duplicated
data gracefully. This patch detects the duplicated data and returns only
the expected 8 bit mr data.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Errata ID:i727
Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.
Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.
This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
EMIF and DDR device state are preserved in warmreset. Redoing the full
initialisation would cause unexpected behaviour. Do only partial
initialisation to account for frequency change.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.
This will be used to skip the module configurations
that are retained across a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.
Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.
A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.
MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).
Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This function can be overridden at run-time and allows implementors
of new boards based on the i.MX28 chip to fine-tune the memory params.
It is possible to write into the dram_vals array because when the SPL
runs, it is located SRAM. Therefore the location is writable. There is
no possibility of these data to be read-only.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
The macro mistakenly referred to 32bit struct instead of 8bit one.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c.
Fix the mask for these bits.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Previously, only the low 5 bits (NCH) were being transfered
from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed.
VTP_RECAL should be bit 15, not 18.
The only mainline board affected by this change is davinci_sonata.
The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT.
However, if the program that loads u-boot on these boards
copied the code from u-boot, they will need fixed as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Please get tested by acks before applying, where tested by
means an overnight memory test.
Thanks
Troy
get_ram_size checks the given memory range for valid ram,
but expects the size of memory to be aligned to the power
of 2. In case of OMAP5 evm board the memory available is
2GB - 16MB(used for TRAP section) = 2032MB.
So always ensure that the size of memory used for testing is
aligned to the power of 2.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.
This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.
Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The DMM sections can be overlapping with each other, with
sections 3 to 0 having the highest to lowest priority in that
order. There could also be a section that is used trap the
unmapped Tiler entries and this trap section could be
overlapping with the actual sdram area.
So take care of the above scenarios while calculating the
size of the actual ram.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.
The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9. While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry
v2: remove enum change
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun <yorksun@freescale.com>
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun <yorksun@freescale.com>
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.
The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.
Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).
So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.
Please refer doc/README.mpc85xx for more information
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.
As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.
2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register
Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
The misspelling of "semiconductor" causes some internal copyright analysis
tools to complain.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in <config_fallbacks.h> which mkconfig places after <configs/...h> in
the generated config file. This is used when a board has not set its
own table.
Signed-off-by: Tom Rini <trini@ti.com>
* 'master' of git://git.denx.de/u-boot-video:
video: atmel/lcd: add LCD driver for new Atmel SoC
video: cfb_console: flush dcache for frame buffer in DRAM
cfb_console: Ignore bell character
cfb_console: Add console_clear_line function
cfb_console: Fix function console_back
omap3_dss: cosmetic changes
omap3_dss: add optional framebuffer
mx53loco: Add LCD support
mx5: Rename mx51_fb_init()
mx53: Allow IPUv3 driver to also work on mx53
mx51evk: Add LCD support
EXYNOS: display 32bpp bitmap TIZEN logo
create lib/tizen directory
LCD: display 32bpp decompressed bitmap image
common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
common/lcd.c: use ARRAY_SIZE
cmd_bmp.c: make bmp_display() usable by drivers or board code
LCD: support another s6e8ax0 panel type
LCD: change s6e8ax0 panel gamma value
include/video.h: drop unused video_printf()
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-mips:
MIPS: board.c: move extern declarations to u-boot-mips.h
MIPS: bootm_qemu_mips.c: make checkpatch.pl clean
MIPS: bootm.c: make checkpatch.pl clean
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-sh:
sh/ap_sh4a_4a: Fix typo of operator in ET0_ETXD4
sh: Add SH7269 device and RSK2+SH7269 board
sh: Set CONFIG_SH_ETHER_PHY_MODE and CONFIG_SH_ETHER_SH7734_MII to boards with sh_eth
sh: Add support for AP-SH4A-4A board
sh: Add register definition of PFC for SH7734
sh: r0p7734: Add support I2C controller
sh: Add bit control functions
sh: Add support for r0p7734 board
sh: Add support Renesas SH7734
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:
$ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
Configuring for MPC8572DS board...
make: *** [u-boot] Error 1
powerpc-linux-gnu-size: './u-boot': No such file
e1000.c: In function ‘e1000_initialize’:
e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
tsec.c: In function ‘tsec_initialize’:
tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1
--------------------- SUMMARY ----------------------------
Boards compiled: 1
Boards with errors: 1 ( MPC8572DS )
----------------------------------------------------------
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
This patch fixes following warning:
---8<---
board.c: In function 'board_init_r':
board.c:257: warning: unused variable 's'
--->8---
Patch de30122bb5 missed to remove this variable
too.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
