In SMP all harts will register themself in available_hart
during start up. Then main hart will send IPI to other harts
according to this variables. But this mechanism may not
guarantee that all other harts can jump to next stage.
When main hart is sending IPI to other hart according to
available_harts, but other harts maybe still not finish the
registration. Then the SMP booting will miss some harts finally.
So let it become an option and it will be enabled by default.
Please refer to the discussion:
https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.
In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.
The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.
This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.
So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.
Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit sychronizes the header file for FU740 PRCI clocks with the
one from Linux 5.19.
The constant values are the same, but all constant names are changed
(most are just prefixed with FU740_).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This adds the onkey, RTC and watchdog children to the DA9063 PMIC node,
fixes the compatible for qspi0's flash node to match the official DT
schema (it being an is25wp256 is discoverable, hence jedec,spi-nor is
the only compatible that should be present) and exposes the card detect
GPIO.
Note that the device trees still diverge in some places (including
important things like the PCIe controller's clock name) and should be
cleaned up so that a common device tree is used in both projects rather
than having different bindings. This patch does not attempt to do that,
merely expose important functionality present in Linux's that is not in
U-Boot's so that it can be used without the OS providing its own bundled
copy.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The booting flow is SPL -> OpenSBI -> U-Boot.
The boot hart may change after OpenSBI and may not always be hart0,
so wrap the related branch instruction with M-MODE.
Current DTB setup for XIP is not valid.
There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used
in XIP mode, to be returned. Fix this.
Fixes: 2e8d2f8843 ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Restore global pointer before board_init_f_init_reserve call,
as "a0" can be set in harts_early_init call and we end up with
invalid global pointer.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
With commit ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory
location"), the function board_get_usable_ram_top() is allocating
MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this
much memory in case of mini U-Boot.
Keep these functions which use lmb under CONFIG_LMB so that they are
compiled and used only when LMB is enabled.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.
Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.
Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR
- Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack
pointer directly, otherwise we use the common calculation.
- On some platforms that were using the standard calculation but did not
set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them.
- On a small number of platforms that were not subtracting
GENERATED_GBL_DATA_SIZE do so now via the standard calculation.
- CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most
board config header files.
Signed-off-by: Tom Rini <trini@konsulko.com>
Clean up asm/io.h by
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa, mem_pci)
This massively improves the readability of the file.
Suggested by commits:
7ab2e47d27 ("arm: Clean up asm/io.h")
909d0399a5 ("ARM: asm/io.h: kill off confusing #ifdef __mem_pci block")
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Commit ba1ed5b022 ("Convert CONFIG_ARCH_MAP_SYSMEM to Kconfig") clearly
defined that this option is available for SANDBOX (was also for already
removed NDS32). That's why there is no way how this code can be enabled
with current Kconfig layout for riscv.
Based on this removing this code.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When trying to run qemu-riscv64_smode_defconfig with 32 harts booting
fails. The debug UART shows a message
alloc space exhausted
32 is the current maximum number of harts for machine virt in QEMU 7.0.
Raise the default for SYS_MALLOC_F_LEN to 16 KiB.
Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for
other architectures too.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Provide library functions to read:
* machine vendor ID
* machine architecture ID
* machine implementation ID
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification
has added the Performance Monitoring Unit Extension.
The sbi command should be able to detect it.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Linux PLIC interrupt-controller driver actually initializes the hart
context registers in the PLIC driver exactly in the same order as
specified in the interrupts-extended device tree property. See the device
tree binding [1].
The ordering of the interrupts is therefore essential in order to
configure the PLIC correctly.
Fix the order so that we will have sane IRQ behavior when booting Linux
with the u-boot device tree.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the
power bit offset of the fpioa device to be specified as a single
property "canaan,k210-sysctl-power".
Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset"
properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel
requirements. This new property is parsed using the existing function
dev_read_phandle_with_args().
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Linux drivers for many of the K210 peripherals depend on the power bus
clock to be specified. Add the missing clocks and their names to avoid
problems when booting Linux using u-boot DT.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Instead of a special function, send an event after driver model is inited
and adjust the boards which use this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
When building for a custom board, it is quite common to maintain a
private branch which include some defconfig and .dts files. But to
hook up those .dts files requires modifying a file "belonging" to
upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch
to a newer upstream then often results in a conflict which, while it
is trivial to resolve by hand, makes it harder to have a CI do "try to
build our board against latest upstream".
The .config usually includes information on precisely what .dtb(s) are
needed, so to avoid having to modify the Makefile, simply add the
files in (SPL_)OF_LIST to dtb-y.
A technicality is that (SPL_)OF_LIST is not always defined, so rework
the Kconfig symbols so that (SPL_)OF_LIST is always defined (when
(SPL_)OF_CONTROL), but only prompted for in the cases which used to be
their "depends on".
nios2 and microblaze already have something like this in their
dts/Makefile, and the rationale in commit 41f59f6853 is similar to
the above. So this simply generalizes existing practice. Followup
patches could remove the logic in those two makefiles, just as there's
potential for moving some common boilerplate from all the
arch/*/dts/Makefile files to the new scripts/Makefile.dts.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
The alignment of sections in the EFI binaries generated by U-Boot is
incorrect.
According to the PE-COFF specification [1] the minimum value for
FileAlignment is 512. If the value of SectionAlignment is
less then the page size, it must equal FileAlignment.
Let's set both values to 512 for the ARM and RISC-V architectures.
[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
EDK II refuses to load the EFI binaries created by U-Boot.
The reason is an incorrect PE-COFF header. The number of
data directories does not match NumberOfRvaAndSizes.
This leads to a failed consistency check in
PeCoffLoaderGetPeHeader():
SizeOfOptionalHeader - HeaderWithoutDataDir) !=
NumberOfRvaAndSizes * sizeof(DATA_DIRECTORY))
Fixes: 9afaeec6ef ("riscv: Complete efi header for RV32/64")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
This uses QEMU virt which creates its own devicetree.
Copy the existing empty version of this file, so splitting the existing
qemu-virt into two, since anyone actually trying to use this will need a
different devicetree for 32- and 64-bit machines.
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable saving environment to SPI flash memory on SiFive
Unmatched.
Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Configure SPI flash devices into SPL. Add SPI boot option to spl.c.
Document how to format flash for booting.
Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The device tree split into .dtsi and .dts files, common
device node for eMMC/SD, enable I2C1, UART1 for console
instead of UART0, enable the DDR 2GB memory and in
that 288MB memory is reserved for fabric buffer.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This patch adds memcpy_fromio and memcpy_toio definitions for some device
drivers which have these definitions, like cadence_qspi_apb.c
Signed-off-by: Wei Fu <wefu@redhat.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Provide function sbi_get_impl_version() to retrieve the SBI implementation
version.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
io read/write may cause wrong result because they may read/write data
from/to register instead of memory. Add 'volatile' to avoid it.
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
introduced, in order to support a DTB handed over by an earlier stage boo
loader. However we have another option in the Kconfig (OF_BOARD) which has
identical semantics.
On RISC-V some of the boards pick up the DTB from a1 and copy it in their
private gd_t. Apart from that they copy it to prior_stage_fdt_address, if
the Kconfig option is selected, which is unnecessary.
So let's switch the config option for those boards to OF_BOARD and define
the required board_fdt_blob_setup() for them.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reserved memory nodes can have additional flags. Support reading and
writing these flags to ensure that reserved memory nodes can be properly
parsed and emitted.
This converts support for the existing "no-map" flag to avoid extending
the argument list for fdtdec_add_reserved_memory() to excessive length.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reserved memory nodes can have a compatible string list to identify the
type of reserved memory that they represent. Support specifying an
optional compatible string list when creating these nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a host Kconfig for OF_LIBFDT. With this we can use
CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the
unnecessary indirection.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.
Enable CM and I/D cache at the same time in harts_early_init
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The no-map property is wrongly skipped if a no-map reserved memory
node follows one without that property. Fix this by not remembering
the absence of a no-map property across loop iterations.
Fixes: d4ea649f17 ("riscv: Provide a mechanism to fix DT for reserved memory")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.
Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Leo <ycliang@andestech.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Invokes the common cache_init function to initialize ccache.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.
In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
To make analyzing exceptions easier output the code that leads to it.
We already do the same on the ARM platform.
Here is an example:
=> exception ebreak
Unhandled exception: Breakpoint
EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000
EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted
Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)
To disassemble the code we can use the decodecode script:
$ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \
CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode
Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)
All code
========
0: 2785 addiw a5,a5,1
2: 07a00693 li a3,122
6: fef6dce3 bge a3,a5,0xfffffffffffffffe
a: 47a5 li a5,9
c: 00e7d563 bge a5,a4,0x16
10:* 9002 ebreak <-- trapping instruction
...
Code starting with the faulting instruction
===========================================
0: 9002 ebreak
...
As it is not always clear if the first 16 bits are at the start or in the
middle of a 32bit instruction it may become necessary to strip the first
u16 from the output before calling decodecode to get the correct
disassembled code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <trini@konsulko.com>
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
Introduce select statements for other architectures based on current
usage. For MIPS, we take the existing arch-specific symbol and migrate
to the generic symbol. This lets us remove a little bit of otherwise
unused code.
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Leo <ycliang@andestech.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Add the Linux magic to the EFI file header to allow running our test
programs with GRUB's linux command.
MajorImageVersion = 1 indicates a kernel that can consume the
EFI_LOAD_FILE2_PROTOCOL. This allows to dump the GRUB provided intird with
our initrddump.efi tool.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Rename these options so that CONFIG_IS_ENABLED can be used with them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
This patch reverts the following commits:
- 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
- ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")
We won't plan to support unmatched that the revision below 3 in u-boot,
so they can be dropped because they might be useless.
Changed in v2:
- rebase codebase to the latest master branch
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
If force_reloc flag is not set and booti is called for an address
ouside RAM (i. e. QSPI NOR flash), we should honor that and not try
to force relocation in a bogus fashion.
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Previous device tree for OpenPiton emits a warning during compilation.
This commit fixes the previous warning adds dts to the OpenPiton RISC-V
board and added the device tree to MAINTAINER file.
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The difference between unmatched rev3 and rev1 is DDR timing, the rev3
uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
There are different DDR parameter settings for different board
revisions. Add a new interface to get the PCB revision to determine
which DT should be selected at runtime.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
i2c node.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.
Let's add all the required "u-boot,dm-spl" for SPL config.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
PLIC nodes don't have child nodes, so #address-cells is not needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
There are two spaces before "debug' in bootargs. Drop one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The SPDX license header is currently missing. Add one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Add defconfig and board support for HiFive Unmatched.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Add dts support for fu740. The HiFive Unmatched support is based on
fu740 cpu and drivers in following patch set.
Signed-off-by: Green Wan <green.wan@sifive.com>
[greentime.hu: set fu740 speed to 1.2GHz]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit does the same thing as Linux commit 33def8498fdd.
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.
Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have switched to binman to generate u-boot.itb for all
RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can
be dropped.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs,
so that binman is now used to generate u-boot.itb.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sort the RISC-V DTS build targets by their Kconfig target names in
alphabetical order.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently all assembly optimized implementation of memory routines
show up at the top level of the RISC-V architecture Kconfig menu.
Let's group them together into a submenu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present U-Boot SPL fails to boot on SiFive Unleashed board, due
to a load address misaligned exception happens when loading the FIT
image in spl_load_simple_fit(). The exception happens in memmove()
which is called by fdt_splice_().
Commit 8f0dc4cfd1 introduces an assembly version of memmove but
it does take misalignment into account (it checks if length is a
multiple of machine word size but pointers need also be aligned).
As a result it will generate misaligned load/store for the majority
of cases and causes significant performance regression on hardware
that traps misaligned load/store and emulate them using firmware.
The current behaviour of memcpy is that it checks if both src and
dest pointers are co-aligned (aka congruent modular SZ_REG). If
aligned, it will copy data word-by-word after first aligning
pointers to word boundary. If src and dst are not co-aligned,
however, byte-wise copy will be performed.
This patch was taken from the Linux kernel patch [1], which has not
been applied at the time being. It fixes the memmove and optimises
memcpy for misaligned cases. It will first align destination pointer
to word-boundary regardless whether src and dest are co-aligned or
not. If they indeed are, then wordwise copy is performed. If they
are not co-aligned, then it will load two adjacent words from src
and use shifts to assemble a full machine word. Some additional
assembly level micro-optimisation is also performed to ensure more
instructions can be compressed (e.g. prefer a0 to t6).
With this patch, U-Boot boots again on SiFive Unleashed board.
[1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/
Fixes: 8f0dc4cfd1 ("riscv: assembler versions of memcpy, memmove, memset")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
If /chosen was missing, chosen_offset would never get updated with the new
/chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes
this by setting chosen_offset. In addition, log any errors from setting
boot-hartid as well.
Fixes: 5370478d1c ("riscv: Add boot hartid to device tree")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
This reverts commit bc8bbb77f7.
This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This is more consistent with the naming of other ram banks, and matches
what Linux is doing.
Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for stack protector for UBOOT, SPL, and TPL
as well as new pytest for stackprotector
Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com>
Adjust UEFI build flags.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The uart nodes already provide <clocks> property for the driver to
dynamically calculate the correct clock frequency. There is no need
to keep the hard-coded <clock-frequency> property.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Provide optimized versions of memcpy(), memmove(), memset() copied from
the Linux kernel.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The value returned by setjmp must be nonzero. If zero is passed as
parameter it must be replaced by 1.
This patch reduces the code size a bit.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
