Zong Li 4d4222d074 common: board_r: support enable_caches for RISC-V ... The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>		2021-09-07 10:34:29 +08:00
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cpu	riscv: cpu: fu740: Fix typo of date	2021-08-17 19:28:37 +08:00
dts	board: sifive: drop stuff related to unmatched revision 1	2021-07-21 16:39:57 +08:00
include/asm	board: sifive: Add an interface to get PCB revision	2021-07-06 20:24:25 +08:00
lib	common: board_r: support enable_caches for RISC-V	2021-09-07 10:34:29 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	board: riscv: add openpiton-riscv64 SoC support	2021-07-06 13:50:56 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00