Commit graph

15508 commits

Author SHA1 Message Date
Jagan Teki
aa30aae8b4 ram: rk3399: Add tsel control clock drive
tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.

Add support for these control clock for all dramtype
sdrams.

Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.

tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
2fb2de33b2 ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
Now we have IO settings available for all supported sdram
frequencies, so retrieve these IO settings and make used
for LPDDR4 ds odt configuration.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
74109de3c2 ram: rk3399: Add IO settings
Add IO settings for dram ctl and phy.

IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.

Right now, this patch added IO setting for all supported
sdram frequencies.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
740409804e ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits

and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.

So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
66912baa0f ram: rk3399: Configure tsel write ca for lpddr4
tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.

Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
4e9de9eba8 ram: rk3399: Map chipselect for lpddr4
Assign desired cs_map values for lpddr4 during set memory map.

Initial cs_map values is based on the sdram parameters, so
the same will adjusted based dramtype as LPDDR4.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
d3d0099ca6 ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
f9f32d61a6 ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
881860fd34 ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
009fe1bac9 ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.

So, configure the same in pctl_cfg for LPDDR4.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
47627c8a5c ram: rk3399: Avoid two channel ZQ Cal Start at the same time
It is possible in lpddr4 dram, where both the channels would
start at same time with ZQ Cal Start. If it uses ZQ Call start
then it will use RZQ.

For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe
connect to both channel. If ZQ Cal Start at the same time,
it will use the same RZQ.

It is not a problem of using RZQ in both the channels, but can not
use at the same time.

So, to avoid this, we have an option of dram tINIT3 value for
increasing the frequency for channel 1.

This patch increase the available tINIT3 with existing running
dram frequency.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
5cbc866981 ram: rk3399: Don't wait for PLL lock in lpddr4
lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.

So no need to wait explicitly during pctl config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
6cbd2426b3 ram: rk3399: Move mode_sel assignment
mode_sel assignment is based on dram type.

In phy_io_config, already have vref setting based
on the dram type, so move this mode_sel assignment
on vref setting area.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
c716bf67f5 ram: rk3399: Add lpddr4 rank mask for wdql training
Add rank_mask based on the rank number for lpddr4.

This would keep the wdql data training loop based on the
desired rank mask value instead of looping for all values.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
3dae87da89 ram: rk3399: Add lpddr4 rank mask for ca training
Add rank_mask based on the rank number for lpddr4.

This would keep the ca data training loop based on the
desired rank mask value instead of looping for all values.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
b6cf08949d ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry
Supporting LPDDR4 code support in RK3399 would increases
the size of SPL/TPL.

So add kconfig entry for RK3399 LPDDR4 code so-that
the boards have LPDDR4 can enable them via defconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
ba607fafd1 ram: rk3399: Configure phy IO in ds odt
Some dramtypes like lpddr4 initialization would required to
configure phy IO even after pctl_cfg and after set_ds_odt.

For those cases the set_ds_odt would be an initial call to
setup the phy.

To satisfy all the cases, trigger phy IO from set_ds_odt.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
a735550bb8 ram: rk3399: Add DdrMode
Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
ed77ce728a ram: rk3399: Add ddrtimingC0
Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
b713e0291b ram: rk3399: Add ddr version enc macro
Add dram config macro for handling ddr version number.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
01cc103915 ram: rk3399: Introduce sys_reg3 for more capacity info
cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
e0ddb0ba21 ram: rk3399: Rename sys_reg with sys_reg2
Use dram config variable name as sys_reg2 instead of sys_reg
since the final variable value is to written into a pmugrf
register named as sys_reg2.

This reflect the both variable and associated register
names are same and also help to add next sys_reg's to
add it in future.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
879f9fed6a ram: rk3399: Simply existing dram enc macro
Add simplified and meaningful macro for all setting.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash the similar patches into 1 patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
a9191b8eec ram: rk3399: Enable sdram debug functions
This would help to debug the sdram base parameters while
debugging existing chip or while supporting new sdram type.

It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG
for showing the debug prints.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
d0ba88f5dd ram: rk3399: Add rank detection support
Right now the rk3399 sdram driver assume that the board
has configured with 2 channels, so any possibility to
enable single channel on the same driver will encounter
channel #1 data training failure.

Log:
U-Boot TPL board init
sdram_init: data training failed
rk3399_dmc_init DRAM init failed -5

So, add an algorithm that can capable to compute the active
or configured rank with associated channel like
a) do rank loop to compute the active rank, with associated
   channel numbers
b) then, succeed the data training only for configured channel
c) preserve the rank for given channel
d) do channel loop for setting the active channel
e) if given rank is zero or inactive on the specific channel,
   clear the timings for the associated channel
f) finally, return error if number of channels is zero

Tested in NanoPI-NEO4 since it support single channel sdram
configuration.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(add PI_READ_GATE_TRAINING for LPDDR3 to support rk3399-evb case)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:54:32 +08:00
Lukasz Majewski
2756fd16ca serial: mxc: Add compatibles to NXP's serial driver (for imx21 and imx53)
This patch fixes not enabled uart2 (and hence serial console) on i.MX53
devices. After following commit 1d255904c3 ("ARM: dts: imx: imx53:
Synchronize iMX53 DT with Linux") from the uart2 compatible the
'fsl,imx7d-uart' has been removed (which was correct).

However, the root cause of the problem was the commit 98d62e618b ("arm:
imx: add i.MX53 Beckhoff CX9020 Embedded PC") which introduced this
compatible.

Moreover, without this patch all i.MX53 UARTs are not usable as neither
'fsl,imx53-uart' nor 'fsl,imx21-uart' are in compatible IDs in
drivers/serial/serial_mxc.c file.

The fix is to add 'fsl,imx53-uart' and 'fsl,imx21-uart' as compatibles
for the aforementioned serial driver (those are also defined in the Linux
kernel).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2019-07-19 20:32:24 +02:00
Lukasz Majewski
1b8c986b68 IMX: serial: dm: Set DM_FLAG_PRE_RELOC in the IMX uart driver
The DM_FLAG_PRE_RELOC shall be set unconditionally as this driver is going
to be re-used in both early SPL and U-Boot proper's pre-reloc.

For i.MX based devices it is crucial to have available the serial console
before relocation (otherwise the board may hand).

The device definition may be provided either via device tree description or
with U_BOOT_DEVICE(mxc_serial) definition. In the latter case the device
will not bind in U-Boot proper when DM_FLAG_PRE_RELOC is not set.

The !CONFIG_IS_ENABLED(OF_CONTROL) #if check was set as a "workaround" for
DM problem described in following commit 4687919684
("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers").

Let's look on this check more thoroughly - we add this flag if the board
doesn't support OF_CONTROL. This is a bit strange as the serial_mxc.c can
be used with CONFIG_DM_SERIAL but without corresponding device tree
description (OF_CONTROL). In such case the aforementioned
U_BOOT_DEVICE(mxc_serial) definition is used.

Other boards/SoCs have this flag set unconditionally for serial driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 20:14:50 +02:00
Marek Vasut
4b969deac0 watchdog: imx: Add DM support
Add DM and DT probing support to iMX watchdog driver. This should
allow boards to move over to this driver, enable SYSRESET_WATCHDOG
to handle cpu_reset() if required.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
2019-07-19 20:14:50 +02:00
Marek Vasut
6874cb7220 watchdog: Split WDT from SPL_WDT
Use CONFIG_IS_ENABLED(WDT) to permit use of WDT in SPL without DM,
while the full U-Boot can use rich DM/DT WDT driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Suniel Mahesh <sunil.m@techveda.org>
2019-07-19 20:14:50 +02:00
Lukasz Majewski
01941377ff gpio: Add missing parenthesis to the GPIO_TO_PORT define
Add missing parenthesis to the GPIO_TO_PORT macro.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Heiko Schocher
46e10e922a pwm: imx: add DM_PWM support
add DM support for pwm-imx driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-19 20:14:50 +02:00
Heiko Schocher
e0f0657ddf pwm: imx: add Kconfig support
add Kconfig support for this driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Martyn Welch <martyn.welch@collabora.co.uk>
2019-07-19 20:14:50 +02:00
Tom Rini
cfe987ea84 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Update SiFive Unleashed clock driver.
- Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed
  board
2019-07-19 10:11:45 -04:00
Matti Vaittinen
21b02414f1 regulator: bd718x7: support ROHM BD71837 and BD71847 PMICs
BD71837 and BD71847 is PMIC intended for powering single-core,
dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847
is used for example on NXP imx8mm EVK.

Add regulator driver for ROHM BD71837 and BD71847 PMICs.
BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced
version containing 6 bucks and 6 LDOs. Voltages for DVS
bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted
when regulators are enabled. For other bucks and LDOs we may
have over- or undershooting if voltage is adjusted when
regulator is enabled. Thus this is prevented by default.

BD718x7 has a quirk which may leave power output disabled
after reset if enable/disable state was controlled by SW.
Thus the SW control is only allowed for BD71837  bucks
3 and 4 by default. The impact of this limitation must be
evaluated board-by board and restrictions may need to be
modified. (Linux driver get's these limitations from DT and we
may want to implement same on u-Boot driver).

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-19 15:18:47 +02:00
Peng Fan
5ef5b6d46f thermal: add i.MX8 thermal driver
Add i.MX8 thermal driver to support get temperature from SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 15:17:05 +02:00
Peng Fan
7752a0fef7 misc: imx8: add sc_misc_get_temp
Add sc_misc_get_temp to support get temperature

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 15:16:54 +02:00
Lukasz Majewski
d99b018a6e spi: mxs: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion)
This patch converts mxs_spi driver to support DM/DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19 14:57:14 +02:00
Lukasz Majewski
0f66653310 pinctrl: mxs: Add support for i.MX2[38] mxs pinctrl driver
The code responsible for setting proper values in the MUX registers
(in the mxs_pinctrl_set_state()) has been ported from Linux kernel
- SHA1: 17bb763e7eaf tag v5.1.11 from linux-stable.

As the pinctrl node in the imx28.dtsi file has gpio pins nodes as subnodes,
it was necessary to use 'dm_scan_fdt_dev()' (as a .bind method) to also
make them 'visible' by the DM's "gpio_mxs" driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19 14:57:14 +02:00
Lukasz Majewski
397af35601 gpio: mxs: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO)
This patch adds support for DM/DTS in the mxs_gpio.c driver.
Information regarding per gpio controller pin number is passed via DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19 14:57:14 +02:00
Lukasz Majewski
7782f4e441 net: fec: Enable support for i.MX28 DM_ETH in the fec_mxc.c driver
The fec_mxc.c driver can be reused by i.MX28 when DM_ETH is enabled.
One only needs to add proper compatible and dependency on FEC_MXC in the
Kconfig.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19 14:57:14 +02:00
Shyam Saini
1d43e24b94 i.MX6: nand: add nandbcb command for imx
Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.

It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.

It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.

So, cmd_nandbcb implemented in arch/arm/mach-imx

BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.

On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
  1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocks

for nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.

Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.

Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
2019-07-19 14:51:25 +02:00
Lukasz Majewski
87e460c304 clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]
This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.

In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.

Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
5da0095e3a clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HW
The generic mux clock code for CCF requires reading the clock multiplexer
value from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the mux structure (accessible only when sandbox is run)
has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
6bb15d6f07 clk: sandbox: Adjust clk-divider to emulate reading its value from HW
The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
1a961c9b32 dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flag
If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate()
provides recalculated clock value without considering the cache setting.

This may be necessary for some clocks tightly coupled with power domains
(i.e. imx8), and prevents from reading invalid cached values.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
1d7993d1d0 clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y
SHA1: 5752b50477da)to provide clocks support as it is used on the Linux
kernel with Common Clock Framework [CCF] setup.

The directory structure has been preserved. The ported code only supports
reading information from PLL, MUX, Divider, etc and enabling/disabling
the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic
to the alias numbering as the information about the clock is read from the
device tree.

One needs to pay attention to the comments indicating necessary for U-Boot's
driver model changes.

If needed, the code can be extended to support the "set" part of the clock
management.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
2796af7368 dm: clk: Define clk_get_by_id() for clk operations
This commit adds the clk_get_by_id() function, which is responsible
for getting the udevice with matching clk->id. Such approach allows
re-usage of inherit DM list relationship for the same class (UCLASS_CLK).
As a result - we don't need any other external list - it is just enough
to look for UCLASS_CLK related udevices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
4aa78300a0 dm: clk: Define clk_get_parent_rate() for clk operations
This commit adds the clk_get_parent_rate() function, which is responsible
for getting the rate of parent clock.
Unfortunately, u-boot's DM support for getting parent is different
(the parent relationship is in udevice) than the one in Common Clock
Framework [CCF] in Linux.

To alleviate this problem - the clk_get_parent_rate() function has been
introduced to clk-uclass.c.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
0c660c2b32 dm: clk: Define clk_get_parent() for clk operations
This commit adds the clk_get_parent() function, which is responsible
for getting the parent's struct clock pointer.

U-Boot's DM support for getting parent is different (the parent
relationship is in udevice) than the one in Common Clock Framework [CCF]
in Linux. To obtain the pointer to struct clk of parent the
pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
36bac0a193 clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)
Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK
without declaring struct clk. As a result it was only accessible by
iterating the udevice's uclass list.

This is a problem for clock code, which operates on pointers to struct
clk (like clk_get_rate()), not udevices.

After this change struct clk is accessible from udevice and udevice from
struct clk.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
ec8f1c02dd clk: Remove clock ID check in .get_rate() of clk_fixed_*
This check requires the struct clk passed to .get_rate() to be always
cleared out as any clock with valid ID causes -EINVAL return value.

The return code of fixed clocks shall always be returned.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Anup Patel
8633edeb2a clk: sifive: Drop GEMGXL clock driver
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
ed0ef3776c clk: sifive: Sync-up main driver with upstream Linux
The DT bindings of SiFive clock driver in upstream Linux has
changes. As-per latest DT bindings, the clock driver takes two
parent clocks and compatible string has also changed.

This patch sync-up SiFive clock driver implementation as-per
upstream Linux so that we now use latest DT bindings.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
66591a719a clk: sifive: Sync-up DT bindings header with upstream Linux
The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
c236802696 clk: sifive: Sync-up WRPLL library with upstream Linux
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
d04c79d2b2 clk: sifive: Factor-out PLL library as separate module
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Jagan Teki
1ff5283d92 ram: rk3399: Compute stride for 1 channel a
Add stride computation for the sdram which support
single channel a

This configuration available in NanoPi NEO4 and the
same can work with existing rk3399-sdram-ddr3-1866.dtsi

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
4b09719c38 ram: rk3399: Compute stride for 2 channels
stride value from sdram timings can be computed dynamically
based on the determined capacity for the given channel.

Right now these stride values are taken as part of sdram timings
via dtsi, but it possible to use same timings dtsi for given
frequency even though the configured board sdram do support
single channel with different size by dynamically detect the
stride value.

Example, NanoPi NEO4 do have DDR3-1866, but with single channel
and 1GB size with dynamic stride detection it is possible to
use existing rk3399-sdram-ddr3-1866.dtsi whose stride,
number of channels and capacity it support is d efferent.

So, add initial support to calculate the stride value for
2 channels sdram, which is available by default on existing
boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
cb13534abe ram: rk3399: debug: Add sdram_print_stride
Add code to print the channel stride, this would help to
print the stride of associated channel.

Here is sample print on LPDDR4, 50MHz.
256B stride

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
79674a6278 ram: rockchip: debug: Get the cs capacity
Add code to get the channel capacity, this would help to
print the capacity of specific channel.

Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
07894f5aac ram: rockchip: debug: Add sdram_print_ddr_info
Add sdram ddr info print support, this would help to
observe the sdram base parameters.

Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
07112672a5 ram: rockchip: Add debug sdram driver
Add sdram driver to handle debug across rockchip SoCs.

This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
82ee138def ram: rockchip: Add initial Kconfig
Right now sdram drivers in rockchip SoC are built based
on the SoC configs which may not be an adequate solutions
while adding common or debug driver.

So, add meaningful Kconfig options start with rk3399.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
a0aebe8398 ram: rk3399: Add pctl start support
Add support for pctl start for both channel 0, 1 control
and phy registers.

This would also handle pwrup_srefresh_exit init based
on the channel number.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
fe42d4a199 ram: rk3399: Move pwrup_srefresh_exit to dram_info
Add pwrup_srefresh_exit to be part of dram_info so-that
the it can help to support pwrup_srefresh_exit in individual
channels while starting pctl in future.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
33921035be ram: rk3399: Add phy pctrl reset support
Add support for phy pctrl reset support for both channel 0, 1.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
21cf392b1f ram: rk3399: Use rank mask in wdql data training
Add rank_mask based on the rank number, this would keep
the wdql data training loop based on the desired rank mask
value instead of looping for all values.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
708e9a79dc ram: rk3399: Use rank mask in ca data training
Add rank_mask based on the rank number, this would keep
the ca data training loop based on the desired rank mask
value instead of looping for all values.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
01976ae6f5 ram: rk3399: Clear PI_175 interrupts in data training
Clear the PI_175 interrupts before processing actual
data training in all relevant calls.

This would help to clear interrupt from previous training.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
02fad6f9ed ram: rk3399: Handle data training return types
data trainings calls like ca, wl, rg, rl, wdql have proper
return types with -EIO and the return type missed to handle
in data_training function.

This patch, add proper return type checks along with useful
debug statement on each data training calls.

Incidentally this would help to prevent the sdram initialization
hang for single channel dram and when the code is trying to
initialize second channel with proper return type of relevant
data training call might failed.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
dd7dfa217e clk: rockchip: rk3399: Fix check patch warnings and checks
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements

Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
355490dc5c ram: rockchip: rk3399: Add cap_info structure
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig

into a common cap_info structure for more code readability and extend
if possible based on the new features.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
9c4d517db8 ram: rk3399: Order tsel variables
Order tsel* variable declarations and assignment in proper
and meaningful way.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
30bd86a399 ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based
on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
a12a5be7a3 ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based
on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
a5085ee4e8 ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
Rename tsel_wr_select_p to tsel_wr_select_dq_p based
on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
fa2b015b9c ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
Rename tsel_wr_select_n to tsel_wr_select_dq_n based
on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
d4b4bb47c6 ram: rk3399: Handle pctl_cfg return type
Add proper return type handling of pctl_cfg with
meaningful print statement.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
fde7f457e1 ram: rk3399: s/sdram_params/params
Rename variable name of struct rk3399_sdram_params
from sdram_params with params for more code readability.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
3eaf539849 ram: rk3399: Some trivial code fixes
- Add proper spaces in data training, rk3399_dmc_init, pctl_cfg
- Order include files
- Move macro after include files

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
63f4d716b1 ram: rk3399: Fix code warnings
Fix checkpatch warninigs on sdram_rk3399.c like
- Avoid CamelCase
- Unnecessary parentheses
- Alignment should match open parenthesis
- multiple blank lines
- misspelled
- spaces preferred around that '>>'

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Mark Kettenis
c908d46f3a rockchip: xhci: Remove RK3399 support
Remove RK3399 compatible strings as this driver is no longer
used on that SoC.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Mark Kettenis
062790f461 usb: xhci-dwc3: Add USB2 PHY configuration
Configure USB2 PHY register based on "phy_type" property and
handle all the quirks that are relevant for Rockchip RK3399 SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Mark Kettenis
aaa8d6b149 usb: dwc3-of-simple: Add support for RK3399
Add compatible string for RK3399 and enable it by default on
Rockchip platforms with USB3 support.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Mark Kettenis
555ceca088 rockchip: clk: rk3399: handle clk_enable requests for USB3
The "simple" OF glue layer for the Designware USB3 core enables
all refernced clocks.  These need to be need to be implemented
otherwise the driver fails to probe.  A dummy implementation
that simply returns success is sufficient since the RK3399 comes
out of reset with all clock gates open.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Tom Rini
62a09f45ab Merge branch 'master' of git://git.denx.de/u-boot-net 2019-07-18 20:32:07 -04:00
Simon Goldschmidt
4ee587e2cf net: designware: remove mdio bus on probe failure
The designware eth driver registers an mdio bus during probe, but if no
PHY is found, this bus is never removed although probe failes and the
driver is shown as not probed in the dm tree.

This later leads to errors when e.g. the mii or mdio commands try to
use available mdio buses because the mdio bus is still registered but
all corresponding data structures are invalid because probe failed.

Fix this by unregistering the mdio bus on probe failure (just as it is
unregistered in the .remove callback, too).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-18 16:37:13 -05:00
Alex Marginean
c3d9f3f899 test: dm: add a test for MDIO MUX DM uclass
Adds a test using a makeshift MDIO MUX.  The test is based on the existing
MDIO test.  It uses the last emulated PHY register to verify MUX selection.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-18 16:37:13 -05:00
Alex Marginean
b47edf8069 test: dm_mdio: add a 2nd register to the emulated PHY
This 2nd register is used by the follow-up MDIO MUX test.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-18 16:37:13 -05:00
Alex Marginean
8880edba06 net: add MDIO_MUX DM class
Adds a class for MDIO MUXes, which control access to a series of
downstream child MDIOs.
MDIO MUX drivers are required to implement a select function used to switch
between child buses.
MUX children are registered as MDIO buses and they can be used just like
regular MDIOs.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-18 16:37:13 -05:00
Alex Marginean
3bf135b6c3 drivers: net: phy: Ignore PHY ID 0 during PHY probing
Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-18 16:37:13 -05:00
Alexandru Marginean
14df216d10 drivers: net: phy: Use Aquantia driver for AQR112, AQR412
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-18 16:37:13 -05:00
Tom Rini
0de8153564 Merge branch '2019-07-17-master-imports'
- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support.
2019-07-18 11:31:37 -04:00
Ramon Fried
eb18742575 pci_ep: fix wrong addressing to barno
barno was mistakely readed from the target structure,
resulting in undefined behavious depending on the previous memory
content. fix that.

Fixes: bb41333782 ("pci_ep: add pci endpoint sandbox driver")
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
[trini: Drop unused bar_idx]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-18 11:31:32 -04:00
Weijie Gao
0ebe112d09 blk: Invalidate block cache when switching hwpart
Some storage devices have multiple hw partitions and both address from
zero, for example eMMC.
However currently block cache invalidation only applies to block
write/erase.
This can cause a problem that data of current hw partition is cached
before switching to another hw partition. And the following read
operation of the latter hw partition will get wrong data when reading
from the addresses that have been cached previously.

To solve this problem, invalidate block cache after a successful
select_hwpart operation.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18 11:31:31 -04:00
Sven Schwermer
aa2067a869 regulator: Allow enabling GPIO regulator
Drivers need to be able to enable regulators that may be implemented as
GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is
commonly implemented as a GPIO regulator in order to switch between I/O
voltage levels.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18 11:31:25 -04:00
Sven Schwermer
2f7a5f2682 regulator: Factor out common enable code
In preparation of being able to enable/disable GPIO regulators, the
code that will be shared among the two kinds to regulators is factored
out into its own source files.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18 11:31:24 -04:00
Chuanhua Han
55f2bc7dd6 rtc: Add DM support to ds3231
Add an implementation of the ds3231 driver that uses the driver
model i2c APIs.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18 11:31:23 -04:00
Ashish Kumar
8385520f29 mtd: spi: Add flash property for Micron mt25qu512a
mt25qu512a is rebranded after its spinoff from STM, so it is
different only in term of extended jedec ID, initial JEDEC id
is same as that of n25q512a.In order to avoid any confussion
with respect to name new entry is added.

This flash is tested for Single I/O mode on LS1046FRWY although
it also support QUAD I/O.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18 17:11:16 +05:30
Bhargav Shah
a2f32bfdd3 spi: Add SiFive SPI driver
This patch adds SiFive SPI driver. The driver is 100% DM driver
and it determines input clock using clk framework.

The SiFive SPI block is found on SiFive FU540 SOC and is used to
access flash and MMC devices on SiFive Unleashed board.

This driver implementation is inspired from the Linux SiFive SPI
driver available in Linux-5.2 or higher and SiFive FSBL sources.

Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18 17:11:16 +05:30
Anup Patel
a706029410 mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
SPI_XFER_END flags to enable/disable slave chip select.

This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
MMC command is send at start and pass SPI_XFER_END flag using a
dummy transfer (of bitlen = 0) at the end of MMC command.

Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18 17:11:16 +05:30
Thomas Schaefer
733391e84b drivers/spi: fsl_qspi: improve timeout calculation
Use readl_poll_timeout instead of explicit calculation

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18 17:11:16 +05:30
Thomas Schaefer
c6d0c5eb30 drivers/spi: fsl_qspi: fix read timeout
During QSPI reads, current is_controller_busy function sporadically
fails with -ETIMEDOUT due to fixed number of 5 test loops. Using
timer functions to wait 1000 us instead will fix this.

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18 17:11:16 +05:30
Ye Li
535b1fdb8e spi: spi-mem: Fix read data size issue
When slave drivers don't set the max_read_size, the spi-mem should directly
use data.nbytes and not limit to any size. But current logic will limit to
the max_write_size.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18 17:11:16 +05:30
Vignesh R
14106bcadb i2c: omap24xx_i2c: Adapt driver to support K3 devices
K3 devices have I2C IP that is same as OMAP2+ family. Allow driver to be
compiled for ARCH_K3.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-17 11:12:54 -04:00
Andreas Dannenberg
70942db4dd mmc: am654_sdhci: Allow driver to probe without PDs specified
We would like to use the driver even without power domains being
specified for cases such as during early boot when the required power
domains have already gotten enabled by the SoC's boot ROM and such
explicit initialization is not needed and possible.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:54 -04:00
Faiz Abbas
f605807f3d mmc: am654_sdhci: Add a platform specific set_control_reg() callback
Add a platform specific set_control_reg() callback to help switch to
UHS speed modes.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
d1c0a2200a mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.

Also create a common API to set UHS timings in HOST_CONTROL2.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
ce142ff0c5 mmc: am654_sdhci: Add Support for PHY
Add support in the driver for handling phy specific registers.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
a8185c50d3 mmc: sdhci: Make set_ios_post() return int
Make set_ios_post() return int to faciliate error handling in
platform drivers.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
3966c7d006 mmc: sdhci: Make sdhci_set_clock() non static
The am654_sdhci driver needs to switch the clock off
before disabling its phy dll and needs to re-enable
the clock before enabling the phy again.

Therefore, make the sdhci_set_clock() function accessible
in the am654_sdhci driver.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask
Add Support for masking some bits in the capabilities
register of a host controller.

Also remove the redundant readl() into caps1.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
55a1a09b2a regmap: Add API regmap_init_mem_index()
In device nodes with more than one entry in the reg property,
it is sometimes useful to regmap only of the entries. Add an
API regmap_init_mem_index() to facilitate this.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
6fca7fb3a0 mmc: am654_sdhci: Remove quirks
The host controller works perfectly well without having to add any
quirks. Remove them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Faiz Abbas
3a1a0dfc39 arm64: dts: k3: Sync sdhci0 node from kernel and change driver name
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.

Also change the name of the driver to match the compatible in kernel.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17 11:12:08 -04:00
Tom Rini
0e80dda32c Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Beelink-x2 STB support (Marcus)
- H6 DDR3, LPDDR3 changes (Andre, Jernej)
- H6 pin controller, USB PHY (Andre)
2019-07-16 11:19:31 -04:00
Andre Przywara
35fa673e0e sunxi: phy: Add USB PHY support for Allwinner H6
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual),
which require a small addition to the USB PHY driver:
In this case the second PHY is PHY3, not PHY1, so we need to skip number
1 and 2 in the code. Just use the respective code from Linux for that.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Andre Przywara
106c1300a5 sunxi: clocks: Add H6 USB clock gates and resets
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Andre Przywara
0d3c77f5c3 sunxi: gpio: Enable support for H6 pin controller
The Allwinner H6 pin controller is not really special, at least not when
it comes to normal GPIO operation.

Add the H6 compatible strings to the list of recognised strings, to make
GPIOs work for H6 boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Andre Przywara
10cfbaabc1 sunxi: move SUNXI_GPIO to Kconfig
Probably for no particular reason SUNXI_GPIO was still defined the "old
way", in header files only.

Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove
another line from our dreadful config_whitelist.txt.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Tom Rini
9c94e0a644 Merge branch 'master' of git://git.denx.de/u-boot-net 2019-07-15 18:56:24 -04:00
Radu Pirea
0dc97fc3d8 net: macb: Add support for 1000-baseX
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX
phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and
LPA_1000XHALF bits.

Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:26 -05:00
Radu Pirea
1b0c9914cc net: macb: Fixed reading MII_LPA register
If macb is gem and is gigabit capable, lpa value is not read from
the right register(MII_LPA) and is read from MII_STAT1000. This patch
fixes reading of the lpa value.

Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:26 -05:00
Keerthy
9d0dca1199 net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Independent Interface (RMII), and the Management Data Input/Output (MDIO)
interface for physical layer device (PHY) management. The TI AM65x SoC has
integrated two-port Gigabit Ethernet Switch subsystem into device MCU
domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
and RMII interfaces and an internal Communications Port Programming
Interface (CPPI) port (Host port 0).

Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
channels and on RX channels operating by TI am654 NAVSS Unified DMA
Peripheral Root Complex (UDMA-P) controller.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Keerthy
45e8c055cc driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addr
Use phys_addr_t for mdio_base address to avoid build
warnings on arm64 and dra7. Cast it to uintprt_t before
assigning to regs.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Yinbo Zhu
4db6e790ba net: phy: cortina: Use block layer to read from mmc
This patch is to use block layer to read from mmc in cortina

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Horatiu Vultur
61243678c2 net: mscc: refactor mscc_miim
Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Alex Marginean
ec9594a50f test: dm: add MDIO test
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Alex Marginean
c3452b50c3 net: introduce MDIO DM class for MDIO devices
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices.  Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Horatiu Vultur
149468699e net: mscc: serval: Remove delay when serdes is configured
When serdes configuration was written in hardware there was a delay
of 100ms to be sure that configuration was written. But the delay is not
needed because already the function serdes_write it is checking that the
operation finished.

Therefore remove the mdelay. This improves the speed of configuring the
network driver.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Trent Piepho
2529dea893 net: phy: ti: Fix clock output DT property
The code block reading the DT property for the clock output control was
before the phy's DT node pointer was set, so it could never work.  Move
it after the node pointer is set.

Also store the unsigned 32-bit property into an unsigned value, not a
signed value, as the former will cause a problem if value overflows.
For instance, if one were to add 0xffffffff as a code to mean the clock
output should be turned off.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Trent Piepho
c2df9b49ce net: phy: ti: Use default values for tx/rx delay and fifo size
When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver.  When using DM_ETH, they should come
from the device tree.  However, if the device tree does not have the
properties, the driver will silent use -1.  Which is entirely out of
range, programs nonsense into the PHY's registers, and does not work.

Change this to use the same defaults as non-DM_ETH if the device tree is
lacking the properties.

As an alternative, the kernel driver for the phy will display an error
message and fail if the device tree is lacking.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15 13:32:25 -05:00
Tom Rini
6674dc77c2 Merge tag 'mmc-2019-7-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- mmc spi driver model support
- drop mmc_spi command
- enhanced Strobe mmc HS400 support
- minor mmc bug/fixes and optimization
- omap hsmmc and mvbeu update
- sdhci card detect support
2019-07-15 09:42:41 -04:00
Peng Fan
356f782c6e mmc: fsl_esdhc_imx: enlarge mmc timeout
Flash system partition with fastboot will earse the partition firstly
The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make
it works for most of sdcard

Cc: guoyin.chen <guoyin.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15 10:30:09 +08:00
Peng Fan
609ba125c5 mmc: fsl_esdhc_imx: add i.MX8QM compatible
Add i.MX8QM compatible and soc data, the soc data is following Linux
i.MX SDHC driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15 10:30:09 +08:00
Peng Fan
e9c2255267 mmc: fsl_esdhc_imx: add HS400 Enhanced strobe support
Implement set_enhanced_strobe hook for fsl_esdhc_imx,
,in esdhc_set_timing and esdhc_change_pinstate, also handle HS400_ES.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15 10:30:09 +08:00
Peng Fan
b0155ac63c mmc: fsl_esdhc_imx: use mmc_of_parse to set host_caps
Use mmc_of_parse to set host_caps.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15 10:30:09 +08:00
Peng Fan
479a8dd6dc mmc: Parse no-1-8-v DT property
Parse no-1-8-v DT

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-07-15 10:30:08 +08:00
Peng Fan
b0fc3127bd mmc: Parse HS400 Enhanced strobe DT properties
Add HS400 Enhanced strobe properties parsing support to mmc_of_parse().

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-07-15 10:30:08 +08:00
Peng Fan
44acd49248 mmc: support hs400 enhanced strobe mode
eMMC 5.1+ supports HS400 Enhances Strobe mode without the need for
tuning procedure.
The flow is as following:
 - set HS_TIMIMG (Highspeed)
 - Host change freq to <= 52Mhz
 - set the bus width to Enhanced strobe and DDR8Bit(CMD6),
   EXT_CSD[183] = 0x86 instead of 0x80
 - set HS_TIMING to 0x3 (HS400)
 - Host change freq to <= 200Mhz
 - Host select HS400 enhanced strobe complete

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15 10:30:08 +08:00
Ye Li
8277171663 mmc: fsl_esdhc_imx: fix config check issue when building in SPL
Should use CONFIG_IS_ENABLED not IS_ENABLED for clock and regulator drivers,
CONFIG_IS_ENABLED will check the CONFIG_SPL_CLK and CONFIG_SPL_DM_REGULATOR
when building SPL.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15 10:30:08 +08:00
Bhargav Shah
05e35d4297 mmc: mmc_spi: Re-write driver using DM framework
This patch rewrites MMC SPI driver using U-Boot DM
framework and get it's working on SiFive Unleashed
board.

Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15 10:16:49 +08:00
Anup Patel
f49ff79935 mmc: skip select_mode_and_width for MMC SPI host
The MMC mode and width are fixed for MMC SPI host hence we skip
sd_select_mode_and_width() and mmc_select_mode_and_width() for
MMC SPI host.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
0538477c53 mmc: retry a few times if a partition switch failed
This operation may fail. Retry it a few times before giving up and report
a failure.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
9bc5666c8a mmc: do not change mode when accessing a boot partition
Accessing the boot partition had been error prone with HS200 and HS400 and
was disabled. The driver first switched to a lesser mode and then switched
the partition access. It was mostly due to a bad handling of the switch and
has been fixed, so let's remove this 'feature'

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
bb98b8c5c0 mmc: During a switch, poll on dat0 if available and check the final status
The switch operation can sometimes make the bus unreliable, in that case
the send_status parameter should be false to indicate not to poll using
CMD13. If polling on dat0 is possible, we should use it to detect the end
of the operation.
At the end of the operation it is safe to use CMD13 to get the status of
the card. It is important to do so because the operation may have failed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
513e00b64e mmc: When switching partition, use the timeout specified in the ext_csd
The e-MMC spec allows the e-MMC to specify a timeout for the partition
switch command. It can take up to 2550 ms. There is no lower limit to this
value in the spec, but do as the the linux driver does and force it to be
at least 300ms.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
39320c537d mmc: use the generic timeout for cmd6 (SWITCH) provided in the ext_csd
Starting with rev 4.5, the eMMC can define a generic timeout for the
SWITCH command.

Following Linux Kernel code, the timeout also changed from 1000 -> 500

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
cd0b80ec9c mmc: if possible, poll the busy state using DAT0
Using the DAT0 line as a rdy/busy line is an alternative to reading the
status register of the card. It especially useful in situation where the
bus is not in a good shape, like when modes are switched.
This is also how the linux driver behaves.

Note of warning: As per the specification, while polling on DAT0 the CLK
must not turned off: "[...] Without a clock edge the Device (unless
previously disconnected by a deselect command (CMD7)) will force the DAT0
line down, forever. [...]"

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
863d10044a mmc: add mmc_poll_for_busy() and change the purpose of mmc_send_status()
mmc_send_status() is currently used to poll the card until it is ready, not
actually returning the status of the card.
Make it return the status and add another function to poll the card.

Also remove the 'extern' declaration in the mmc-private.h header to comply
with the coding standard.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
c2c22b9df3 mmc: omap_hsmmc: provide wait_dat0 even if UHS modes are not supported
This function can also be used for eMMC devices.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
c5bda37589 Revert "mmc: Add a new callback function to perform the 74 clocks cycle sequence"
This reverts commit 318a7a576b.

The last and only user of this callback had been the omap_hsmmc driver.
It is not used anymore. Removing the callback.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
db52e19ced mmc: omap_hsmmc: don't fill the send_init_stream callback
This is not required. The MMC core sends CMD0 right after the
initialization and it serves the same purpose.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Jean-Jacques Hiblot
b2ffa3320a mmc: omap_hsmmc: reset FSM for DAT and CMD lines if needed before a new command
It sometimes happen that the PSTATE register does not indicate that the
bus is ready when it really is. This usually happens after a mode switch.
In that case it makes sense to reset the FSM handling the CMD and DATA

Also reset the FSMs if the STATE register cannot be cleared. This also
sometimes happens after a mode switch.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15 10:16:49 +08:00
Akio Hirayama
24b1e0c7e2 mmc: rpmb: fix response type of CMD25
The response type of CMD25 is R1 instead of R1b.

Signed-off-by: Akio Hirayama <hirayama.akio@socionext.com>
[masahiro: add log ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-15 10:16:49 +08:00
T Karthik Reddy
da18c62b6e mmc: sdhci: Implement SDHCI card detect
Card detect function implemented for SDHCI framework.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-15 10:16:49 +08:00
T Karthik Reddy
451931ea70 mmc: sdhci: Read cd-gpio from devicetree
This patch reads cd-gpio property from devicetree

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-15 10:16:49 +08:00
T Karthik Reddy
86a94e7b2b mmc: Read sd card detect properties from DT
This patch reads card detect properties from device tree &
added mmc capability macros in mmc.h.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-15 10:16:49 +08:00
Tom Rini
a9a3a37f92 - syscon: add support for power off
- stm32mp1: add op-tee config
 - stm32mp1: add specific commands: stboard and stm32key
 - add stm32 mailbox driver
 - solve many stm32 warnings when building with W=1
 - update stm32 gpio driver
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Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- syscon: add support for power off
- stm32mp1: add op-tee config
- stm32mp1: add specific commands: stboard and stm32key
- add stm32 mailbox driver
- solve many stm32 warnings when building with W=1
- update stm32 gpio driver
2019-07-14 09:09:49 -04:00
Sven Schwermer
1164c546d5 regulator: Allow autosetting fixed regulators
Fixed regulators don't have a set_value method. Therefore, trying to
set their value will always return -ENOSYS.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-13 11:11:31 -04:00
Heiko Schocher
5fc7cf8c8e gpio: add gpio-hog support
add gpio-hog support. GPIO hogging is a mechanism
providing automatic GPIO request and configuration
as part of the gpio-controller's driver probe function.

for more infos see:
doc/device-tree-bindings/gpio/gpio.txt

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Michal Simek <michal.simek@xilinx.com> (zcu102)
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-13 11:11:30 -04:00
Adam Ford
159a887e74 pinctrl: pinctrl-single: Add 'pinctrl-single, bits' support
The TI Davinci (da850/l138/am1808) use pinctrl-single,bits for
pinmuxing peripherals.  This patch allosw the pinctrl-single
driver to parse the pinctrl-single,bits options and correctly
setup devices.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-13 11:11:29 -04:00
Keerthy
28115e7bac power: regulator: Kconfig: Add SPL_DM_REGULATOR configs for palmas/lp873x/lp87565
Add SPL_DM_REGULATOR configs for palmas/lp873x/lp87565. These were missing
and the Makefile already assumes them to be defined. Add the corresponding
SPL config options. This enables the regulator support in SPL.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-07-13 11:11:29 -04:00
Keerthy
2463874883 power: pmic: Kconfig: Add SPL_PMIC configs for palmas/lp873x/lp87565
Add SPL_PMIC configs for palmas/lp873x/lp87565. These were missing
and the Makefile already assumes them to be defined. Add the corresponding
SPL config options. This enables the pmics in SPL.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-07-13 11:11:28 -04:00
Michael Walle
fb9a1ffef3 rtc: add Microcrystal RV-8803 driver
Signed-off-by: Michael Walle <michael@walle.cc>
2019-07-13 11:11:28 -04:00
Derald D. Woods
9adaa039b6 usb: musb-new: omap2430: Fix compilation warning with USB_MUSB_GADGET
This commit addresses the following warning, when _NOT_ USB_MUSB_HOST:

[...]
  CC      drivers/usb/gadget/f_mass_storage.o
  CC      drivers/usb/musb-new/omap2430.o
  CC      drivers/usb/gadget/f_fastboot.o
  CC      env/common.o
  CC      env/env.o
/src/etinker/software/u-boot-master/drivers/usb/musb-new/omap2430.c: In function ‘omap2430_musb_probe’:
/src/etinker/software/u-boot-master/drivers/usb/musb-new/omap2430.c:239:6: warning: assignment to ‘int’ from ‘struct musb *’ makes integer from pointer without a cast [-Wint-conversion]
  ret = musb_register(&platdata->plat,
      ^
  LD      drivers/usb/host/built-in.o
  CC      drivers/usb/gadget/f_sdp.o
  CC      fs/ext4/ext4fs.o
[...]

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2019-07-13 11:11:27 -04:00
Heiko Schocher
8dd6803ded rtc: ds1307: add support for m41t11
add m41t11 support in ds1307 driver. changes:

- add compatible string for m41t11
- check if RTC clock is running, if not
  enable the clock

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-13 11:11:26 -04:00
Ezequiel Garcia
d66fb5b1f6 mmc: Register only the first MMC device on MMC_TINY
When MMC_TINY is enabled, support for only one MMC device
is provided. Boards that register more than one device,
will just write over mmc_static keeping only the last one
registered.

This commit prevents this, keeping only the first MMC
device created. A debug warning message is added, if nothing
else, as a hint/documentation for developers.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
2019-07-13 11:11:26 -04:00
Ezequiel Garcia
bf7c01d92b spl: Move SPL_MMC_TINY option to appear under SPL menu
The SPL_MMC_TINY implements feature-reduced MMC support
on SPL, and as such, it's more consistent and convenient
to find it as part of the SPL configuration.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
2019-07-13 11:11:26 -04:00
Peng Fan
4213609cc7 drivers: core: use strcmp when find device by name
`if (!strncmp(dev->name, name, strlen(name)))` might find out
the wrong device, it might find out `dram_pll_ref_sel`, when name is
`dram_pll`. So use strcmp to avoid such issue.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-12 21:07:59 -04:00
Marek Behún
60ee60944b pci: ensure enumeration of all devices in pci_init
Use the uclass_first_device_check and uclass_next_device_check functions
instead of uclass_first_device and uclass_next_device in pci_init. This
ensures that all PCI devices are tried to be probed. Currently if a
device fails to probe, the enumeration stops and the devices which come
after the failed device are not probed.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-12 21:07:58 -04:00
Patrice Chotard
60bc487666 gpio: stm32: Remove .ofmatch callback
As compatible string "st,stm32-gpio" is no more used, .ofmatch
callback becomes useless, remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:58 +02:00
Patrice Chotard
158abbf57b pinctrl: stm32: update .bind callback
Update .bind callback in order to bind all pinctrl subnodes
with "gpio-controller" property to gpio_stm32 driver.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:58 +02:00
Patrice Chotard
95fbdd1ad8 gpio: stm32: Rename stm32f7_gpio to stm32_gpio
As this driver is used on stm32f4/f7/h7 and stm32mp1
SoCs, rename it with a more generic name.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:58 +02:00
Patrick Delaunay
54ef8fb86b spi: stm32: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/spi/stm32_spi.c: In function 'stm32_spi_write_txfifo':
drivers/spi/stm32_spi.c:116:20: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
   if (priv->tx_len >= sizeof(u32) &&
                    ^~
drivers/spi/stm32_spi.c:122:27: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
   } else if (priv->tx_len >= sizeof(u16) &&
                           ^~
drivers/spi/stm32_spi.c: In function 'stm32_spi_read_rxfifo':
drivers/spi/stm32_spi.c:150:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
                     ^~
drivers/spi/stm32_spi.c:156:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       (priv->rx_len >= sizeof(u16) ||
                     ^~
drivers/core/simple-bus.c:15:12: warning: no previous prototype for 'simple_bus_translate' [-Wmissing-prototypes]
 fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr)
            ^~~~~~~~~~~~~~~~~~~~
drivers/spi/stm32_spi.c: In function 'stm32_spi_set_speed':
drivers/spi/stm32_spi.c:335:10: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
      div > STM32_MBR_DIV_MAX)
          ^
drivers/spi/stm32_spi.c:344:19: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
  if ((mbrdiv - 1) < 0)
                   ^
drivers/spi/stm32_spi.c: In function 'stm32_spi_probe':
drivers/spi/stm32_spi.c:531:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
                ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:57 +02:00
Patrick Delaunay
1ddf544e63 spi: stm32_qspi: avoid warnings when building with W=1 option
This patch solves warnings detected by setting W=1 when building.

Warnings type detected:
 - [-Wtype-limits]
 - [-Wsign-compare]

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:57 +02:00
Patrick Delaunay
d99ea13cdf mtd: rawnand: stm32_fmc2: avoid warnings when building with W=1 option
This patch solves warnings detected by setting W=1 when building.

Warnings type detected:
 - [-Wsign-compare]
 - [-Wtype-limits]

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:57 +02:00
Patrick Delaunay
92be6834da power: stpmic1: Fix warnings when compiling with W=1
This patch solves the following warnings:
warning: this statement may fall through [-Wimplicit-fallthrough=]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:57 +02:00
Patrick Delaunay
91ca91e855 pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1
This patch solves the following warnings:

warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
    if (*idx < 0)
             ^
drivers/pinctrl/pinctrl_stm32.c: At top level:
warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes]
 int stm32_pinctrl_probe(struct udevice *dev)
     ^~~~~~~~~~~~~~~~~~~

Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:56 +02:00
Patrick Delaunay
588448517f ram: stm32mp1_ram: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/ram/stm32mp1/stm32mp1_ram.c: In function 'stm32mp1_ddr_clk_enable':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
                    ^
drivers/ram/stm32mp1/stm32mp1_ram.c: In function 'stm32mp1_ddr_setup':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
                    ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:56 +02:00
Patrick Delaunay
be56ab1b8f misc: stm32_fuse: Fix warnings when compiling with W=1
This patch solves the following warnings:

warning: no previous prototype for 'fuse_read' [-Wmissing-prototypes]
 int fuse_read(u32 bank, u32 word, u32 *val)
     ^~~~~~~~~
  CC      cmd/sf.o
warning: no previous prototype for 'fuse_prog' [-Wmissing-prototypes]
 int fuse_prog(u32 bank, u32 word, u32 val)
     ^~~~~~~~~
warning: no previous prototype for 'fuse_sense' [-Wmissing-prototypes]
 int fuse_sense(u32 bank, u32 word, u32 *val)
     ^~~~~~~~~~
warning: no previous prototype for 'fuse_override' [-Wmissing-prototypes]
 int fuse_override(u32 bank, u32 word, u32 val)
     ^~~~~~~~~~~~~

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:56 +02:00
Patrick Delaunay
c8a8937b92 power: regulator: stm32: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/power/regulator/stm32-vrefbuf.c: In function 'stm32_vrefbuf_set_value':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
   if (uV == stm32_vrefbuf_voltages[i]) {
          ^~

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:56 +02:00
Patrick Delaunay
67d74ce2fa clk: clk_stm32mp1: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/clk/clk_stm32mp1.c: In function 'stm32mp1_clk_get_parent':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
                ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:55 +02:00
Patrick Delaunay
499504ba06 i2c: stm32f7_i2c: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/i2c/stm32f7_i2c.c: In function 'stm32_i2c_compute_solutions':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    if (scldel < scldel_min)
               ^
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
     if (((sdadel >= sdadel_min) &&
                  ^~
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
          (sdadel <= sdadel_max)) &&
                  ^~
drivers/i2c/stm32f7_i2c.c: In function 'stm32_i2c_choose_solution':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
      if (clk_error < clk_error_prev) {
                    ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:55 +02:00
Patrick Delaunay
99e14b2793 gpio: stm32_gpio: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/gpio/stm32_gpio.c: In function 'stm32_offset_to_index':
: comparison between signed and unsigned integer expressions [-Wsign-compare]
    if (idx == offset)
            ^~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:55 +02:00
Patrick Delaunay
c0d7f1fbad adc: stm32: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/adc/stm32-adc-core.c: In function 'stm32h7_adc_clk_sel':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
   for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
                 ^
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
                ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com>
2019-07-12 11:50:55 +02:00
Patrick Delaunay
0fb0365673 adc: stm32-adc: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/adc/stm32-adc.c: In function 'stm32_adc_chan_of_init':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  if (num_channels > adc->cfg->max_channels) {
                   ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com>
2019-07-12 11:50:55 +02:00
Patrick Delaunay
0e9fb25f71 mmc: stm32_sdmmc2: avoid warnings when building with W=1 option
This patch solves warnings detected by setting W=1 when building.

Warnings type detected:
 - [-Wmissing-prototypes]
 - [-Wimplicit-fallthrough=]

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:54 +02:00
Patrick Delaunay
585289b4fc serial: stm32: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/serial/serial_stm32.c: In function 'stm32_serial_probe':
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
  if (plat->clock_rate < 0) {
                       ^

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:54 +02:00
Patrick Delaunay
82cd1a2a04 pmic: stpmic1: add support for SYSRESET_POWER_OFF
Adds support for SYSRESET_POWER_OFF = PMIC power off used by command
power off and introduced by commit 751fed426f ("sysreset: Add a way
to find the last reset").
The driver use SYSRESET_POWER for the PMIC-level power cycle, with restart.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:18:53 +02:00
Patrick Delaunay
dfda7d4c83 stm32mp1: syscon: remove stgen
Reduce difference with kernel Linux device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:18:53 +02:00
Patrick Delaunay
486942184a sysreset: syscon: add support for power off
The new type sysreset 'POWER_OFF', introduced by
commit 751fed426f ("sysreset: Add a way to find the last reset")
is only supported for "syscon-poweroff" compatible.

For details see Linux binding:
./Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt

This patch removes the support of POWER_OFF for "syscon-reboot"
and keeps only the COLD reset (for command reset support)
and it introduces the compatible "syscon-poweroff"
for the POWER_OFF case.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:18:53 +02:00
Fabien Dessenne
01964d8e23 mailbox: introduce stm32-ipcc driver
On STM32 family, the IPCC peripheral allows the communication
between 2 processors offering doorbells mechanism.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-07-12 11:18:53 +02:00
Tom Rini
a9758ece08 - Sandbox improvements including .dts refactor
- Minor tracing and PCI improvements
 - Various other minor fixes
 - Conversion of patman, dtoc and binman to support Python 3
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Merge tag 'dm-pull-9jul19-take2' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

- Sandbox improvements including .dts refactor
- Minor tracing and PCI improvements
- Various other minor fixes
- Conversion of patman, dtoc and binman to support Python 3
2019-07-11 18:10:11 -04:00
Tom Rini
68deea2308 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- SPL SATA enhancements to allow booting from RAW SATA device
  needed for Clearfog (Baruch)
- Enable SATA booting on Clearfog (Baruch)
- Misc changes to Turris Omnia (Marek)
- Enable CMD_BOOTZ and increase SYS_BOOTM_LEN on crs305-1g-4s
  (Luka)
- Enable FIT support for db-xc3-24g4xg (Chris)
- Enable DM_SPI on Keymile Kirkwood board with necessary changes
  for this (Pascal)
- Set 38x and 39x AVS on lower frequency (Baruch)
2019-07-11 18:09:38 -04:00
Tom Rini
79b8d3c285 UniPhier SoC updates for v2019.10
- import DT updates from Linux
 
 - add UniPhier SPI controller driver
 
 - make U-Boot image for 64bit SoCs position independent
 
 - tidy up various init code for next generation SoCs
 
 - misc cleanups
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Merge tag 'uniphier-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2019.10

- import DT updates from Linux

- add UniPhier SPI controller driver

- make U-Boot image for 64bit SoCs position independent

- tidy up various init code for next generation SoCs

- misc cleanups
2019-07-11 18:08:44 -04:00
Marek Vasut
4a09831ab2 gpio: pca953x: Add TI TCA9539 compatible string
Add TI TCA9539 compatible string for yet another I2C GPIO expander.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-11 14:11:20 -04:00
Roman Kapl
27eb177b39 tpm: wait for valid status
The TPM specification says that the EXPECT_DATA bit is not valid until
the VALID bit is set. Wait for that bit to be set. Fixes problems with
Ifineon SPI TPM.

Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-07-11 14:11:18 -04:00
Ramon Fried
bb41333782 pci_ep: add pci endpoint sandbox driver
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-11 10:05:15 -04:00
Ramon Fried
c2ccc9e5cb pci_ep: add Cadence PCIe endpoint driver
Add Cadence PCIe endpoint driver supporting configuration
of header, bars and MSI for device.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-11 10:05:15 -04:00
Ramon Fried
914026d258 drivers: pci_ep: Introduce UCLASS_PCI_EP uclass
Introduce new UCLASS_PCI_EP class for handling PCI endpoint
devices, allowing to set various attributes of the PCI endpoint
device, such as:
* configuration space header
* BAR definitions
* outband memory mapping
* start/stop PCI link

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-11 10:05:15 -04:00
Pascal Linder
fd9d70d738 km/spi: remove deprecated SPI flash driver code for KM Kirkwood boards
KM Kirkwood boards now implement the driver model for its SPI flash
interface. Therefore, the old board specific claim and release functions
can be deleted. The preprocessor definition CONFIG_SYS_KW_SPI_MPP is yet
unused as well. All its appearances and dependencies are removed in the
kirkwood_spi driver, header files and finally the configuration whitelist.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-07-11 10:58:03 +02:00
Pascal Linder
f169653483 km/spi: add weak functions to kirkwood_spi driver (DM part)
The weak functions, known from the legacy code, are added to the DM part
as well. For this purpose, the release operation first needs to be
implemented. KM Kirkwood boards will overwrite those weak functions to
change the MPP configuration when claiming/releasing the bus, because the
hardware pins are shared between the SPI NOR and NAND devices.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-07-11 10:58:03 +02:00
Alex Marginean
b8e1f8270c drivers: pci: add API to issue FLR on a PCI function if supported
Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function,
if FLR is supported.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Alex Marginean
21ebbafde8 test: dm: Add a test for PCI Enhanced Allocation
This test is built on top of the existing swap_case driver.  It adds EA
capability structure support to swap_case and uses that to map BARs.
BAR1 works as it used to, swapping upper/lower case.  BARs 2,4 map to a
couple of magic values.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Alex Marginean
0b143d8ab2 drivers: pci: add map_bar support for Enhanced Allocation
Makes dm_pci_map_bar API available for integrated PCI devices that
support Enhanced Allocation instead of the original PCI BAR mechanism.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Patrick Delaunay
6998974926 fdt: Allow indicating a node is for U-Boot proper only
This add missing parts for previous commit 06f94461a9
("fdt: Allow indicating a node is for U-Boot proper only")

At present it is not possible to specify that a node should be used before
relocation (in U-Boot proper) without it also ending up in SPL and TPL
device trees. Add a new "u-boot,dm-pre-proper" boolean property for this.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:58 -06:00
Vabhav Sharma
1edc5688df drivers: serial: lpuart: Enable Little Endian Support
By default LPUART driver with compatible string "fsl,ls1021a-lpuart"
support big-endian mode.On NXP SoC like LS1028A LPUART IP is
little-endian,Added support to Fetch LPUART IP Endianness from lpuart
device-tree node.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:58 -06:00
Simon Glass
ca2abb75a0 spi: Avoid using malloc() in a critical function
In general we should avoid calling malloc() and free() repeatedly in
U-Boot lest we turn it into tianocore. In SPL this can make SPI flash
unusable since free() is often a nop and allocation space is limited.

In any case, these seems no need for malloc() since the number of bytes
is very small, perhaps less than 8.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d13f5b254a (spi: Extend the core to ease integration of SPI
	memory controllers)
2019-07-10 16:52:58 -06:00
Simon Glass
731ba3c0be blk: Allow control of the block cache in TPL
Generally block devices are not enabled in TPL, but in case they are,
add a Kconfig option for the block cache. This allows the setting (default
off) to be found with CONFIG_IS_ENABLED().

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:58 -06:00
Simon Glass
24c2776ba9 sandbox: Correct spi flash operation
Since the SPI nor conversion, 'sf probe' does not work on sandbox. Fix
this by using the expected compatible string in the flash node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: cd35365762 (mtd: sf_probe: remove spi-flash compatible)
2019-07-10 16:52:58 -06:00
Simon Glass
9072326a6a sandbox: Exit when SYSRESET_POWER_OFF is requested
At present this returns but it seems better to just exit sandbox
immediately.

Signed-off-by: Simon Glass <sjg@chromium.org>

reset
2019-07-10 16:52:58 -06:00
Tom Rini
ef8b7e045e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-i2c 2019-07-10 13:51:53 -04:00
Tom Rini
a52f1fe408 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-ubi
[trini: Migrate sama5d27_som1_ek_qspiflash/sama5d2_xplained_qspiflash
        for CONFIG_ENV_SECT_SIZE]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-10 13:18:54 -04:00
Masahiro Yamada
9a2f0e5ccd clk: uniphier: add EMMC clock for LD11, LD20, and PXs3
I also added comments for NAND clocks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:55 +09:00
Kunihiko Hayashi
9424ecd735 spi: Add SPI controller driver for UniPhier SoCs
Add SPI controller driver implemented in Socionext UniPhier SoCs.
This controller has the SPI master mode only.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2019-07-10 22:37:23 +09:00
Tom Rini
b4944e2574 First set of u-boot-atmel features and fixes for 2019.10 cycle
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Merge tag 'u-boot-atmel-2019.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features and fixes for 2019.10 cycle

This includes the Atmel QSPI driver and support for the at91 boards.
This is the port of the driver from Linux, mostly done by Tudor Ambarus.
2019-07-09 08:17:12 -04:00
Chuanhua Han
ef6c26d338 rtc: pcf2127: Fixed bug with rtc settings and getting error time
The previous pcf2127 RTC chip could not read and set the correct time.
When reading the data of internal registers, the read address was the
value of register plus 1. This is because this chip requires the host
to send a stop signal after setting the register address and before
reading the register data.

This patch sets the register address using dm_i2c_write and reads
the register data using the original dm_i2c_xfer in order to generate
a stop signal after the register address is set, and fixes the bug of
the original read and write time.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-07-09 10:51:12 +02:00
Tudor Ambarus
24c8ff4684 spi: Add Atmel QuadSPI driver
Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-09 09:26:43 +03:00
Melin Tomas
d3826fb052 xilinx_xiic: Fix transfer initialisation
Prior to starting a new transfer, conditionally wait for bus to not
be busy.

Reinitialise controller as otherwise operation is not stable.
For reference, see linux kernel
commit 9656eeebf3f1 ("i2c: Revert i2c: xiic: Do not reset controller before every transfer")

hs: Fixed DOS line endings
    added missing '\n'
    Fixed git commit description style

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2019-07-09 07:02:11 +02:00
Melin Tomas
5324e8ef6c xilinx_xiic: Fix fill tx fifo loop
Comparison should be against the actual message length, not loop index.

len is used for stopping while loop, pos is position in message.
stop should be sent when entire message is sent, not when
len and pos meet.

hs: fixed DOS line endings

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2019-07-09 07:02:11 +02:00
Ley Foon Tan
2d1e879c79 i2c: designware: Get clock rate from clock DM
Get clock rate from clock DM if CONFIG_CLK is enabled.
Otherwise, uses IC_CLK define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-07-09 07:02:11 +02:00
Jun Chen
e3b93dcee8 i2c: designware_i2c: Restore enable state after set speed
Before calling __dw_i2c_set_bus_speed(),
the I2C could already be set as ether enable or disable,
we should restore the original setting instead of enable i2c anyway.

This patch fix a bug happened in init function:
    __dw_i2c_init(){
            /* Disable i2c */
            ...
            __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
            writel(slaveaddr, &i2c_base->ic_sar);
            /* Enable i2c */
    }
In this case, enable i2c inside __dw_i2c_set_bus_speed() function
will cause ic_sar write fail.

Signed-off-by: Jun Chen <ptchentw@gmail.com>
2019-07-09 07:02:10 +02:00
Markus Klotzbuecher
a2257d378e ubispl: introduce separate CONFIG_UBI_SPL_SILENCE_MSG
This allows to silence ubi and ubispl individually.

Signed-off-by: Markus Klotzbuecher <markus.klotzbuecher@kistler.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kmpark@infradead.org>
2019-07-09 07:00:26 +02:00
Hamish Guthrie
6ea31cce0b ubispl: add support for loading volumes by name
The motivation is to use the UBI atomic volume rename functionality to
allow double copy software updates on UBI. To that end the SPL is
configured to always load the same volume name (e.g. "u-boot"),
whereas a software updater always installs into the secondary volume
"u-boot_r". After successful installation, these two volume names are
switched.

This extension is protected by #ifdefs as it will somewhat slow down
loading of volumes by id. This is because the code needs to disable
the optimization of ignoring all volume ids which are not
to-be-loaded, since these can only be resolved after attaching.

This adds two vtbl related functions from Linux, which are taken from
the same kernel version as the current main U-Boot UBI code (Linux 4.2
64291f7db5bd8).

Signed-off-by: Hamish Guthrie <hamish.guthrie@kistler.com>
Signed-off-by: Markus Klotzbuecher <markus.klotzbuecher@kistler.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kmpark@infradead.org>
2019-07-09 07:00:25 +02:00
Markus Klotzbuecher
5ebd3df64d ubi: fix UBI_SILENCE_MSG
- drop CONFIG_ prefix from kconfig entry
 - fix small compilation issue with CONFIG_UBI_SILENCE_MSG

Signed-off-by: Markus Klotzbuecher <markus.klotzbuecher@kistler.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kmpark@infradead.org>
2019-07-09 07:00:23 +02:00
Tom Rini
f5e73a34ed Merge tag 'mmc-6-23' of https://github.com/MrVan/u-boot
- Pull in the series to split fsl_esdhc for i.MX/non-i.MX cleanly
2019-07-08 15:59:41 -04:00
Tom Rini
29e9363504 - fix pwm backlight
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Merge tag 'video-for-2019.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- fix pwm backlight
2019-07-07 16:17:13 -04:00
Marc Dietrich
a2c4ef0977 video: backlight: fix pwm inversion
set_pwm() will always fail with -ENOSYS if pwm_ops set_invert() is
not implemented, leaving the backlight dark. Fix this by returning
no error if set_invert() is not implemented and no polarity change
is requested.

Fixes: 57e7775413 ("video: backlight: Parse PWM polarity cell")
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
2019-07-06 23:31:52 +02:00
Jean-Jacques Hiblot
3b83829ed6 usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic glue
dwc3-generic has been broken since MISC uclass has been modified to scan DT
sub-nodes after bind.
Fixing it by a using the no-op uclass.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-05 14:19:41 +02:00
Jean-Jacques Hiblot
07e33711fe dm: Add a No-op uclass
This uclass is intended for devices that do not need any features from the
uclass, including binding children.
This will typically be used by devices that are used to bind child devices
but do not use dm_scan_fdt_dev() to do it. That is for example the case of
several USB wrappers that have 2 child devices (1 for device and 1 for
host) but bind only one at a any given time.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-05 14:19:41 +02:00
Jean-Jacques Hiblot
e445d46651 usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback
There is simply no reason to do that here.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-05 14:19:40 +02:00
Marek Vasut
501547cec1 usb: ehci-mx6: Fix bus enumeration for DM case
The EHCI iMX6 driver is only partly converted to DT probing and
still uses a tremendous amount of hard-coded addresses. Worse,
the driver uses hard-coded SoC-model-specific base addresses, which
are derived from values protected by SoC-specific macros, hence the
driver is also compiled for a specific SoC model. Even worse, the
driver depends on specific sequential indexing of the controllers,
from which it derives offsets in the PHY and ANATOP register sets.

However, when the driver is probed from DT, the indexing is not
correct. In fact, each controller has index 0. This patch derives
the index for DT probing case from the controller base addresses,
which is not the way this should be done, however it is the least
intrusive approach, favorable this close to release.

The necessary steps to convert this driver fully to DT probing are
described inside the patch, however this should be done in the next
release and depends on iMX clock driver patches.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Ludwig Zenz <lzenz@dh-electronics.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
2019-07-05 14:19:40 +02:00
Kunihiko Hayashi
d5381853ad pinctrl: uniphier: Add SPI pin-mux settings
Add pin-mux settings for SPI controller.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-29 22:21:26 +09:00
Tom Rini
0352e878d2 Fixes for 2019.07
- menlo board
 - allow SDB on Sabre
 - HAB for mx6sl
 - apalis board
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Merge tag 'u-boot-imx-20190628' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2019.07

- menlo board
- allow SDB on Sabre
- HAB for mx6sl
- apalis board
2019-06-28 08:00:22 -04:00
Frieder Schrempf
2c72ead738 usb: gadget: f_sdp: Allow SPL to load and boot FIT via SDP
Add support for loading u-boot FIT images over the USB SDP protocol in
the SPL

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
[Various build fixes]
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
2019-06-27 13:50:28 +02:00
Yangbo Lu
5053da2e4a mmc: fsl_esdhc_imx: drop useless code
Dropped useless code for i.MX eSDHC driver.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-06-23 14:18:48 +08:00
Yangbo Lu
4d8ff42e46 mmc: fsl_esdhc: drop i.MX code
Dropped i.MX code which couldn't be reused.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
2019-06-23 14:18:42 +08:00
Yangbo Lu
fa33d20749 mmc: split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.

For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.

This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
2019-06-23 14:15:31 +08:00
Tom Rini
5eea874b5e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- boot failure fix for Intel edison
- tangier wdt conversion to driver model
2019-06-22 12:09:33 -04:00
Andy Shevchenko
c974a3d155 watchdog: tangier: Convert to use WDT class
Convert legacy driver to use watchdog class.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-22 22:27:13 +08:00
Andy Shevchenko
8b295a2026 watchdog: tangier: Replace unused constant with a comment
The default timeout value had been left in order to leave some traces
about default setup of watchdog done by firmware.

For better understanding and compiler burden, replace it with a comment.

Suggested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-22 22:26:22 +08:00
Bin Meng
5fafd7e35f pci: Avoid assigning PCI resources that are below 0x1000
commit b7598a43f2 ("[PATCH] Avoid assigning PCI resources from
zero address") only moved the bus lower address to 0x1000 if the
given bus start address is zero. The comment said 0x1000 is a
reasonable starting value, hence we'd better apply the same
adjustment when the given bus start address is below 0x1000.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-21 10:07:11 -04:00
Shannon Barber
2bc1821e86 Fix watchdog timeout setup for mt7623
Signed-off-by: Shannon Barber <sbarber@dataspeedinc.com>
2019-06-20 10:57:08 -04:00
Joel Stanley
894e235f14 aspeed/watchdog: Correct timeout value
The driver was using milliseconds and programming it into a register
which takes ticks of the watchdog clock, which runs at 1MHz. This meant
we were off by 1000 with the desired value.

When 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") was added the aspeed board would leave the watchdog running,
causing it to bite before u-boot was done.

Discovered by booting in qemu:

  $ qemu-system-arm -M ast2500-evb -drive file=test.img,format=raw,if=mtd -nographic -no-reboot -d cpu_reset

  U-Boot 2019.07-rc3-00091-g2253e40caef5 (Jun 06 2019 - 16:53:23 +0930)

  Model: Aspeed BMC
  DRAM:  496 MiB
  WDT:   Started with servicing (60s timeout)
  MMC:
  In:    serial@1e784000
  Out:   serial@1e784000
  Err:   serial@1e784000
  Watchdog timer expired.

Fixes: 06985289d4 ("watchdog: Implement generic watchdog_reset() version")
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-06-20 10:57:08 -04:00
Tom Rini
f643fb9f4c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- PCIe driver change to support DM model
- T2080QDS migrated to use PCIe DM model
2019-06-20 09:14:35 -04:00
Tom Rini
e8c185bb15 _ Update STM32MP entry in MAINTAINERS
_ Handle correctly binding for g-tx-fifo-size for USB DWC2 driver
 _ Fix trusted STM32MP1 defconfig with correct ethernet driver
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Merge tag 'u-boot-stm32-20190619' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Update STM32MP entry in MAINTAINERS
- Handle correctly binding for g-tx-fifo-size for USB DWC2 driver
- Fix trusted STM32MP1 defconfig with correct ethernet driver
2019-06-20 09:14:03 -04:00
Tom Rini
64fabed971 Merge tag 'mmc-6-19' of https://github.com/MrVan/u-boot
- Avoid HS400 mode when accessing boot partitions
2019-06-20 09:13:27 -04:00
Hou Zhiqiang
b89e3d9250 dm: pci: add Freescale PowerPC PCIe driver
Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20 10:44:45 +05:30
Tom Rini
63a4585791 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- LS1046AFRWY support
- USB errata fix and secure boot defconfig support for LS1028A
- Enabled SDHC and SATA for LX2160
- LS1046A serdes fixes
- other minor fixes
2019-06-19 14:01:11 -04:00
Patrick Delaunay
7c65468346 usb: dwc2: allow peripheral mode for OTG configuration
Allow device mode in DWC2 driver when device tree select the dr_mode
"peripheral" or "otg".

The device mode is not allowed when dr_mode = "host" in device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-06-19 16:56:11 +02:00
Patrick Delaunay
7350a75b51 usb: dwc2: correctly handle binding for g-tx-fifo-size
Manage g-tx-fifo-size as a array as specify in the binding.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-06-19 16:56:11 +02:00
Yangbo Lu
66fa035b55 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
u-boot is trying to make CONFIG_BLK as a hard requirement
for DM_MMC. But now it's still not.

config BLK
	bool "Support block devices"
	depends on DM
	default y if DM_MMC

When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC
without CONFIG_BLK enabled wasn't considered. This patch is to
fix probe issue without CONFIG_BLK enabled.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Marek Vasut
72119aa14a mmc: Avoid HS400 mode when accessing boot partitions
U-Boot code currently only applies this restriction to HS200 mode,
extend this to HS400 mode as well.

Currently U-Boot code not support accessing boot partition in HS200/400
mode. This needs more check.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-19 13:53:59 +08:00
Tom Rini
c3f43185ee Merge branch 'master' of git://git.denx.de/u-boot-spi
- Drop zipitz2 board (Tom)
- Add DEPRECATED option (Tom)
- Mark legacy or non-dm drivers as DEPRECATED (Jagan)
2019-06-17 11:32:22 -04:00
Tom Rini
c3e8aa1a9e Merge branch 'master' of git://git.denx.de/u-boot-usb
- Assorted gadget fixes
2019-06-17 11:27:21 -04:00
Igor Opaniuk
220f655176 fastboot: Check if partition really exist in getvar_has_slot()
Currently getvar_has_slot() invocation for "boot" and "system"
partitions always returns affirmative response regardless the fact of
existence of these partitions, which leads to impossibility to flash them
on old non-A/B AOSP setups, where _a/_b suffixes aren't used:

$ fastboot flash boot boot.img
Sending 'boot__a' (11301 KB)    OKAY [  0.451s]
Writing 'boot__a'               FAILED (remote: 'cannot find partition')
fastboot: error: Command failed

Although partition layout is:
-> part list mmc 0
Partition Map for MMC device 0  --   Partition Type: EFI

Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00000800	0x000107ff	"boot"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	ea2e2470-db4a-d646-b828-10167f736d63
  2	0x00010800	0x000127ff	"environment"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	10a819d2-6004-3d48-bd87-114e2a796db9
  3	0x00012800	0x0001a7ff	"recovery"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	guid:	9ea116e4-8a34-0c48-8cf5-2fe9480f56cd
  4	0x0001a800	0x0031a7ff	"system"
	attrs:	0x0000000000000000
......

This patch adds checks of existence for requested partitions
on eMMC/NAND.

Fixes: f73a7df984 ("net: fastboot: Merge AOSP UDP fastboot")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-06-14 12:39:54 +02:00
Sam Protsenko
f23a87d581 fastboot: getvar: Refactor fastboot_*_get_part_info() usage
Extract fastboot_*_get_part_info() usage for MMC and NAND into
getvar_get_part_info() function, as it will be needed further in other
functions. This way we can avoid code duplication and mess with
preprocessor directives across all points of usage.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-06-14 12:39:54 +02:00
Sam Protsenko
cacb03e490 fastboot: Use const qualifier for char *part_name
In fastboot_*_get_part_info() functions we can use stronger typing by
expecting const strings.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-06-14 12:39:54 +02:00
Sam Protsenko
97a0c6ff57 fastboot: Fix slot names reported by getvar
In commit [1] fastboot tool was changed w.r.t. new A/B specification [2],
and now we should report slot names in "a" format instead of "_a".
Latter is now considered legacy and we shouldn't rely on that anymore.

Due to this one can observe next error with recent fastboot tool:

    $ fastboot flash boot boot.img
    Sending 'boot__a' (11301 KB)
        OKAY [  0.451s]
    Writing 'boot__a'
        FAILED (remote: 'cannot find partition')
    fastboot: error: Command failed

Let's use new slot format in order to fix double underscores "__" and to
be in sync with AOSP master.

[1] 8091947847
[2] https://source.android.com/devices/tech/ota/ab/ab_implement#partitions

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-06-14 12:39:54 +02:00
Jagan Teki
ea73ec08d1 spi: Kconfig: Mark LPC32XX_SSP as DEPRECATED
Mark LPC32XX_SSP as DEPRECATED, this so the resulting build shows
warning for deprecated configuration enabled and associated code
will remove in v2019.07 release.

Cc: Albert ARIBAUD <albert.aribaud@3adev.fr>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Sylvain Lemieux <slemieux@tycoint.com>
[trini: Switch to DEPRECATED]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-06-13 12:51:06 +05:30
Jagan Teki
32f70d67c7 spi: Kconfig: Mark SOFT_SPI as DEPRECATED
Mark SOFT_SPI as DEPRECATED, this so the resulting build shows
warning for deprecated configuration enabled and associated code
will remove in v2019.07 release.

Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[trini: Switch to DEPRECATED]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-06-13 12:51:06 +05:30
Jagan Teki
e124759289 spi: Kconfig: Mark SH_SPI as DEPRECATED
Mark SH_SPI as DEPRECATED, this so the resulting build shows
warning for a deprecated configuration enabled and associated code
will remove in v2019.07 release.

Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[trini: Switch to DEPRECATED]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-06-13 12:51:06 +05:30
Jagan Teki
d5ded320a1 spi: Kconfig: Mark MXS_SPI has DEPRECATED
Mark MXS_SPI as DEPRECATED, this so the resulting build shows
warning for broken configuration enabled and associated code
will remove in v2019.07 release.

Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[trini: Switch to DEPRECATED]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-06-13 12:51:06 +05:30
Tom Rini
698bc1f2e9 - pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groups
- pinctrl: meson-gxbb: add hdmi related pins to fix HDMI on GXBB
 - pinctrl: meson: add support for getting pinmux status
 - pinctrl: meson-g12a: add support for drive-strength-microamp property
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Merge tag 'u-boot-amlogic-20190612' of git://git.denx.de/u-boot-amlogic

- pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groups
- pinctrl: meson-gxbb: add hdmi related pins to fix HDMI on GXBB
- pinctrl: meson: add support for getting pinmux status
- pinctrl: meson-g12a: add support for drive-strength-microamp property
2019-06-12 15:28:34 -04:00
Maxime Jourdan
63860dbfdf pinctrl: meson-gxbb: add hdmi related pins
The GXBB pinctrl is missing pins related to HDMI, namely hot plug
detection (hpd) and I2C (sda + scl).

This fixes HDMI support for GXBB in u-boot.

Reported-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12 11:50:02 +02:00
Guillaume La Roque
60fe59355c pinctrl: meson: g12a: add DS bank value
add drive-strength bank regiter and bit value for G12A SoC

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12 11:50:02 +02:00
Guillaume La Roque
478c563b40 pinctrl: meson: add support of drive-strength-microamp
drive-strength-microamp is a new feature needed for G12A SoC.
the default DS setting after boot is usually 500uA and it is not enough for
many functions. We need to be able to set the drive strength to reliably
enable things like MMC, I2C, etc ...

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12 11:50:02 +02:00
Neil Armstrong
b9308f2c05 pinctrl: meson-axg: add support for getting pinmux status
In order to support the "pinmux status" command, use the common functions
to get the pins count and names, and add the AXG specific function to get
the current function from registers.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12 11:50:02 +02:00
Neil Armstrong
2392289477 pinctrl: meson-gx: add support for getting pinmux status
In order to support the "pinmux status" command, use the common functions
to get the pins count and names, and add the GX specific function to get
the current function from registers.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Maxime Jourdan <mjourdan@baylibre.com>
2019-06-12 11:50:02 +02:00
Neil Armstrong
88fa32b849 pinctrl: meson: add common function to get pins name
In order to support the "pinmux status" command, add common function
to get pins count and pin name.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12 11:50:02 +02:00
Neil Armstrong
fb94245534 pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groups
The GPIO_TEST_N was in the wrong pmx group table, move it back with the AO
groups, GPIODV_18 was missing, add it back, and finally the GPIOCLK_*
group names were missing.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12 11:50:02 +02:00
Tom Rini
2702646bc0 - Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
 - Add STM32MP1 Avenger96 board support
 - Add SPI driver suport for STM32MP1
 - Add watchdog support for STM32MP1
 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
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Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot

- Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
2019-06-11 17:22:22 -04:00
Tom Rini
529faf80c3 u-boot-imx-20190612
--------------------
 
 - Board fixes:
 	- imx6logic
 	- wandboard
 	- mx6sabre boots again
 	- imx8qm_mek
 	- pico-* boards
 	- Toradex apalis / colibri
 	- engicam imx6 (environment)
 	- KP MX53
 	- opos6ul
 - Switch to DM:
 	- vining2000
 	- dh MX6
 	- Toradex colibri i.MX7
 	- Novena
 - Security : fix CSF size for HAB
 - Other:
       - imx: fix building for i.mx8 without spl
       - pcie and switch to DM
 
       mx6sabreauto: Enable SPL SDP support
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Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imx

u-boot-imx-20190612
--------------------

- Board fixes:
	- imx6logic
	- wandboard
	- mx6sabre boots again
	- imx8qm_mek
	- pico-* boards
	- Toradex apalis / colibri
	- engicam imx6 (environment)
	- KP MX53
	- opos6ul
- Switch to DM:
	- vining2000
	- dh MX6
	- Toradex colibri i.MX7
	- Novena
- Security : fix CSF size for HAB
- Other:
      - imx: fix building for i.mx8 without spl
      - pcie and switch to DM

      mx6sabreauto: Enable SPL SDP support
2019-06-11 13:41:24 -04:00
Lukasz Majewski
c0df121a97 pinctrl: imx: Define imx6_pinctrl_soc_info in .data section
This commit is necessary to be able to re-use the pinctrl code in early
SPL to properly configure pins.

The problem is that those "static" structures (without explicit
initialization) are placed in the SDRAM area, which corresponds to
u-boot proper (not even SPL).
Hence, when one wants to configure pins before relocation via DTS/DM,
the board hangs (imx6q SoC powered one) as only OCRAM area is available
(0x009xxxxx).

This commit prevents from this issue by moving the imx6_pinctrl_soc_info
structure to data section (from BSS).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-11 10:43:00 +02:00
Peng Fan
b5d97e10fa net: fec_mxc: not access reserved register on i.MX8
We should not access reserved register on i.MX8, otherwise met SERROR

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-06-11 10:43:00 +02:00
Marek Vasut
6757fa5756 serial: mxc: Add iMX6SX compatible string
Add compatible string for iMX6SX.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-06-11 10:42:48 +02:00
Marek Vasut
a11c0f44b7 pci: imx: Add DM and DT support
Add DM support and support for probing the iMX PCI driver from DT.
The legacy non-DM support is retained, however shall be removed once
DM PCI is the only option remaining.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marek Vasut
d2cc2e86f8 pci: imx: Pass driver private data around
Pass the driver private data around the driver as much as possible, instead
of having it as a static global variable. This is done in preparation for
the DM conversion, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marek Vasut
90f87fb525 pci: imx: Fix potential 64bit memory access clamping
The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marek Vasut
33f794be36 pci: imx: Factor out hard-coded register base addresses
Pull out hard-coded register base addresses into driver private
structure in preparation for DM conversion. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11 10:42:48 +02:00
Marcel Ziswiler
74c0f5cd7c imx8: fuse: fix fuse driver
This fixes the i.MX 8 fuse driver to actually build for i.MX 8QM as
well.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11 10:42:48 +02:00
Marcel Ziswiler
16f8b84917 clk: imx8qm: fix usdhc2 clocks
Trying to bring up uSDHC2 the following error message was observed:

MMC:   imx8_clk_set_rate(Invalid clk ID #60)
imx8_clk_set_rate(Invalid clk ID #60)
usdhc@5b030000 - probe failed: -22

This commit fixes this by properly setting resp. clocks.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11 10:42:48 +02:00
Heiko Schocher
7a3faf31a7 spi: imx: work with cs greater 0
currently spi mxc driver can only handle cs 0.
Allow it to handle also cs > 0.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-06-11 10:42:48 +02:00
Heiko Schocher
2b849e1f74 spi: imx: remove doubled pointer from mxc_spi_probe
in mxc_spi_probe() plat and mxcs pointer are created:

struct mxc_spi_slave *plat = bus->platdata;
struct mxc_spi_slave *mxcs = dev_get_platdata(bus);

which have the same value. Remove plat pointer.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-06-11 10:42:48 +02:00
Breno Matheus Lima
51f1357f34 Revert "drivers/crypto/fsl: assign job-rings to non-TrustZone"
Commit 22191ac353 ("drivers/crypto/fsl: assign job-rings to
 non-TrustZone") breaks HABv4 encrypted boot support in the
following i.MX devices:

- i.MX6UL
- i.MX7S
- i.MX7D
- i.MX7ULP

For preparing a HABv4 encrypted boot image it's necessary to
encapsulate the generated DEK in a blob. In devices listed
above the blob generation function takes into consideration
the Job Ring TrustZone ownership configuration (JROWN_NS)
and can be only decapsulated by the same configuration.

The ROM code expects DEK blobs encapsulated by the Secure World
environments which commonly have JROWN_NS = 0.

As U-Boot is running in Secure World we must have JROWN_NS = 0
so the blobs generated by dek_blob tool can be decapsulated
by the ROM code.

Job-rings assignment is now handled in OP-TEE OS, this commit can
be safely reverted.
https://github.com/OP-TEE/optee_os/pull/2986

This reverts commit 22191ac353.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2019-06-11 10:42:48 +02:00
Matti Vaittinen
1023c8739b regulator: bd71837: copy the bd71837 pmic driver from NXP imx u-boot
https://source.codeaurora.org/external/imx/uboot-imx

cherry picked, styled and merged commits:
- MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a
- MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-06-11 10:42:48 +02:00
Trent Piepho
d3eaf95ec6 power: pfuze100: Fix off by one error in voltage table handling
The code that sets a regulator by looking up the voltage in a table had
an off by one error.  vsel_mask is a bitmask, not the number of table
entries, so a vsel_mask value of 0x7 indicates there are 8, not 7,
entries in the table.

Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
2019-06-11 10:42:48 +02:00
Tom Rini
07798764c2 Merge branch 'master' of git://git.denx.de/u-boot-spi
- mpc8xxx spi driver fixes (Mario)
- mpc8xxx spi dm conversion (Mario, Jagan)
- SPI DM Migration update (Jagan)
2019-06-10 09:43:11 -04:00
Jagan Teki
c1a3f1ee18 spi: mpc8xxx: Convert to DM
Support DM in the MPC8xxx SPI driver, and remove the legacy SPI
interface.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:49 +05:30
Mario Six
67adbaef5a spi: mpc8xxx: Use get_timer
The comment before the transmission loop in conjunction with the
definition of SPI_TIMEOUT as 1000 implies that the loop is supposed to
have a timeout value of 1000 ms. But since there is no mdelay(1) or
similar in the loop body, the loop just runs 1000 times, without regard
for the time elapsed.

To correct this, use the standard get_timer functionality to properly
time out the loop after 1000 ms.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:49 +05:30
Mario Six
f6fcad5f2a spi: mpc8xxx: Fix if check
Decreasing the bit length and increasing the write data pointer should
be done when there are more than 32 bit of data, not 16 bit.

This did not produce incorrect behavior, because the only time where the
two checks produce different outcomes is the case of 16 < bitlen < 32,
and in this case the subsequent transmission is the last one regardless,
hence the additional bit length decrease and write data pointer increase
has no effect anyway.

Still, the correct check is the check for "bitlen > 32", so correct this
behavior.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:49 +05:30
Mario Six
a1c178e4c7 spi: mpc8xxx: Re-order transfer setup
Minize the time the adapter is disabled (via SPI_MODE_EN
clearing/setting) to just the character length setting, and only set up
the temporary data writing variable right before we need it, so there is
a more clear distinction between setting up the SPI adapter, and setting
up the data to be written.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:49 +05:30
Mario Six
85fa265530 spi: mpc8xxx: Document LEN setting better
Instead of having a table right before the code implementing the length
setting for documentation, have inline comments for the if branches
actually implementing the length setting described table's entries
(which is readable thanks to the set_char_len function).

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:49 +05:30
Mario Six
5ccfb8a995 spi: mpc8xxx: Rename variable
The variable "char_size" holds the number of bits to be transferred in
the current loop iteration. A better name would be "xfer_bitlen", which
we rename this variable to.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:49 +05:30
Mario Six
8dea61da19 spi: mpc8xxx: Make code more readable
Introduce the to_prescale_mod and set_char_len inline functions to make
the code more readable.

Note that the added "if (bitlen > 16)" check does not change the
semantics of the current code, and hence only preserves the current
error (this will be fixed in a later patch in the series).

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:48 +05:30
Mario Six
65f88e0408 spi: mpc8xxx: Reduce scope of loop variables
The transmission loop starts with setting some variables, which are only
used inside the loop. Reduce the scope to the loop to make the
declaration and initialization of these variables coincide.

In the case of char_size this also always initializes the variable
immediately with the final value actually used in the loop (instead of
the placeholder value 32).

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:48 +05:30
Mario Six
e4da4c2e0e spi: mpc8xxx: Simplify logic a bit
We do nothing in the loop if the "not empty" event was not detected. To
simplify the logic, check if this is the case, and skip the execution of
the loop early to reduce the nesting level and flag checking.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:48 +05:30
Mario Six
6409c6103a spi: mpc8xxx: Get rid of is_read
Get rid of the is_read variable, and just keep the state of the "not
empty" and "not full" events in two boolean variables within the loop
body.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:48 +05:30
Mario Six
76c82afef3 spi: mpc8xxx: Simplify if
Instead of having a nested if block, just have two branches within the
overarching if block to eliminate one nesting level.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-10 17:59:48 +05:30