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ram: rk3399: Rename sys_reg with sys_reg2

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Use dram config variable name as sys_reg2 instead of sys_reg
since the final variable value is to written into a pmugrf
register named as sys_reg2.

This reflect the both variable and associated register
names are same and also help to add next sys_reg's to
add it in future.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-16 17:27:00 +05:30 committed by Kever Yang
parent 879f9fed6a
commit e0ddb0ba21
1 changed files with 13 additions and 13 deletions
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26
drivers/ram/rockchip/sdram_rk3399.c
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@ -1073,11 +1073,11 @@ static void set_ddrconfig(const struct chan_info *chan,
static void dram_all_config(struct dram_info *dram,
const struct rk3399_sdram_params *params)
{
u32 sys_reg = 0;
u32 sys_reg2 = 0;
unsigned int channel, idx;
sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
for (channel = 0, idx = 0;
(idx < params->base.num_channels) && (channel < 2);
@ -1089,15 +1089,15 @@ static void dram_all_config(struct dram_info *dram,
if (params->ch[channel].cap_info.col == 0)
continue;
idx++;
sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &params->ch[channel].noc_timings;
@ -1118,7 +1118,7 @@ static void dram_all_config(struct dram_info *dram,
1 << 17);
}
writel(sys_reg, &dram->pmugrf->os_reg2);
writel(sys_reg2, &dram->pmugrf->os_reg2);
rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
params->base.stride << 10);