This enable the network function on the i.mx6q armadillo2
board(arm2), thus we can use tftp to load image from network.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
fsl_lbc: add printout of LCRR and LBCR to local bus regs
sbc8548: Fix up local bus init to be frequency aware
sbc8548: enable support for hardware SPD errata workaround
sbc8548: relocate fixed ddr init code to ddr.c file
sbc8548: Make enabling SPD RAM configuration work
sbc8548: Fix LBC SDRAM initialization settings
sbc8548: enable ability to boot from alternate flash
sbc8548: relocate 64MB user flash to sane boundary
Revert "SBC8548: fix address mask to allow 64M flash"
MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
eXMeritus HWW-1U-1A: Minor environment variable tweaks
* 'master' of git://git.denx.de/u-boot-ppc4xx:
board/mpl/pati: use the CFI driver for the PATI board
board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
board/mpl/pip405: use the CFI driver for the PIP405 board
board/mpl/common: remove the old legacy flash
ppc4xx: Setup HICB on Io64
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size). Set the values
by comparing to the register file for the board used during
JTAG init sequence:
LSDMR1 0x2863B727 /* PCHALL */
LSDMR2 0x0863B727 /* NORMAL */
LSDMR3 0x1863B727 /* MRW */
LSDMR4 0x4063B727 /* RFEN */
This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.
The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This reverts commit ccf1ad535a.
The commit "SBC8548: fix address mask to allow 64M flash"
essentially made this change:
* OR6:
- * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
But this makes no sense, as section 13.3.1.2.1 in the
MPC8548ERM v2 clearly indicates the masks:
1111_1111_1000_0000_0 8 Mbytes
1111_1100_0000_0000_0 64 Mbytes
1111_1000_0000_0000_0 128 Mbytes
So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device. The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:
FB80_0000 – FF7F_FFFF 32-bits 64MB FLASH SODIMM
FF80_0000 – FFFF_FFFF 8-bits 8MB FLASH
By extending the mapping of the 64MB flash to 128MB, it now
conflicts with the normal 8MB boot flash, causing issues.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This EEPROM is hardware-write-protected and used to persist key
information such as the serial number and MAC addresses even if the
primary environment sector in NOR FLASH is overwritten.
During manufacturing, the environment is initialized from Linux and then
the key parameters copied to the EEPROM via U-Boot:
env export -c -s 0x2000 $loadaddr serial# macaddr mac1addr mac2addr
eeprom write $loadaddr 0x0000 0x2000
The chip is then locked via hardware for delivery.
When doing a field U-Boot upgrade, the environment is erased and reset
to the defaults to avoid problems with "hwconfig" changes, etc. After
loading the new U-Boot image, the hardware data is reloaded:
i2c dev 0
eeprom read $loadaddr 0x0000 0x2000
env import -c $loadaddr 0x2000
saveenv
The first three commands are saved in the "restore_eeprom" variable for
user convenience. (EG: "run restore_eeprom && saveenv")
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Most of the ethernet connections are internal links with specialized
hardware and are not useful for "dhcp" or general-purpose networking;
U-Boot should not be cycling through them. Force the primary external
network interface in "ethprime" and disable the interface cycling with
"ethrotate=no".
Additionally, the environment variable "preboot" has its own config
option and means something entirely different from what the HWW-1U-1A
variable was intended for. Rename the board variable to "setbootargs"
to avoid potential confusion.
Finally, fix an incorrect address for the kernel in FLASH memory.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix a copy-and-paste error when adapting mpc8315erdb mtdparts
to mpc8313erdb. mtdids was already using the proper address
on mpc8313erdb.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This board is similar to our tuxx1 target. But on this board there
is only one application specific chip select configured.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
These boards are from a u-boot point of view identical. So collect
the two headerfiles to one, to decrease maintenance.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
CONFIG_SYS_LCRR is unused and CONFIG_SYS_LBC_LBCR is already
defined in the common header file, so remove them.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Measurements during HW basic test showed, that the SDRAM timing
has to be optimized. This patch adapted these timings accordingly.
Signed-off-by: Marco Schmid <marco.schmid@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This enables the XGMAC ethernet driver and networking related config
options.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Seaboard changes have removed the need for common/board.o in the
Makefile. Propagate this change to the other Tegra2 builds.
Signed-off-by: Tom Warren <twarren@nvidia.com>
We need to define CONFIG_ENV_IS_NOWHERE to avoid this error:
cmd_nvedit.c:69:3: error: #error Define one of CONFIG_ENV_IS_IN_...
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Medcom is a 16:9 15" terminal that is used for patient infotainment
in hospitals.
Changes in v3:
* Remove unused implementation of gpio_config_uart().
* Implement MMC/SD card detection.
* Drop board_mmc_getcd() which is now implemented by common Tegra2
code.
* Add MAINTAINERS entry.
Changes in v2:
* No longer override the default CONFIG_SYS_TEXT_BASE setting.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Plutux is a set-top box device based on the Tamonten processor
module. It can be connected to a display via an HDMI output.
Changes in v3:
* Remove unused implementation of gpio_config_uart().
* Implement MMC/SD card detection.
* Drop board_mmc_getcd() which is now implemented by common Tegra2
code.
* Add MAINTAINERS entry.
Changes in v2:
* No longer override the default CONFIG_SYS_TEXT_BASE setting.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
NVIDIA's flashing tools assume that the bootloader is loaded at address
0x00108000. Instead of requiring non-standard builds of those tools
which allow a load address of 0x00E08000, this commit just switches all
Tegra2 boards to use the standard load address.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This uses the SPI flash on Seaboard to store an 8KB environment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The twister board is a development board using
the TAM3517 SOM.
Support for NAND, 2 Ethernet (EMAC and SMC911),
USB (EHCI_OMAP).
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tapani Utrianen <tapani@technexion.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
The TAM3517 is a SOM module that can be used on custom boards.
The patch add a common configuration file that is included
by the boards using this module.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tapani Utrianen <tapani@technexion.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
* 'next' of ../next:
mkenvimage: Add version info switch (-V)
mkenvimage: Fix getopt() error handling
mkenvimage: Fix some typos
phy: add Micrel KS8721BL phy definition
net: introduce per device index
mvgbe: remove setting of ethaddr within the driver
x86: Add support for specifying an initrd with the zboot command
x86: Refactor the zboot innards so they can be reused with a vboot image
x86: Add infrastructure to extract an e820 table from the coreboot tables
x86: Add support for booting Linux using the 32 bit boot protocol
x86: Clean up the x86 zimage code in preparation to extend it
x86: Import code from coreboot's libpayload to parse the coreboot table
x86: Initial commit for running as a coreboot payload
CHECKPATCH: ./board/esd/hh405/logo_320_240_8bpp.c
CHECKPATCH: ./board/esd/hh405/logo_1024_768_8bpp.c
CHECKPATCH: ./board/esd/hh405/logo_320_240_4bpp.c
CHECKPATCH: ./board/esd/hh405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/apc405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/voh405/logo_320_240_4bpp.c
CHECKPATCH: ./board/esd/voh405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/hh405/fpgadata.c
CHECKPATCH: ./board/esd/pci405/fpgadata.c
CHECKPATCH: ./board/esd/tasreg/fpgadata.c
CHECKPATCH: ./board/esd/apc405/fpgadata.c
CHECKPATCH: ./board/esd/voh405/fpgadata.c
CHECKPATCH: ./board/esd/ash405/fpgadata.c
CHECKPATCH: ./board/esd/dasa_sim/fpgadata.c
CHECKPATCH: ./board/esd/ar405/fpgadata_xl30.c
CHECKPATCH: ./board/esd/ar405/fpgadata.c
CHECKPATCH: ./board/esd/plu405/fpgadata.c
CHECKPATCH: ./board/esd/wuh405/fpgadata.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405ab.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci4052.c
CHECKPATCH: ./board/esd/canbt/fpgadata.c
CHECKPATCH: ./board/esd/du405/fpgadata.c
CHECKPATCH: ./board/esd/cpciiser4/fpgadata.c
CHECKPATCH: ./board/dave/PPChameleonEVB/fpgadata.c
avr32:mmu.c: fix printf() length modifier
fat.c: fix printf() length modifier
cmd_sf.c: fix printf() length modifier
Make printf and vprintf safe from buffer overruns
vsprintf: Move function documentation into header file
Add safe vsnprintf and snprintf library functions
Move vsprintf functions into their own header
Conflicts:
tools/mkenvimage.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
MACH_TYPE_TNY_A9G20 and MACH_TYPE_TNY_A9260 were removed
from mach-types.h. Add them to the board config file.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
MACH_TYPE_SBC35_A9G20 was removed from mach-types.h.
Add it to the board config file.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Fix trailing white space, indentation by spaces instead of TABs,
excessive blank lines, trailing blank lines.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
This commit enables support for USB Gadgets on the Exynos4210 (C210 Universal)
reference target.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
CC: Remy Bohmer <linux@bohmer.net>
Switch to extension board detection using pci_find_device()
instead of detecting by i2c access to EEPROM device on
extension board.
This is a cleaner detection method since EEPROM addresses
can be different on different board revisions. This also
avoids "i2c_read: failed to address chip" error messages
in the boot log on boards without extension board which
may confuse users.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
This commit enables support for USB Gadgets on the GONI
reference target.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
* 'master' of git://git.denx.de/u-boot-arm:
M28: Cleanup memsize.o OOT build
i.MX28: Move SPL to arch/arm/cpu/arm926ejs/mx28
M28: Fix typo
M28: Document that units has to be set to sectors on SD bootcard
i.mx: i.mx6q: add the initial support for i.mx6q ARM2 board
i.mx: mxc_gpio: add the i.mx6q support
i.mx: add the initial support for freescale i.MX6Q processor
i.mx: introduce the armv7/imx-common folder
S5PC2XX: Rename S5pc2XX to exynos
tegra2: Don't use board pointer before it is set up
tegra2: Remove unneeded 'dynamic ram size' message
tegra2: Remove unused low-level Tegra2 UART code
tegra2: Remove unneeded config option
tegra2: Remove unneeded boot code
tegra2: Enable instruction cache
arm: Move CP15 init out of cpu_init_crit()
tegra2: Simplify tegra_start() boot path
tegra2: Add arch_cpu_init() to fire up Cortex-A9
tegra2: Use new GPIO APIs in gpio_config_uart()
tegra2: Add support for Ventana
tegra2: Modify MMC driver to handle power and cd GPIOs
tegra2: Move board_mmc_init into board files
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
Update pci_ids.h from current Linux sources
omap: overo: Use ubifs instead of jffs2 for nand
omap: TWL4030 Bump VMMC1 interface voltage from 3V to 3.15V
The current way memsize.c is built just made a symlink into the directory
with SPL and then compiled it like any other file there. This was bad as that
broke the out-of-tree build.
The new way introduced in this patch uses the standard spl/Makefile methods
(CONFIG_SPL_LIBCOMMON_SUPPORT / CONFIG_SPL_LIBGENERIC_SUPPORT) to let files in
common/ be built. Because common/Makefile says memsize.c is always built (SPL
and non-SPL build), this fixes our issue with memsize.c out-of-tree build.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This moves SPL to common location so it can be reused by multiple boards. Also,
this commit adjusts M28 SoM to avoid breakage due to the move.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.
There is two MMC slots on the boards:
mmc dev 0 -> connect USDHC3 -> the lower slot on the board,
mmc dev 1 -> connect USDHC4 -> the upper slot on the board,
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
CONFIG_ENABLE_CORTEXA9 and CONFIG_SKIP_RELOCATE_UBOOT are not needed,
so remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to move away from a special Tegra2 start-up, and just use
arch_cpu_init() instead. However, if we run board_init_f() from boot
we need to build it for ARMv4T, since the Tegra's AVP start-up CPU
does not support ARMv7.
The effect of this is to do the AVP init earlier, and in
arch_cpu_init(), rather that board_early_init_f().
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Ventana is a board which is very similar to Seaboard. Support it by
re-using board/nvidia/seaboard/seaboard.c with minor run-time conditionals.
v5: Makefile: Use cmd_link_o_target, remove unused clean/distclean targets.
v6: Make gpio_config_uart_seaboard() static.
v7: Add MAINTAINERS entry for Ventana. Tom Warren doesn't have Ventana, so
he asked me to add myself for this board.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones. Two independent P2020 computers may
be found inside each zone. Complete hardware support is included.
High-level hardware overview:
* DO-160 certified for passenger aircraft (noncritical)
* TEMPEST ceritified for RED/BLACK separation
* 3 zones per chassis, 2 computers per zone (total of 6)
* Dual-core 1.066GHz P2020 per computer
* One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
* Removable 80GB or 160GB Intel X18-M SSD per computer
* Front-accessible dual-port E1000E per computer
* Front-accessible serial console per computer
* Front-accessible USB port per computer
* Internal Gigabit crossover within each TEMPEST zone
* Internal unidirectional fiber links across TEMPEST zones
* Battery-backed DS1339 I2C RTC on each CPU.
Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.
Additional notes:
* SPD detection is only known to work with the DO-160-certified DIMMs
* CPU reset is a little quirky due to hardware misfeature. Proper
support for the hardware reset mechanism has been left for a later
patch series to address.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The BAB7xx boards are almost deceased. They cause build warnings, an
it's not worth the effort to fix these. Remove the dead body.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Frank Gottschling <fgottschling@eltec.de>
This moves CONFIG_SYS_TEXT_BASE one MB after beginning of SD-RAM. Move
CONFIG_SYS_SPL_MALLOC_START to have one MB of free space for the u-boot
image.
CONFIG_SYS_TEXT_BASE was in the middle of the bss-section. This was the
reason for the problems with MMC boot described here:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118711
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Tested-by: Thomas Weber <weber@corscience.de>
Signed-off-by: Tom Rini <trini@ti.com>
there are two boards based on da850 SOC - OMAP-L138 and AM18x.
In order to differentiate between these two boards, revision id
is passed to kernel via second byte of ATAG_REVISION.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Revision B of the board uses CSD0 for the DRAM,
as usual for MX3 boards. The patch fixes also
some values in the U-Boot environment.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The serial driver for iMX SOCs is continuosly changed if a
new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port>
defines were used only to find the base address for the selected UART.
Instead of that, move the base address to the board configuration
file and drop all #ifdef from driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Helmut Raiger <helmut.raiger@hale.at>
CC: John Rigby <jcrigby@gmail.com>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c. OMAP4
doesn't need i2c enabled in SPL. Enable SPL_BOARD_INIT on devkit8000.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
The only change of note is that we move from 0x80008000 to 0x80100000
for CONFIG_SYS_TEXT_BASE
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Tested-by: Koen Kooi <k-kooi@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
The only change of note is that we move from 0x80008000 to 0x80100000
for CONFIG_SYS_TEXT_BASE
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
Signed-off-by: Tom Rini <trini@ti.com>
This introduces 200MHz Micron parts timing information based on x-loader
to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init
logic is also based on what x-loader does in these cases. Note that
while previously u-boot would be flashed in with SW ECC in this case it
now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to
0x80100000.
Cc: Dirk Behme <dirk.behme@gmail.com>
Beagleboard rev C5, xM rev A:
Tested-by: Tom Rini <trini@ti.com>
Beagleboard xM rev C:
Tested-by: Matt Ranostay <mranostay@gmail.com>
Beagleboard rev B7, C2, xM rev B:
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
- booting from NOR Flash with direct boot method
- POST support
- LOGBUF support
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Christian Riesch <christian.riesch@omicron.at>
The boards in board/davinci/da8xxevm/ define pinmux_config[] vectors
that contain pinmux configurations for emac, uarts, memory controllers...
In an earlier patch such pinmux configurations were added to the arch
tree. This patch makes the hawkboard use these definitions instead of
defining its own.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
The boards in board/davinci/da8xxevm/ define pinmux_config[] vectors
that contain pinmux configurations for emac, uarts, memory controllers...
In an earlier patch such pinmux configurations were added to the arch
tree. This patch makes the da850evm use these definitions instead of
defining its own.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
The previous commit changed it to "zero two" instead of the proper "Oh two". This was completely broken!
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Acked-by: Tom Rini <trini@ti.com>
Fix:
arch/arm/cpu/arm926ejs/davinci/libdavinci.o: In function `timer_init':
/work/agust/git/u-boot/arch/arm/cpu/arm926ejs/davinci/timer.c:62:
undefined reference to `davinci_arm_clk_get'
drivers/i2c/libi2c.o: In function `i2c_init':
/work/agust/git/u-boot/drivers/i2c/davinci_i2c.c:102:
undefined reference to `davinci_arm_clk_get'
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
This patch removes the definition of stack sizes for
irq and fiq if the CONFIG_USE_IRQ is undefined before.
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Luca Ceresoli <luca.ceresoli@comelit.it>
This patch removes the unused definition of SDRC_R_C_B
from the config files.
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Acked-by: Tom Rini <trini@ti.com>
This patch removes the CONFIG_OMAP3430, because it is unused.
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Change the CONFIG_SYS_TEXT_BASE and the addresses of SDRAM
buffers used by SPL(heap and BSS) keeping in mind the
following requirements:
1. Make sure that SPL's heap and BSS doesn't come in the way
of Linux kernel, which is typically loaded at 0x80008000. This
will be important when SPL directly loads kernel.
2. Align the CONFIG_SYS_TEXT_BASE between TI internal
U-Boot and mainline U-Boot. This avoids a lot of confusion
and allows for the inter-operability of x-loader, SPL,
internal U-Boot, mainline U-Boot etc. The internal U-Boot's
address can not be changed to that of mainline U-Boot
as internal U-Boot doesn't have relocation and 0x80100000
used by mainline U-Boot will clash with kernel
3. Assume only a minimum amount of memory that may be available
on any practical OMAP4/5 board in future too. We are assuming
a minimum of 128 MB of memory
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
V2: Add missing u-boot-spl.lds, convert bitshifts to division,
convert to spl_onenand_load_image()
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Add support for the Ethernut 5 open hardware design, based
on Atmel's AT91SAM9XE512 SoC.
V4
- Fix several coding style issues.
- Move machine type to config file.
- Remove use of CONFIG_ATMEL_LEGACY.
Signed-off-by: Tim Schendekehl <tim.schendekehl@egnite.de>
This patch groups together all the common functions for LaCie boards:
Ethernet PHY and MAC address initializations.
Moreover the configurations for LaCie Kirkwood boards are merged into
a single file: include/configs/lacie_kw.h
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This patch adds support for the LaCie 2Big Network v2 board, based on
the Marvell Kirkwood 6281 SoC.
Additional information is available at:
http://lacie-nas.org/doku.php?id=2big_network_v2
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
I don't know what exactly the code was going for, but the object code
is the same before/after my change, and in looking at the env strings,
this seems to be OK.
Otherwise gcc warns:
cc1: warning: unknown escape sequence: '\$'
cc1: warning: unknown escape sequence: '\)'
cc1: warning: unknown escape sequence: '\040'
cc1: warning: unknown escape sequence: '\$'
cc1: warning: unknown escape sequence: '\)'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The ecovec board has SH7724, 256MB DDR2-SDRAM, USB,
Ethernet, and more.
This patch supports the following functions:
- 256MB DDR2-SDRAM
- USB
- I2C
- Ethernet
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The new sh_eth driver uses the phy driver. So, this patch enables it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The new sh_eth driver uses the phy driver. So, this patch enables it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
When DDR-ECC is effective, the physical memory which can be used
reduces this boardby half. However, this mode can chenge to disable.
When it was disabled, user can use 512 MB of physical memory.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: "Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>
Acked-by: "Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The new sh_eth driver uses the phy driver. So, this patch enables it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
mpc85xx: support for Freescale COM Express P2020
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
mpc85xx: support board-specific reset function
powerpc/85xx: verify the localbus device tree address before booting the OS
mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
powerpc/p3060qds: Add board related support for P3060QDS platform
powerpc/85xx: clean up and document the QE/FMAN microcode macros
powerpc/85xx: always implement the work-around for Erratum SATA_A001
powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
powerpc/85xx: Add workaround for erratum A-003474
powerpc/85xx: fixup flexcan device tree clock-frequency
powerpc/85xx: Add workaround for erratum CPU-A003999
This patch switches PMC440 board code to the CONFIG_PCI_BOOTDELAY option
instead of using a private implemention. This relies on Anatolji's patch
that moves the pcidelay handling behind pci_target_init.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.
Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.
This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P3060QDS is a Freescale reference board for the six-core P3060 SOC.
P3060QDS Board Overview:
Memory subsystem:
- 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
- 128M Bytes NOR flash single-chip memory
- 16M Bytes SPI flash
- 8K Bytes AT24C64 I2C EEPROM for RCW
Ethernet:
- Eight Ethernet controllers (4x1G + 4x1G/2.5G)
- Three VSC8641 PHYs on board (2xRGMII + 1xMII)
- Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
PCIe: Two PCI Express 2.0 controllers/ports
USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
I2C: Four I2C controllers
UART: Supports two dUARTs up to 115200 bps for console
RapidIO: Two RapidIO, sRIO1 and sRIO2
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman. Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both. A given SOC will only have
a QE or an Fman, so this is safe.
Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND. There's no way to know by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020. It was already defined for the
P1010 and P1014.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch fixes the build breakage for the davinci_sonata board.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sergey Kubushyn <ksi@koi8.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
This patch fixes the build breakage for the davinci_schmoogie board.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sergey Kubushyn <ksi@koi8.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
MACH_TYPE_FARADAY was dropped from mach-types.h. Add it back to
board config file.
Signed-off-by: Yan-Pai Chen <ypchen@faraday-tech.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Change my old email address which is no longer valid.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
As a result of the commit 6833260 the uart16550 driver
is broken for Microblaze big endian systems, because of
the missing 3 byte offset. Other than as described, not
all U-Boot BSP will treat properly the 3 byte offset.
This why prefer to mask out the 3 byte offset in general
and setup correct _REG_SIZE value depending on edianess.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Tested-by: Michal Simek <monstr@monstr.eu>
* 'master' of git://git.denx.de/u-boot-nios:
nios2: Offer ft_board_setup() capability and call fdt_fixup_ethernet().
board/nios2-generic: Use altera_pio driver and remove board specific driver
gpio: Add driver for Altera's PIO core
nios2: Pseudo implement dcache_status/enable/disable()
* 'master' of git://git.denx.de/u-boot-arm:
arm, davinci: add DAVINCI_MMC_CLKID
arm, davinci_emac: fix driver bug if more then 3 PHYs are detected
arm, davinci: da850/dm365 lowlevel cleanup
omap5: Add omap5_evm board build support.
omap4/5: Add support for booting with CH.
omap5: emif: Add emif/ddr configurations required for omap5 evm
omap5: clocks: Add clocks support for omap5 platform.
omap5: Add minimal support for omap5430.
omap: Checkpatch fixes
omap4: make omap4 code common for future reuse
GCC4.6: Squash warnings in onenand_base.c
GCC4.6: Fix common/usb.c on xscale
OneNAND: Add simple OneNAND SPL
PXA: vpac270: Enable the new generic MMC driver
PXA: Cleanup serial_pxa
PXA: Drop csb226 and innokom boards (unmaintained)
m28evk: Fix comment about the number of RAM banks
mx31: Fix checkpatch warnings in generic.c
mx31: Use proper IO accessor for GPR register
mx31: Remove duplicate definition for GPR register
qong: Use generic function for configuring GPR register
M28EVK: Enable USB HOST support
iMX28: Add USB HOST driver
iMX28: Add USB and USB PHY register definitions
M28: Add memory detection into SPL
iMX28: Fix ARM vector handling
M28: Add doc/README.m28 documentation
M28: Add MMC SPL
iMX28: Add support for DENX M28EVK board
iMX28: Add u-boot.sb target to Makefile
iMX28: Add image header generator tool
iMX28: Add driver for internal RTC
iMX28: Add GPMI NAND driver
iMX28: Add APBH DMA driver
iMX28: Add SPI driver
iMX28: Add GPIO control
iMX28: Add I2C bus driver
iMX28: Add PINMUX control
FEC: Add support for iMX28 quirks
iMX28: Add SSP MMC driver
iMX28: Initial support for iMX28 CPU
MX25: zmx25: GCC4.6 fix build warnings
da850: add new config file for AM18xx
BeagleBoard: config: Switch to ttyO2
OMAP3: Change omap3_evm maintainer
devkit8000: Fix NAND SPL on boards with 256MB NAND
integrator: enable Vpp and disable flash protection
integrator: add system controller header
integrator: make flash writeable on boot
integrator: use io-accessors for board init
integrator: move text offset to config
integrator: pass configs for core modules
ARM: remove superfluous setting of arch_number in board specific code.
SPL: Allow ARM926EJS to avoid compiling in the CPU support code
integrator: do not test first part of the memory
arm: a320: fix broken timer
ARM: define CONFIG_MACH_TYPE for all ronetix boards
dm646x: pass board revision info to kernel
dm646x: add new configuration for dm6467T
arm, davinci: Fix setting of the SDRAM configuration register
arm, davinci: Remove the duplication of LPSC functions
arm, davinci: Rename AM1808 lowlevel functions to DA850
da8xxevm: fix build error
ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
This patch adds the build support for the
omap5_evm board.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.
Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
In order to support 1920x01080 resolution, we must increase the alloc
length.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Anatolij Gustschin <agust@denx.de>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
m28evk has one bank of RAM.
Fix the comment.
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
This enables the second port, aka. the port with the USB connector on the
M28EVK.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
This code allows the DDR DRAM size to be detected at runtime. The RAM size is
stored into two scratch registers, from which it is then fetched in U-Boot.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
This patch introduces proper ARM vector handling for i.MX28 CPU. This issue
wasn't addressed because the interrupts weren't enabled on any ARMv5 core,
therefore the issue wasn't noticed earlier.
In previous implementation, the vectoring code used by i.MX28 CPU when an
exception happened was that of the SPL. With this change, the branch target when
an exception happens can be reconfigured by U-Boot.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
This patch adds SPL code for the M28 board.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
This contains support for the following components:
- DUART
- MMC
- Both FEC interfaces
- NAND
- I2C (RTC, EEPROM)
- SPI (FLASH)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
add new configuration file da850_am18xxevm.h for AM18xx boards
which are based on da850 SOC. AM18xx has WINBOND spi flash which
is indicated in the config file. And make appropriate changes in
board.cfg for building.
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This is needed to support the latest kernel versions.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The devkit8000 ships with either a 128MB or 256MB NAND chip. In
order for SPL to work with 256MB NAND CONFIG_SYS_NAND_5_ADDR_CYCLE
needs to be set. After talking with Scott Wood this should be
safe to set even for smaller NAND chips.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Do away with the config.mk file and move the text offset to the
config files to make things easier.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We cause CCSRBAR to be relocated in the SPL phase of NAND boot which
isn't expected and breaks things. Fixing the board config.h to NOT
relocate CCSR during the CONFIG_NAND_SPL phase.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add board_eth_init(). PCIe network card is also supported.
Put RGMII init after tsec_eth_init().
Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.
Signed-off-by: Ebony Zhu
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
add a function in board file to pass board revision
info to kernel. Revision number 0 and 1 are passed in
case of DM6467 and DM6467T respectively.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
add new configuration file for dm6467T and appropraite changes
in boards.cfg. dm6467T is the new varaiant of dm6467 SOC which
supports 33 MHz reference clock where as dm6467 supports 27 MHz
reference clock.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The new MPC8360EMDS board changes the oscillator to 33.33MHz
in order to support QE 500MHz since 2008.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 'master' of git://git.denx.de/u-boot-arm:
Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
arm: jadecpu: Readd MACH_TYPE_JADECPU
at91: defined mach-types for otc570 board in board config file
at91: defined mach-types for meesc board in board config file
mx31pdk: Enable D and I caches
ehci-mxc: remove incorrect comment
README: Fix supported i.MX SoC list for CONFIG_MXC_SPI
mx53: Turn off child clocks before reconfigure perclk_root
qong: enable support for compressed images
imx: imx31_phycore.h: fix checkpatch warnings
vision2: Remove unused get_board_rev function
mx53smd: Remove unused get_board_rev function
mx53ard: Remove unused get_board_rev function
mx53evk: Remove unused get_board_rev function
mx53evk: Add RTC support
mx53loco: Remove unused get_board_rev function
mx53evk: Remove unneeded '1' from mx53evk.h
OMAP3: mvblx: Initial support for mvBlueLYNX-X
ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE
omap3: mem: Move comments next to definitions
omap3: mem: Clean-up whitespaces
omap3: mem: Define and use common macros
Davinci: ea20: added PREBOOT to configuration
Davinci: ea20: added I2C support
Davinci: ea20: added video support
VIDEO: davinci: add framebuffer to da8xx
ARM: Davinci: added missing registers to hardware.h
Davinci: ea20: add gpios for LCD backlight control
Davinci: ea20: add gpio for keeping power on in board_late_init
Davinci: ea20: Add default U-Boot environment
Davinci: ea20: Add early init to get early output from console
Davinci: ea20: Add NAND support
Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
Davinci: ea20: set console on UART0
arm, davinci: add cam_enc_4xx support
arm926ejs, davinci: add missing spi defines for dm365
arm926ejs, davinci: add cpuinfo for dm365
arm, davinci: add lowlevel function for dm365 soc
arm, davinci: add header files for dm365
spl, nand: add 4bit HW ecc oob first nand_read_page function
arm, davinci: add support for new spl framework
spl: add option for adding post memory test to the SPL framework
net, davinci_emac: make clock divider in MDIO control register configurable
arm, usb, davinci: make USBPHY_CTL register configurable
usb, davinci: add enable_vbus() weak function
omap3evm: fix errors caused by multiple definitions
omap3evm: Add (quick) configuration for NAND only
omap3evm: Add (quick) configuration for MMC/SD only
omap3evm: move common config options to new file
omap3evm: Prepare to split configuration
omap3evm: Reorder related config options
omap/spl: actually enable the console
davinci_emac: compilation fix, phy is array now
omap3evm: Set environment variable 'ethaddr'
arm, arm926: fix missing symbols in NAND_SPL mode
arm, davinci: Add function lpsc_syncreset()
arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
arm/km: portl2 environment address update to P1B
arm/km: adapt bootcounter evaluation
arm/km: enable jffs2 cmds
arm/km: trigger reconfiguration for the Xilinx FPGA
arm/km: add boardid and hwkey to kernel command line
ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards
netspace_v2: enable I2C EEPROM support
netspace_v2: fix SDRAM configuration
armada100: define CONFIG_SYS_CACHELINE_SIZE
pantheon: define CONFIG_SYS_CACHELINE_SIZE
kirkwood: define CONFIG_SYS_CACHELINE_SIZE
kirkwood: drop empty asm-offsets.s file
arm/km/mgcoge3un: enhance "waitforne" feature
arm/km: add variable waitforne to mgcoge3un
gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
ARM: dreamplug: fix compilation
ARM: DockStar: fix compilation
ARM: netspace_v2: fix warnings
am335x: Drop board_sysinfo struct
am335x: Temporarily add MACH_TYPE define
misc:pmic:samsung Enable PMIC driver at C210 Universal target
dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target
dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target
smdkv310: use macro for mmc data read function address
smdkv310: use spl framework for mmc spl
SMDKV310: use get_ram_size() to validate dram size
SMDKV310: Initialize board id using CONFIG_MACH_TYPE
ORIGEN : use absolute paths and fix tool naming
ORIGEN : enable device tree support
MX25: tx25: Fix building due to missing MACH_TYPE
mx31: Add board support for HALE TT-01
mx31: add ESD control registers
mx31: define pins and init for UART2 and CSPI3
MX35: add support for flea3 board
MX51: vision2: add MACH_TYPE in config file
vision2: Remove unused header file
mx51evk: Remove unused get_board_rev function
mx51evk: Remove unneeded '1' from mx51evk.h
I2C: Fix mxc_i2c.c problem on imx31_phycore
mx35pdk: Add RTC support
mx51evk: Use GPIO API for configuring the IOMUX
mx51evk: Add RTC support
rtc: Make mc13783-rtc driver generic
qong: remove unneeded IOMUX settings
qong: Use mx31_set_gpr to setup USBH2 pins
mx31: Introduce mx31_set_gpr function
mx31pdk: Add MC13783 PMIC support
qong: remove unneeded "1" from qong.h
misc: pmic: fix regression in pmic_fsl.c (SPI)
mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME
MX35: Drop unnecessary prototypes from imx-regs.h
I2C: added I2C-2 and I2C-3 to MX35
MX35: factorize common assembly code
MX35: add reset cause as provided by other i.MX
MX35: add pins definition for UART3
MX35: added ESDC structure to imx-regs
* 'master' of git://git.denx.de/u-boot-coldfire:
ColdFire: The EB+MCF-EV123 boards config update
ColdFire: Fix the compile issue for M52277
ColdFire:Moving the remaining coldfire boards to boards.cfg
This also fixes a build warning:
main.c: In function 'main_loop':
main.c:311:16: warning: variable 'bootlimit' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
After commit 327474f854, the
M52277EVB_stmicro configuration fail to build. Fix it by moving
the env outside the flash and update the lds file.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
quotation from Albert ARIBAUD:
"Recently the ARM mach-types.h file has been brought in sync with its
Linux original, leasing to a number of boards not being listed any more,
as the new list only contains boards which have actual Linux support or
were declared less than one year ago.
The symptom is a build failure with a message of the form "error:
'MACH_TYPE_XXXXXX' undeclared (first use in this function)".
U-Boot maintainers of such boards (in Cc: of this mail) should provide a
patch to re-introduce the MACH_TYPE_XXXXXX definition in their boards'
config header file in include/configs/."
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
quotation from Albert ARIBAUD:
"Recently the ARM mach-types.h file has been brought in sync with its
Linux original, leasing to a number of boards not being listed any more,
as the new list only contains boards which have actual Linux support or
were declared less than one year ago.
The symptom is a build failure with a message of the form "error:
'MACH_TYPE_XXXXXX' undeclared (first use in this function)".
U-Boot maintainers of such boards (in Cc: of this mail) should provide a
patch to re-introduce the MACH_TYPE_XXXXXX definition in their boards'
config header file in include/configs/."
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
- enable support for unzip command
- enable support for compressed bitmap images
We also have to increase the malloc() arena a bit for this.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
No board information is passed for MX53EVK, so remove get_board_rev function.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
No board information is passed for MX53LOCO, so remove get_board_rev function.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Remove unneeded '1' from mx53evk.h.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
MACH_TYPE_OMAP3_CPS was dropped in the latest mach-types sync (47af6f61bc)
because it is not mainlined in Linux.
Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The new MPC8360EMDS board supports 512MB DDR since 2008.
For 512MB DDR:
BAT0 is used for the first 256MB memory, BAT4 is used for the second
256MB memory and the address space of SDRAM follows the DDR, so if the
size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of
DDR is 512MB, the BAT4 will be used for the second 256MB memory and
there is no BAT for SDRAM.
Therefore, if the size of DDR is 512MB, this patch will use BAT6 for
SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the
codes relocates to the DDR.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Kim Phillips <kim.phillips@freescale.com>
Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
Cleanup the setting of the csnbds to respect the setting of
CONFIG_SYS_DDR_SDRAM_BASE
Use __ilog2 instead of writing the code to compute it
Disable unused CS configs
Ensure ddrlaw.bar is configured
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
PREBOOT is used on the ea20 to load a splash image
at the start up.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The pin called HALTEN drives a transistor to operate the supply
voltage. After HALTEN is high, the user can release the power
switch button and the device will stay powered on.
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
CC: sbabic@denx.de
CC: dzu@denx.de
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
