mirror of
https://github.com/AsahiLinux/u-boot
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MPC7xx: remove obsolete "BAB7xx" board
The BAB7xx boards are almost deceased. They cause build warnings, an it's not worth the effort to fix these. Remove the dead body. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Frank Gottschling <fgottschling@eltec.de>
This commit is contained in:
parent
01baa05643
commit
c53043b7f1
16 changed files with 4 additions and 4276 deletions
4
CREDITS
4
CREDITS
|
@ -161,7 +161,7 @@ D: Support for WRS SBC8347/8349 boards
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N: Frank Gottschling
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E: fgottschling@eltec.de
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D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM
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D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM
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W: www.eltec.de
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N: Marius Groeger
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@ -183,7 +183,7 @@ D: Port to Walnut405 board
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N: Andreas Heppel
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E: aheppel@sysgo.de
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D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
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D: CPU Support for MPC 75x
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N: Josh Huber
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E: huber@alum.wpi.edu
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@ -214,8 +214,6 @@ Frank Gottschling <fgottschling@eltec.de>
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MHPC MPC8xx
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BAB7xx MPC740/MPC750
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Wolfgang Grandegger <wg@denx.de>
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ipek01 MPC5200
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2
README
2
README
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@ -564,7 +564,7 @@ The following options need to be configured:
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CONFIG_CFB_CONSOLE
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Enables console device for a color framebuffer. Needs following
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defines (cf. smiLynxEM, i8042, board/eltec/bab7xx)
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defines (cf. smiLynxEM, i8042)
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VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
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(default big endian)
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VIDEO_HW_RECTFILL graphic chip supports
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@ -1,46 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
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SOBJS = asm_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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File diff suppressed because it is too large
Load diff
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@ -1,253 +0,0 @@
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/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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* (C) Copyright 2001 ELTEC Elektronik AG
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* Frank Gottschling <fgottschling@eltec.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <mpc106.h>
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#include <mk48t59.h>
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#include <74xx_7xx.h>
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#include <ns87308.h>
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#include <video_fb.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*---------------------------------------------------------------------------*/
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/*
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* Get Bus clock frequency
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*/
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ulong bab7xx_get_bus_freq (void)
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{
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/*
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* The GPIO Port 1 on BAB7xx reflects the bus speed.
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*/
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volatile struct GPIO *gpio =
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(struct GPIO *) (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_GPIO_BASE);
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unsigned char data = gpio->dta1;
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if (data & 0x02)
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return 66666666;
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return 83333333;
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz)
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*/
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ulong bab7xx_get_gclk_freq (void)
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{
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static const int pllratio_to_factor[] = {
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00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
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00,
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};
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return pllratio_to_factor[get_hid1 () >> 28] *
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(bab7xx_get_bus_freq () / 10);
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}
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/*----------------------------------------------------------------------------*/
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int checkcpu (void)
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{
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uint pvr = get_pvr ();
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printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
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printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
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bab7xx_get_bus_freq () / 1000000);
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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int checkboard (void)
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{
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#ifdef CONFIG_SYS_ADDRESS_MAP_A
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puts ("Board: ELTEC BAB7xx PReP\n");
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#else
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puts ("Board: ELTEC BAB7xx CHRP\n");
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#endif
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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int checkflash (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("2 MB ## Test not implemented yet ##\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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static unsigned int mpc106_read_cfg_dword (unsigned int reg)
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{
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unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
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out32r (MPC106_REG_ADDR, reg_addr);
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return (in32r (MPC106_REG_DATA | (reg & 0x3)));
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}
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/* ------------------------------------------------------------------------- */
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long int dram_size (int board_type)
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{
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/* No actual initialisation to do - done when setting up
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* PICRs MCCRs ME/SARs etc in ram_init.S.
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*/
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register unsigned long i, msar1, mear1, memSize;
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#if defined(CONFIG_SYS_MEMTEST)
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register unsigned long reg;
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printf ("Testing DRAM\n");
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/* write each mem addr with it's address */
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for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
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*reg = reg;
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for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
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if (*reg != reg)
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return -1;
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}
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#endif
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/*
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* Since MPC106 memory controller chip has already been set to
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* control all memory, just read and interpret its memory boundery register.
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*/
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memSize = 0;
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msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
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mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
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i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
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do {
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if (i & 0x01) /* is bank enabled ? */
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memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
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msar1 >>= 8;
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mear1 >>= 8;
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i >>= 1;
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} while (i);
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return (memSize * 0x100000);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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return dram_size (board_type);
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}
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/* ------------------------------------------------------------------------- */
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void after_reloc (ulong dest_addr)
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{
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/*
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* Jump to the main U-Boot board init code
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*/
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board_init_r ((gd_t *) gd, dest_addr);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* do_reset is done here because in this case it is board specific, since the
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* 7xx CPUs can only be reset by external HW (the RTC in this case).
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*/
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#if defined(CONFIG_RTC_MK48T59)
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/* trigger watchdog immediately */
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rtc_set_watchdog (1, RTC_WD_RB_16TH);
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#else
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#error "You must define the macro CONFIG_RTC_MK48T59."
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_WATCHDOG)
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/*
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* Since the 7xx CPUs don't have an internal watchdog, this function is
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* board specific. We use the RTC here.
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*/
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void watchdog_reset (void)
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{
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#if defined(CONFIG_RTC_MK48T59)
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/* we use a 32 sec watchdog timer */
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rtc_set_watchdog (8, RTC_WD_RB_4);
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#else
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#error "You must define the macro CONFIG_RTC_MK48T59."
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#endif
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}
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#endif /* CONFIG_WATCHDOG */
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_CONSOLE_EXTRA_INFO
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extern GraphicDevice smi;
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void video_get_info_str (int line_number, char *info)
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{
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/* init video info strings for graphic console */
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switch (line_number) {
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case 1:
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sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
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(get_pvr () >> 8) & 0xFF,
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get_pvr () & 0xFF,
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bab7xx_get_gclk_freq () / 1000000,
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bab7xx_get_bus_freq () / 1000000);
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return;
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case 2:
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sprintf (info,
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" ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
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dram_size (0) / 0x100000, flash_init () / 0x100000);
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return;
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case 3:
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sprintf (info, " %s", smi.modeIdent);
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return;
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}
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/* no more info lines */
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*info = 0;
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return;
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}
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#endif
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/*---------------------------------------------------------------------------*/
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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@ -1,291 +0,0 @@
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/*
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* (C) Copyright 2002 ELTEC Elektronik AG
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* Frank Gottschling <fgottschling@eltec.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* SRom I/O routines.
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*/
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#include <common.h>
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#include <pci.h>
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#include "srom.h"
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#define SROM_RD 0x00004000 /* Read from Boot ROM */
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#define SROM_WR 0x00002000 /* Write to Boot ROM */
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#define SROM_SR 0x00000800 /* Select Serial ROM when set */
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#define DT_IN 0x00000004 /* Serial Data In */
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#define DT_CLK 0x00000002 /* Serial ROM Clock */
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#define DT_CS 0x00000001 /* Serial ROM Chip Select */
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static u_int dc_srom_iobase;
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/*----------------------------------------------------------------------------*/
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static int inl(u_long addr)
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{
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return le32_to_cpu(*(volatile u_long *)(addr));
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}
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/*----------------------------------------------------------------------------*/
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static void outl (int command, u_long addr)
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{
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*(volatile u_long *)(addr) = cpu_to_le32(command);
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}
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/*----------------------------------------------------------------------------*/
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static void sendto_srom(u_int command, u_long addr)
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{
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outl(command, addr);
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udelay(1);
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return;
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}
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/*----------------------------------------------------------------------------*/
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static int getfrom_srom(u_long addr)
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{
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s32 tmp;
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tmp = inl(addr);
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udelay(1);
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return tmp;
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}
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/*----------------------------------------------------------------------------*/
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static void srom_latch (u_int command, u_long addr)
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{
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sendto_srom (command, addr);
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sendto_srom (command | DT_CLK, addr);
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sendto_srom (command, addr);
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return;
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}
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/*----------------------------------------------------------------------------*/
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static void srom_command_rd (u_int command, u_long addr)
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{
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srom_latch (command, addr);
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srom_latch (command, addr);
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srom_latch ((command & 0x0000ff00) | DT_CS, addr);
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return;
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}
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/*----------------------------------------------------------------------------*/
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static void srom_command_wr (u_int command, u_long addr)
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{
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srom_latch (command, addr);
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srom_latch ((command & 0x0000ff00) | DT_CS, addr);
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srom_latch (command, addr);
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return;
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}
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/*----------------------------------------------------------------------------*/
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static void srom_address(u_int command, u_long addr, u_char offset)
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{
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int i;
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signed char a;
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a = (char)(offset << 2);
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for (i=0; i<6; i++, a <<= 1)
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{
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srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
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}
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udelay(1);
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i = (getfrom_srom(addr) >> 3) & 0x01;
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return;
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}
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/*----------------------------------------------------------------------------*/
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static short srom_data_rd (u_int command, u_long addr)
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{
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int i;
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short word = 0;
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s32 tmp;
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for (i=0; i<16; i++)
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{
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sendto_srom(command | DT_CLK, addr);
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tmp = getfrom_srom(addr);
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sendto_srom(command, addr);
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word = (word << 1) | ((tmp >> 3) & 0x01);
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}
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sendto_srom(command & 0x0000ff00, addr);
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return word;
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}
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/*----------------------------------------------------------------------------*/
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static int srom_data_wr (u_int command, u_long addr, short val)
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{
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int i;
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u_long longVal;
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s32 tmp;
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longVal = (u_long)(le16_to_cpu(val));
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for (i=0; i<16; i++)
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{
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tmp = (longVal & 0x8000)>>13;
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sendto_srom (tmp | command, addr);
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sendto_srom (tmp | command | DT_CLK, addr);
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sendto_srom (tmp | command, addr);
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longVal = longVal<<1;
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}
|
||||
|
||||
sendto_srom(command & 0x0000ff00, addr);
|
||||
sendto_srom(command, addr);
|
||||
|
||||
tmp = 100;
|
||||
do
|
||||
{
|
||||
if ((getfrom_srom(dc_srom_iobase) & 0x8) == 0x8)
|
||||
break;
|
||||
udelay(1000);
|
||||
} while (--tmp);
|
||||
|
||||
if (tmp == 0)
|
||||
{
|
||||
printf("Write DEC21143 SRom timed out !\n");
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
static short srom_rd (u_long addr, u_char offset)
|
||||
{
|
||||
sendto_srom (SROM_RD | SROM_SR, addr);
|
||||
srom_latch (SROM_RD | SROM_SR | DT_CS, addr);
|
||||
|
||||
srom_command_rd (SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
|
||||
|
||||
srom_address (SROM_RD | SROM_SR | DT_CS, addr, offset);
|
||||
|
||||
return srom_data_rd (SROM_RD | SROM_SR | DT_CS, addr);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static void srom_wr_enable (u_long addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
sendto_srom (SROM_WR | SROM_SR, addr);
|
||||
srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
|
||||
|
||||
srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
|
||||
srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
|
||||
srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
|
||||
|
||||
for (i=0; i<6; i++)
|
||||
{
|
||||
srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static int srom_wr (u_long addr, u_char offset, short val)
|
||||
{
|
||||
srom_wr_enable (addr);
|
||||
|
||||
sendto_srom (SROM_WR | SROM_SR, addr);
|
||||
srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
|
||||
|
||||
srom_command_wr (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
|
||||
|
||||
srom_address (SROM_WR | SROM_SR | DT_CS, addr, offset);
|
||||
|
||||
return srom_data_wr (SROM_WR | SROM_SR | DT_CS, addr, val);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* load data from the srom
|
||||
*/
|
||||
int dc_srom_load (u_short *dest)
|
||||
{
|
||||
int offset;
|
||||
short tmp;
|
||||
|
||||
/* get srom iobase from local network controller */
|
||||
pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
|
||||
dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
dc_srom_iobase = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
|
||||
dc_srom_iobase += 0x48; /* io offset for srom access */
|
||||
|
||||
memset (dest, 0, 128);
|
||||
for (offset=0; offset<64; offset++)
|
||||
{
|
||||
tmp = srom_rd (dc_srom_iobase, offset);
|
||||
*dest++ = le16_to_cpu(tmp);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* store data into the srom
|
||||
*/
|
||||
int dc_srom_store (u_short *src)
|
||||
{
|
||||
int offset;
|
||||
|
||||
/* get srom iobase from local network controller */
|
||||
pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
|
||||
dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
dc_srom_iobase = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
|
||||
dc_srom_iobase += 0x48; /* io offset for srom access */
|
||||
|
||||
for (offset=0; offset<64; offset++)
|
||||
{
|
||||
if (srom_wr (dc_srom_iobase, offset, *src) == -1)
|
||||
return (-1);
|
||||
src++;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
|
@ -1,292 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "srom.h"
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* START sequence
|
||||
* _ _________
|
||||
* SCLK _> \____
|
||||
* _ ____
|
||||
* SDIO _> \_________
|
||||
* : : :
|
||||
*/
|
||||
static void eepStart (void)
|
||||
{
|
||||
out8(I2C_BUS_DAT, 0x60); /* SCLK = high SDIO = high */
|
||||
out8(I2C_BUS_DIR, 0x60); /* set output direction for SCLK/SDIO */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = low */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = low */
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* STOP sequence
|
||||
* _______
|
||||
* SCLK _____/
|
||||
* _ ___
|
||||
* SDIO _>_______/
|
||||
* : : :
|
||||
*/
|
||||
static void eepStop (void)
|
||||
{
|
||||
out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = low */
|
||||
out8(I2C_BUS_DIR, 0x60); /* set output direction for SCLK/SDIO */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = low */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x60); /* SCLK = high SDIO = high */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DIR, 0x00); /* reset to input direction */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Read one byte from EEPROM
|
||||
* ___ ___ ___ ___ ___ ___ ___ ___
|
||||
* SCLK ___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \
|
||||
* _________________________________________________________________
|
||||
* SDIO > ^ ^ ^ ^ ^ ^ ^ ^
|
||||
* : : : : : : : : : : : : : : : : :
|
||||
*/
|
||||
static unsigned char eepReadByte (void)
|
||||
{
|
||||
register unsigned char buf = 0x00;
|
||||
register int i;
|
||||
|
||||
out8(I2C_BUS_DIR, 0x40);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = high */
|
||||
udelay(15);
|
||||
buf <<= 1;
|
||||
buf = (in8(I2C_BUS_DAT) & 0x20) ? (buf | 0x01) : (buf & 0xFE);
|
||||
out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */
|
||||
udelay(10);
|
||||
}
|
||||
return(buf);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Write one byte to EEPROM
|
||||
* ___ ___ ___ ___ ___ ___ ___ ___
|
||||
* SCLK __/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \__
|
||||
* _______ _______ _______ _______ _______ _______ _______ ________
|
||||
* SDIO X_______X_______X_______X_______X_______X_______X_______X________
|
||||
* : 7 : 6 : 5 : 4 : 3 : 2 : 1 : 0
|
||||
*/
|
||||
static void eepWriteByte (register unsigned char buf)
|
||||
{
|
||||
register int i;
|
||||
|
||||
(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = data */
|
||||
out8(I2C_BUS_DIR, 0x60);
|
||||
|
||||
for (i = 7; i >= 0; i--)
|
||||
{
|
||||
(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low SDIO=data */
|
||||
udelay(10);
|
||||
(buf & 0x80) ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK=high SDIO=data */
|
||||
udelay(15);
|
||||
(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low SDIO=data */
|
||||
udelay(10);
|
||||
buf <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Read data acknowledge of EEPROM
|
||||
* _______
|
||||
* SCLK ____/ \___
|
||||
* _______________
|
||||
* SDIO >
|
||||
* : : ^ :
|
||||
*/
|
||||
static int eepReadAck (void)
|
||||
{
|
||||
int retval;
|
||||
|
||||
out8(I2C_BUS_DIR, 0x40);
|
||||
out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = high */
|
||||
udelay(10);
|
||||
retval = (in8(I2C_BUS_DAT) & 0x20) ? ERROR : 0;
|
||||
udelay(10);
|
||||
out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */
|
||||
udelay(10);
|
||||
|
||||
return(retval);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Write data acknowledge to EEPROM
|
||||
* _______
|
||||
* SCLK ____/ \___
|
||||
*
|
||||
* SDIO >_______________
|
||||
* : : :
|
||||
*/
|
||||
static void eepWriteAck (unsigned char ack)
|
||||
{
|
||||
ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = ack */
|
||||
out8(I2C_BUS_DIR, 0x60);
|
||||
udelay(10);
|
||||
ack ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = ack */
|
||||
udelay(15);
|
||||
ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = ack */
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Read bytes from EEPROM
|
||||
*/
|
||||
int el_srom_load (addr, buf, cnt, device, block)
|
||||
unsigned char addr;
|
||||
unsigned char *buf;
|
||||
int cnt;
|
||||
unsigned char device;
|
||||
unsigned char block;
|
||||
{
|
||||
register int i;
|
||||
|
||||
for (i=0;i<cnt;i++)
|
||||
{
|
||||
eepStart();
|
||||
eepWriteByte(0xA0 | device | block);
|
||||
if (eepReadAck() == ERROR)
|
||||
{
|
||||
eepStop();
|
||||
return(ERROR);
|
||||
}
|
||||
eepWriteByte(addr++);
|
||||
if (eepReadAck() == ERROR)
|
||||
{
|
||||
eepStop();
|
||||
return(ERROR);
|
||||
}
|
||||
eepStart();
|
||||
|
||||
eepWriteByte(0xA1 | device | block);
|
||||
if (eepReadAck() == ERROR)
|
||||
{
|
||||
eepStop();
|
||||
return(ERROR);
|
||||
}
|
||||
|
||||
*buf++ = eepReadByte();
|
||||
eepWriteAck(1);
|
||||
eepStop();
|
||||
|
||||
if ((addr == 0) && (i != (cnt-1))) /* is it the same block ? */
|
||||
{
|
||||
if (block == FIRST_BLOCK)
|
||||
block = SECOND_BLOCK;
|
||||
else
|
||||
return(ERROR);
|
||||
}
|
||||
}
|
||||
return(cnt);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
*
|
||||
* Write bytes to EEPROM
|
||||
*
|
||||
*/
|
||||
int el_srom_store (addr, buf, cnt, device, block)
|
||||
unsigned char addr, *buf, device, block;
|
||||
int cnt;
|
||||
{
|
||||
register int i, retVal;
|
||||
|
||||
for (i=0;i<cnt;i++)
|
||||
{
|
||||
retVal = ERROR;
|
||||
do
|
||||
{
|
||||
eepStart();
|
||||
eepWriteByte(0xA0 | device | block);
|
||||
if ((retVal = eepReadAck()) == ERROR)
|
||||
eepStop();
|
||||
} while (retVal == ERROR);
|
||||
|
||||
eepWriteByte(addr++);
|
||||
if (eepReadAck() == ERROR) return(ERROR);
|
||||
|
||||
if ((addr == 0) && (i != (cnt-1))) /* is it the same block ? */
|
||||
{
|
||||
if (block == FIRST_BLOCK)
|
||||
block = SECOND_BLOCK;
|
||||
else
|
||||
return(ERROR);
|
||||
}
|
||||
|
||||
eepWriteByte(*buf++);
|
||||
if (eepReadAck() == ERROR)
|
||||
return(ERROR);
|
||||
|
||||
eepStop();
|
||||
}
|
||||
return(cnt);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* calculate checksum for ELTEC revision srom
|
||||
*/
|
||||
unsigned long el_srom_checksum (ptr, size)
|
||||
register unsigned char *ptr;
|
||||
unsigned long size;
|
||||
{
|
||||
u_long f, accu = 0;
|
||||
u_int i;
|
||||
u_char byte;
|
||||
|
||||
for (; size; size--)
|
||||
{
|
||||
byte = *ptr++;
|
||||
for (i = 8; i; i--)
|
||||
{
|
||||
f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
|
||||
accu >>= 1; accu ^= f;
|
||||
byte >>= 1;
|
||||
}
|
||||
}
|
||||
return(accu);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
|
@ -1,512 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
|
||||
* fixed monitor protection part
|
||||
*
|
||||
* 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
|
||||
* of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
|
||||
* any other.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/pci_io.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
|
||||
/*flash command address offsets*/
|
||||
|
||||
#define ADDR0 (0x555)
|
||||
#define ADDR1 (0x2AA)
|
||||
#define ADDR3 (0x001)
|
||||
|
||||
#define FLASH_WORD_SIZE unsigned char
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size1, size2;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
|
||||
{
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* initialise 1st flash */
|
||||
size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN)
|
||||
{
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size1, size1<<20);
|
||||
}
|
||||
|
||||
/* initialise 2nd flash */
|
||||
size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
|
||||
|
||||
if (flash_info[1].flash_id == FLASH_UNKNOWN)
|
||||
{
|
||||
printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
|
||||
size2, size2<<20);
|
||||
}
|
||||
|
||||
/* monitor protection ON by default */
|
||||
if (size1 == 512*1024)
|
||||
{
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
FLASH_BASE0_PRELIM,
|
||||
FLASH_BASE0_PRELIM+monitor_flash_len-1,
|
||||
&flash_info[0]);
|
||||
}
|
||||
if (size2 == 512*1024)
|
||||
{
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
FLASH_BASE1_PRELIM,
|
||||
FLASH_BASE1_PRELIM+monitor_flash_len-1,
|
||||
&flash_info[1]);
|
||||
}
|
||||
if (size2 == 4*1024*1024)
|
||||
{
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
|
||||
&flash_info[1]);
|
||||
}
|
||||
|
||||
return (size1 + size2);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
int k;
|
||||
int size;
|
||||
int erased;
|
||||
volatile unsigned long *flash;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
flash_init();
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
printf ("AMD ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case AMD_ID_F040B:
|
||||
printf ("AM29F040B (4 Mbit)\n");
|
||||
break;
|
||||
case AMD_ID_F016D:
|
||||
printf ("AM29F016D (16 Mbit)\n");
|
||||
break;
|
||||
case AMD_ID_F032B:
|
||||
printf ("AM29F032B (32 Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
if (info->size >= (1 << 20)) {
|
||||
printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
|
||||
} else {
|
||||
printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
|
||||
}
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
if (i != (info->sector_count-1))
|
||||
size = info->start[i+1] - info->start[i];
|
||||
else
|
||||
size = info->start[0] + info->size - info->start[i];
|
||||
|
||||
erased = 1;
|
||||
flash = (volatile unsigned long *)info->start[i];
|
||||
size = size >> 2; /* divide by 4 for longword access */
|
||||
for (k=0; k<size; k++) {
|
||||
if (*flash++ != 0xffffffff) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
|
||||
printf (" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ",
|
||||
info->protect[i] ? "RO " : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
ulong vendor, devid;
|
||||
ulong base = (ulong)addr;
|
||||
volatile unsigned char *caddr = (unsigned char *)addr;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
|
||||
#endif
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
caddr[0] = 0xF0; /* reset bank */
|
||||
udelay(10);
|
||||
|
||||
eieio();
|
||||
caddr[0x555] = 0xAA;
|
||||
udelay(10);
|
||||
caddr[0x2AA] = 0x55;
|
||||
udelay(10);
|
||||
caddr[0x555] = 0x90;
|
||||
|
||||
udelay(10);
|
||||
|
||||
vendor = caddr[0];
|
||||
devid = caddr[1];
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("Manufacturer: 0x%lx\n", vendor);
|
||||
#endif
|
||||
|
||||
vendor &= 0xff;
|
||||
devid &= 0xff;
|
||||
|
||||
/* We accept only two AMD types */
|
||||
switch (vendor) {
|
||||
case (FLASH_WORD_SIZE)AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
switch (devid) {
|
||||
case (FLASH_WORD_SIZE)AMD_ID_F040B:
|
||||
info->flash_id |= AMD_ID_F040B;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_F016D:
|
||||
info->flash_id |= AMD_ID_F016D;
|
||||
info->sector_count = 32;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_F032B:
|
||||
info->flash_id |= AMD_ID_F032B;
|
||||
info->sector_count = 64;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
|
||||
#endif
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* sector base address */
|
||||
info->start[i] = base + i * (info->size / info->sector_count);
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
caddr = (volatile unsigned char *)(info->start[i]);
|
||||
info->protect[i] = caddr[2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
caddr = (volatile unsigned char *)info->start[0];
|
||||
caddr[0] = 0xF0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
int rc = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
if (info->flash_id & FLASH_MAN_SST) {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
|
||||
udelay(30000); /* wait 30 ms */
|
||||
}
|
||||
else
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
|
||||
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
|
||||
ulong start;
|
||||
int flag;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((volatile FLASH_WORD_SIZE *)dest) &
|
||||
(FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
|
||||
{
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
|
@ -1,159 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_SYS_L2_BAB7xx)
|
||||
|
||||
#include <pci.h>
|
||||
#include <mpc106.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/* defines L2CR register for MPC750 */
|
||||
|
||||
#define L2CR_E 0x80000000
|
||||
#define L2CR_256K 0x10000000
|
||||
#define L2CR_512K 0x20000000
|
||||
#define L2CR_1024K 0x30000000
|
||||
#define L2CR_I 0x00200000
|
||||
#define L2CR_SL 0x00008000
|
||||
#define L2CR_IP 0x00000001
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static int dummy (int dummy)
|
||||
{
|
||||
return (dummy+1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
int l2_cache_enable (int l2control)
|
||||
{
|
||||
if (l2control) /* BAB750 */
|
||||
{
|
||||
mtspr(SPRN_L2CR, l2control);
|
||||
mtspr(SPRN_L2CR, (l2control | L2CR_I));
|
||||
while (mfspr(SPRN_L2CR) & L2CR_IP)
|
||||
;
|
||||
mtspr(SPRN_L2CR, (l2control | L2CR_E));
|
||||
return (0);
|
||||
}
|
||||
else /* BAB740 */
|
||||
{
|
||||
int picr1, picr2, mask;
|
||||
int picr2CacheSize, cacheSize;
|
||||
int *d;
|
||||
int devbusfn;
|
||||
u32 reg32;
|
||||
|
||||
devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
|
||||
PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
|
||||
if (devbusfn == -1)
|
||||
return (-1);
|
||||
|
||||
pci_read_config_dword (devbusfn, PCI_PICR2, ®32);
|
||||
reg32 &= ~PICR2_L2_EN;
|
||||
pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
|
||||
|
||||
/* cache size */
|
||||
if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04)
|
||||
{
|
||||
/* cache size is 512 KB */
|
||||
picr2CacheSize = PICR2_L2_SIZE_512K;
|
||||
cacheSize = 0x80000;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* cache size is 256 KB */
|
||||
picr2CacheSize = PICR2_L2_SIZE_256K;
|
||||
cacheSize = 0x40000;
|
||||
}
|
||||
|
||||
/* setup PICR1 */
|
||||
mask =
|
||||
~(PICR1_CF_BREAD_WS(1) |
|
||||
PICR1_CF_BREAD_WS(2) |
|
||||
PICR1_CF_CBA(0xff) |
|
||||
PICR1_CF_CACHE_1G |
|
||||
PICR1_CF_DPARK |
|
||||
PICR1_CF_APARK |
|
||||
PICR1_CF_L2_CACHE_MASK);
|
||||
|
||||
picr1 =
|
||||
(PICR1_CF_CBA(0x3f) |
|
||||
PICR1_CF_CACHE_1G |
|
||||
PICR1_CF_APARK |
|
||||
PICR1_CF_DPARK |
|
||||
PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
|
||||
|
||||
pci_read_config_dword (devbusfn, PCI_PICR1, ®32);
|
||||
reg32 &= mask;
|
||||
reg32 |= picr1;
|
||||
pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
|
||||
|
||||
/*
|
||||
* invalidate all L2 cache
|
||||
*/
|
||||
picr2 =
|
||||
(PICR2_CF_INV_MODE |
|
||||
PICR2_CF_HIT_HIGH |
|
||||
PICR2_CF_MOD_HIGH |
|
||||
PICR2_CF_L2_HIT_DELAY(1) |
|
||||
PICR2_CF_APHASE_WS(1) |
|
||||
picr2CacheSize);
|
||||
|
||||
pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
|
||||
|
||||
/*
|
||||
* dummy transactions
|
||||
*/
|
||||
for (d=0; d<(int *)(2*cacheSize); d++)
|
||||
dummy(*d);
|
||||
|
||||
pci_write_config_dword (devbusfn, PCI_PICR2,
|
||||
(picr2 | PICR2_CF_FLUSH_L2));
|
||||
|
||||
/* setup PICR2 */
|
||||
picr2 =
|
||||
(PICR2_CF_FAST_CASTOUT |
|
||||
PICR2_CF_WDATA |
|
||||
PICR2_CF_ADDR_ONLY_DISABLE |
|
||||
PICR2_CF_HIT_HIGH |
|
||||
PICR2_CF_MOD_HIGH |
|
||||
PICR2_L2_UPDATE_EN |
|
||||
PICR2_L2_EN |
|
||||
PICR2_CF_APHASE_WS(1) |
|
||||
PICR2_CF_DATA_RAM_PBURST |
|
||||
PICR2_CF_L2_HIT_DELAY(1) |
|
||||
PICR2_CF_SNOOP_WS(2) |
|
||||
picr2CacheSize);
|
||||
|
||||
pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#endif /* (CONFIG_SYS_L2_BAB7xx) */
|
|
@ -1,546 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* includes */
|
||||
#include <common.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <pci.h>
|
||||
#include <net.h>
|
||||
#include <mpc106.h>
|
||||
#include <w83c553f.h>
|
||||
#include "srom.h"
|
||||
|
||||
/* imports */
|
||||
extern int l2_cache_enable (int l2control);
|
||||
extern void *nvram_read (void *dest, const short src, size_t count);
|
||||
extern void nvram_write (short dest, const void *src, size_t count);
|
||||
|
||||
/* globals */
|
||||
unsigned int ata_reset_time = 60;
|
||||
unsigned int scsi_reset_time = 10;
|
||||
unsigned int eltec_board;
|
||||
|
||||
/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860
|
||||
* values fixed after board identification
|
||||
*/
|
||||
unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875;
|
||||
unsigned int scsi_max_scsi_id = 15;
|
||||
unsigned char scsi_sym53c8xx_ccf = 0x13;
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* handle sroms on BAB740/750
|
||||
* fix ether address
|
||||
* L2 cache initialization
|
||||
* ide dma control
|
||||
*/
|
||||
int misc_init_r (void)
|
||||
{
|
||||
revinfo eerev;
|
||||
char *ptr;
|
||||
u_int i, l, initSrom, copyNv;
|
||||
char buf[256];
|
||||
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
|
||||
0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
|
||||
pci_dev_t bdf;
|
||||
|
||||
char sromSYM[] = {
|
||||
#ifdef TULIP_BUG
|
||||
/* 10BaseT, 100BaseTx no full duplex modes */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
|
||||
0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
|
||||
0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61,
|
||||
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8
|
||||
#endif
|
||||
/* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
|
||||
0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
|
||||
0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88,
|
||||
0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80,
|
||||
0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61,
|
||||
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77
|
||||
};
|
||||
|
||||
char sromMII[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00,
|
||||
0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
|
||||
0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08,
|
||||
0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78,
|
||||
0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41
|
||||
};
|
||||
|
||||
/*
|
||||
* Check/Remake revision info
|
||||
*/
|
||||
initSrom = 0;
|
||||
copyNv = 0;
|
||||
|
||||
/* read out current revision srom contens */
|
||||
el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
|
||||
SECOND_DEVICE, FIRST_BLOCK);
|
||||
|
||||
/* read out current nvram shadow image */
|
||||
nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
|
||||
|
||||
if (strcmp (eerev.magic, "ELTEC") != 0)
|
||||
{
|
||||
/* srom is not initialized -> create a default revision info */
|
||||
for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
|
||||
*ptr++ = 0x00;
|
||||
strcpy(eerev.magic, "ELTEC");
|
||||
eerev.revrev[0] = 1;
|
||||
eerev.revrev[1] = 0;
|
||||
eerev.size = 0x00E0;
|
||||
eerev.category[0] = 0x01;
|
||||
|
||||
/* node id from dead e128 as default */
|
||||
eerev.etheraddr[0] = 0x00;
|
||||
eerev.etheraddr[1] = 0x00;
|
||||
eerev.etheraddr[2] = 0x5B;
|
||||
eerev.etheraddr[3] = 0x00;
|
||||
eerev.etheraddr[4] = 0x2E;
|
||||
eerev.etheraddr[5] = 0x4D;
|
||||
|
||||
/* cache config word for bab750 */
|
||||
*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
|
||||
|
||||
initSrom = 1; /* force dialog */
|
||||
copyNv = 1; /* copy to nvram */
|
||||
}
|
||||
|
||||
if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CONFIG_SYS_SROM_SIZE) !=
|
||||
el_srom_checksum((u_char*)buf, CONFIG_SYS_SROM_SIZE)))
|
||||
{
|
||||
printf ("Invalid revision info copy in nvram !\n");
|
||||
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
|
||||
printf (" <r> to reenter revision info.\n");
|
||||
printf ("=> ");
|
||||
if (0 != readline (NULL))
|
||||
{
|
||||
switch ((char)toupper(console_buffer[0]))
|
||||
{
|
||||
case 'C':
|
||||
copyNv = 1;
|
||||
break;
|
||||
case 'R':
|
||||
copyNv = 1;
|
||||
initSrom = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (initSrom)
|
||||
{
|
||||
memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
|
||||
printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]);
|
||||
if (0 != readline (NULL))
|
||||
{
|
||||
eerev.revision[0][0] = (char)toupper(console_buffer[0]);
|
||||
memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
|
||||
}
|
||||
|
||||
printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]);
|
||||
if (1 == readline (NULL))
|
||||
{
|
||||
eerev.revision[0][1] = (char)toupper(console_buffer[0]);
|
||||
}
|
||||
|
||||
printf ("Enter board name (V-XXXX-XXXX): %s ", (char *)&eerev.board);
|
||||
if (11 == readline (NULL))
|
||||
{
|
||||
for (i=0; i<11; i++)
|
||||
eerev.board[i] = (char)toupper(console_buffer[i]);
|
||||
eerev.board[11] = '\0';
|
||||
}
|
||||
|
||||
printf ("Enter serial number: %s ", (char *)&eerev.serial );
|
||||
if (6 == readline (NULL))
|
||||
{
|
||||
for (i=0; i<6; i++)
|
||||
eerev.serial[i] = console_buffer[i];
|
||||
eerev.serial[6] = '\0';
|
||||
}
|
||||
|
||||
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ",
|
||||
eerev.etheraddr[0], eerev.etheraddr[1],
|
||||
eerev.etheraddr[2], eerev.etheraddr[3],
|
||||
eerev.etheraddr[4], eerev.etheraddr[5]);
|
||||
if (12 == readline (NULL))
|
||||
{
|
||||
for (i=0; i<12; i+=2)
|
||||
eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
|
||||
hex[toupper(console_buffer[i+1])-'0']);
|
||||
}
|
||||
|
||||
l = strlen ((char *)&eerev.text);
|
||||
printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
|
||||
if (0 != readline (NULL))
|
||||
{
|
||||
for (i = l; i<63; i++)
|
||||
eerev.text[i] = console_buffer[i-l];
|
||||
eerev.text[63] = '\0';
|
||||
}
|
||||
|
||||
if (strstr ((char *)&eerev.board, "75") != NULL)
|
||||
eltec_board = 750;
|
||||
else
|
||||
eltec_board = 740;
|
||||
|
||||
if (eltec_board == 750)
|
||||
{
|
||||
if (CPU_TYPE == CPU_TYPE_750)
|
||||
*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
|
||||
else
|
||||
*(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH;
|
||||
|
||||
printf("Enter L2Cache config word with leading zero (HEX): %08X ",
|
||||
*(int*)&eerev.res[0] );
|
||||
if (0 != readline (NULL))
|
||||
{
|
||||
for (i=0; i<7; i+=2)
|
||||
{
|
||||
eerev.res[i>>1] =
|
||||
(char)(16*hex[toupper(console_buffer[i])-'0'] +
|
||||
hex[toupper(console_buffer[i+1])-'0']);
|
||||
}
|
||||
}
|
||||
|
||||
/* prepare network eeprom */
|
||||
sromMII[20] = eerev.etheraddr[0];
|
||||
sromMII[21] = eerev.etheraddr[1];
|
||||
sromMII[22] = eerev.etheraddr[2];
|
||||
sromMII[23] = eerev.etheraddr[3];
|
||||
sromMII[24] = eerev.etheraddr[4];
|
||||
sromMII[25] = eerev.etheraddr[5];
|
||||
printf("\nSRom: Writing DEC21143 MII info .. ");
|
||||
|
||||
if (dc_srom_store ((u_short *)sromMII) == -1)
|
||||
printf("FAILED\n");
|
||||
else
|
||||
printf("OK\n");
|
||||
}
|
||||
|
||||
if (eltec_board == 740)
|
||||
{
|
||||
*(int *)&eerev.res[0] = 0;
|
||||
sromSYM[20] = eerev.etheraddr[0];
|
||||
sromSYM[21] = eerev.etheraddr[1];
|
||||
sromSYM[22] = eerev.etheraddr[2];
|
||||
sromSYM[23] = eerev.etheraddr[3];
|
||||
sromSYM[24] = eerev.etheraddr[4];
|
||||
sromSYM[25] = eerev.etheraddr[5];
|
||||
printf("\nSRom: Writing DEC21143 SYM info .. ");
|
||||
|
||||
if (dc_srom_store ((u_short *)sromSYM) == -1)
|
||||
printf("FAILED\n");
|
||||
else
|
||||
printf("OK\n");
|
||||
}
|
||||
|
||||
/* update CRC */
|
||||
eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
|
||||
|
||||
/* write new values */
|
||||
printf("\nSRom: Writing revision info ...... ");
|
||||
if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
|
||||
sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
|
||||
printf("FAILED\n\n");
|
||||
else
|
||||
printf("OK\n\n");
|
||||
|
||||
/* write new values as shadow image to nvram */
|
||||
nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
|
||||
|
||||
} /*if (initSrom) */
|
||||
|
||||
/* copy current values as shadow image to nvram */
|
||||
if (initSrom == 0 && copyNv == 1)
|
||||
nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
|
||||
|
||||
/* update environment */
|
||||
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||
eerev.etheraddr[0], eerev.etheraddr[1],
|
||||
eerev.etheraddr[2], eerev.etheraddr[3],
|
||||
eerev.etheraddr[4], eerev.etheraddr[5]);
|
||||
setenv ("ethaddr", buf);
|
||||
|
||||
/* print actual board identification */
|
||||
printf("Ident: %s Ser %s Rev %c%c\n",
|
||||
eerev.board, (char *)&eerev.serial,
|
||||
eerev.revision[0][0], eerev.revision[0][1]);
|
||||
|
||||
/* global board ident */
|
||||
if (strstr ((char *)&eerev.board, "75") != NULL)
|
||||
eltec_board = 750;
|
||||
else
|
||||
eltec_board = 740;
|
||||
|
||||
/*
|
||||
* L2 cache configuration
|
||||
*/
|
||||
#if defined(CONFIG_SYS_L2_BAB7xx)
|
||||
ptr = getenv("l2cache");
|
||||
if (*ptr == '0')
|
||||
{
|
||||
printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf ("Cache: L2 activated on BAB%d\n", eltec_board);
|
||||
l2_cache_enable(*(int*)&eerev.res[0]);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Reconfig ata reset timeout from environment
|
||||
*/
|
||||
if ((ptr = getenv ("ata_reset_time")) != NULL)
|
||||
{
|
||||
ata_reset_time = (int)simple_strtoul (ptr, NULL, 10);
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf (buf, "%d", ata_reset_time);
|
||||
setenv ("ata_reset_time", buf);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reconfig scsi reset timeout from environment
|
||||
*/
|
||||
if ((ptr = getenv ("scsi_reset_time")) != NULL)
|
||||
{
|
||||
scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10);
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf (buf, "%d", scsi_reset_time);
|
||||
setenv ("scsi_reset_time", buf);
|
||||
}
|
||||
|
||||
|
||||
if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0)
|
||||
{
|
||||
if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0)
|
||||
{
|
||||
/* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 MHz */
|
||||
scsi_dev_id = PCI_DEVICE_ID_NCR_53C860;
|
||||
scsi_max_scsi_id = 7;
|
||||
scsi_sym53c8xx_ccf = 0x15;
|
||||
pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0);
|
||||
}
|
||||
|
||||
if ((ptr = getenv ("ide_dma_off")) != NULL)
|
||||
{
|
||||
u_long dma_off = simple_strtoul (ptr, NULL, 10);
|
||||
/*
|
||||
* setup user defined registers
|
||||
* s.a. linux/drivers/ide/sl82c105.c
|
||||
*/
|
||||
bdf |= PCI_BDF(0,0,1); /* ide user reg at bdf function 1 */
|
||||
if (dma_off & 1)
|
||||
{
|
||||
pci_write_config_byte (bdf, 0x46, 1);
|
||||
printf("IDE: DMA off flag set: Bus 0 : Dev 0\n");
|
||||
}
|
||||
if (dma_off & 2)
|
||||
{
|
||||
pci_write_config_byte (bdf, 0x4a, 1);
|
||||
printf("IDE: DMA off flag set: Bus 0 : Dev 1\n");
|
||||
}
|
||||
if (dma_off & 4)
|
||||
{
|
||||
pci_write_config_byte (bdf, 0x4e, 1);
|
||||
printf("IDE: DMA off flag set: Bus 1 : Dev 0\n");
|
||||
}
|
||||
if (dma_off & 8)
|
||||
{
|
||||
pci_write_config_byte (bdf, 0x52, 1);
|
||||
printf("IDE: DMA off flag set: Bus 1 : Dev 1\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* BAB740 uses KENDIN KS8761 modem chip with not common setup values
|
||||
*/
|
||||
#ifdef CONFIG_TULIP_SELECT_MEDIA
|
||||
|
||||
/* Register bits.
|
||||
*/
|
||||
#define BMR_SWR 0x00000001 /* Software Reset */
|
||||
#define STS_TS 0x00700000 /* Transmit Process State */
|
||||
#define STS_RS 0x000e0000 /* Receive Process State */
|
||||
#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
|
||||
#define OMR_SR 0x00000002 /* Start/Stop Receive */
|
||||
#define OMR_PS 0x00040000 /* Port Select */
|
||||
#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
|
||||
#define OMR_PM 0x00000080 /* Pass All Multicast */
|
||||
#define OMR_PR 0x00000040 /* Promiscuous Mode */
|
||||
#define OMR_PCS 0x00800000 /* PCS Function */
|
||||
#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */
|
||||
|
||||
/* Ethernet chip registers.
|
||||
*/
|
||||
#define DE4X5_BMR 0x000 /* Bus Mode Register */
|
||||
#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
|
||||
#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
|
||||
#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
|
||||
#define DE4X5_STS 0x028 /* Status Register */
|
||||
#define DE4X5_OMR 0x030 /* Operation Mode Register */
|
||||
#define DE4X5_SISR 0x060 /* SIA Status Register */
|
||||
#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
|
||||
#define DE4X5_TXRX 0x070 /* SIA Transmit and Receive Register */
|
||||
#define DE4X5_GPPR 0x078 /* General Purpose Port register */
|
||||
#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static int INL(struct eth_device* dev, u_long addr)
|
||||
{
|
||||
return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static void OUTL(struct eth_device* dev, int command, u_long addr)
|
||||
{
|
||||
*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static void media_reg_init (
|
||||
struct eth_device* dev,
|
||||
u32 csr14,
|
||||
u32 csr15_dir,
|
||||
u32 csr15_v0,
|
||||
u32 csr15_v1,
|
||||
u32 csr6 )
|
||||
{
|
||||
OUTL(dev, 0, DE4X5_OMR); /* CSR6 */
|
||||
udelay(10 * 1000);
|
||||
OUTL(dev, 0, DE4X5_SICR); /* CSR13 */
|
||||
OUTL(dev, 1, DE4X5_SICR); /* CSR13 */
|
||||
udelay(10 * 1000);
|
||||
OUTL(dev, csr14, DE4X5_TXRX); /* CSR14 */
|
||||
OUTL(dev, csr15_dir, DE4X5_GPPR); /* CSR15 */
|
||||
OUTL(dev, csr15_v0, DE4X5_GPPR); /* CSR15 */
|
||||
udelay(10 * 1000);
|
||||
OUTL(dev, csr15_v1, DE4X5_GPPR); /* CSR15 */
|
||||
OUTL(dev, 0x00000301, DE4X5_SISR); /* CSR12 */
|
||||
OUTL(dev, csr6, DE4X5_OMR); /* CSR6 */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
void dc21x4x_select_media(struct eth_device* dev)
|
||||
{
|
||||
int i, status, ext;
|
||||
extern unsigned int eltec_board;
|
||||
|
||||
if (eltec_board == 740)
|
||||
{
|
||||
printf("SYM media select "); /* BAB740 */
|
||||
/* start autoneg. with 10 mbit */
|
||||
media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080);
|
||||
ext = status = 0;
|
||||
for (i=0; i<2000+ext; i++)
|
||||
{
|
||||
status = INL(dev, DE4X5_SISR);
|
||||
udelay(1000);
|
||||
if (status & 0x2000) ext = 2000;
|
||||
if ((status & 0x7000) == 0x5000) break;
|
||||
}
|
||||
|
||||
/* autoneg. ok -> 100MB FD */
|
||||
if ((status & 0x0100f000) == 0x0100d000)
|
||||
{
|
||||
media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280);
|
||||
printf("100baseTx-FD\n");
|
||||
}
|
||||
/* autoneg. ok -> 100MB HD */
|
||||
else if ((status & 0x0080f000) == 0x0080d000)
|
||||
{
|
||||
media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080);
|
||||
printf("100baseTx\n");
|
||||
}
|
||||
/* autoneg. ok -> 10MB FD */
|
||||
else if ((status & 0x0040f000) == 0x0040d000)
|
||||
{
|
||||
media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280);
|
||||
printf("10baseT-FD\n");
|
||||
}
|
||||
/* autoneg. fail -> 10MB HD */
|
||||
else
|
||||
{
|
||||
media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008,
|
||||
(OMR_SDP | OMR_TTM | OMR_PM));
|
||||
printf("10baseT\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("MII media selected\n"); /* BAB750 */
|
||||
OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); /* CSR6 */
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_TULIP_SELECT_MEDIA */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
|
@ -1,120 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI initialisation for the MPC10x.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <mpc106.h>
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
struct pci_controller local_hose;
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
struct pci_controller* hose = (struct pci_controller *)&local_hose;
|
||||
u32 reg32;
|
||||
u16 reg16;
|
||||
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
/*
|
||||
* Attention: pci_hose_phys_to_bus() failes in address compare,
|
||||
* so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
|
||||
*/
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE-1,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* PCI memory space */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CONFIG_SYS_PCI_MEM_BUS,
|
||||
CONFIG_SYS_PCI_MEM_PHYS,
|
||||
CONFIG_SYS_PCI_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* ISA/PCI memory space */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CONFIG_SYS_ISA_MEM_BUS,
|
||||
CONFIG_SYS_ISA_MEM_PHYS,
|
||||
CONFIG_SYS_ISA_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region(hose->regions + 3,
|
||||
CONFIG_SYS_PCI_IO_BUS,
|
||||
CONFIG_SYS_PCI_IO_PHYS,
|
||||
CONFIG_SYS_PCI_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
/* ISA/PCI I/O space */
|
||||
pci_set_region(hose->regions + 4,
|
||||
CONFIG_SYS_ISA_IO_BUS,
|
||||
CONFIG_SYS_ISA_IO_PHYS,
|
||||
CONFIG_SYS_ISA_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 5;
|
||||
|
||||
pci_setup_indirect(hose,
|
||||
MPC106_REG_ADDR,
|
||||
MPC106_REG_DATA);
|
||||
|
||||
pci_register_hose(hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
|
||||
/* Initialises the MPC10x PCI Configuration regs. */
|
||||
pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, ®32);
|
||||
reg32 |= PICR2_CF_SNOOP_WS(3) |
|
||||
PICR2_CF_FLUSH_L2 |
|
||||
PICR2_CF_L2_HIT_DELAY(3) |
|
||||
PICR2_CF_APHASE_WS(3);
|
||||
reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
|
||||
pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);
|
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
|
||||
|
||||
/* Clear non-reserved bits in status register */
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
|
||||
|
||||
pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, ®32);
|
||||
reg32 |= PICR1_CF_CBA(63) |
|
||||
PICR1_CF_BREAD_WS(2) |
|
||||
PICR1_MCP_EN |
|
||||
PICR1_CF_DPARK |
|
||||
PICR1_PROC_TYPE_604 |
|
||||
PICR1_CF_LOOP_SNOOP |
|
||||
PICR1_CF_APARK;
|
||||
pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCI */
|
|
@ -1,102 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* common srom defs */
|
||||
#define FIRST_DEVICE 0x00
|
||||
#define SECOND_DEVICE 0x04
|
||||
#define FIRST_BLOCK 0x00
|
||||
#define SECOND_BLOCK 0x02
|
||||
#define BLOCK_SIZE 0x100
|
||||
#define ERROR (-1)
|
||||
|
||||
#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100
|
||||
#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100
|
||||
|
||||
#define CPU_TYPE_740 0x08
|
||||
#define CPU_TYPE_750 0x08
|
||||
#define CPU_TYPE ((get_pvr()>>16)&0xffff)
|
||||
|
||||
#define ABS(x) ((x<0)?-x:x)
|
||||
#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
|
||||
|
||||
/* bab7xx ELTEC srom */
|
||||
#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220)
|
||||
#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221)
|
||||
|
||||
/* srom at mpc107 */
|
||||
#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */
|
||||
#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */
|
||||
#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */
|
||||
#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */
|
||||
#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */
|
||||
#define MPC107_I2C_TIMEOUT 10000000
|
||||
|
||||
/* i82559 */
|
||||
#define EE_ADDR_BITS 6
|
||||
#define EE_SIZE 0x40 /* 0x40 words */
|
||||
#define EE_CHECKSUM 0xBABA
|
||||
|
||||
/* dc21143 */
|
||||
#define DEC_SROM_SIZE 128
|
||||
|
||||
|
||||
/*
|
||||
* structure of revision srom
|
||||
*/
|
||||
typedef struct {
|
||||
char magic[8]; /* 000 - Magic number */
|
||||
char revrev[2]; /* 008 - Revision of structure */
|
||||
unsigned short size; /* 00A - Size of CRC area */
|
||||
unsigned long crc; /* 00C - CRC */
|
||||
char board[16]; /* 010 - Board Revision information */
|
||||
char option[4][16]; /* 020 - Option Revision information */
|
||||
char serial[8]; /* 060 - Board serial number */
|
||||
char etheraddr[6]; /* 068 - Ethernet node addresse */
|
||||
char reserved[2]; /* 06E - Reserved */
|
||||
char revision[7][2]; /* 070 - Revision codes */
|
||||
char category[2]; /* 07E - Category codes */
|
||||
char text[64]; /* 080 - Text field */
|
||||
char res[64]; /* 0C0 - Reserved */
|
||||
} revinfo;
|
||||
|
||||
unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
|
||||
int el_srom_load (unsigned char addr, unsigned char *buf, int cnt,
|
||||
unsigned char device, unsigned char block);
|
||||
int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
|
||||
unsigned char device, unsigned char block);
|
||||
|
||||
int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
|
||||
int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
|
||||
int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
|
||||
unsigned char offset, unsigned char val);
|
||||
int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
|
||||
unsigned char device, unsigned char block);
|
||||
int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
|
||||
unsigned char device, unsigned char block);
|
||||
|
||||
int dc_srom_load (unsigned short *dest);
|
||||
int dc_srom_store (unsigned short *src);
|
||||
|
||||
unsigned short eepro100_srom_checksum (unsigned short *sromdata);
|
||||
void eepro100_srom_load (unsigned short *destination);
|
||||
int eepro100_srom_store (unsigned short *source);
|
|
@ -357,7 +357,6 @@ PCIPPC2 powerpc 74xx_7xx pcippc2
|
|||
PCIPPC6 powerpc 74xx_7xx pcippc2
|
||||
ppmc7xx powerpc 74xx_7xx
|
||||
ZUMA powerpc 74xx_7xx evb64260
|
||||
BAB7xx powerpc 74xx_7xx bab7xx eltec
|
||||
ELPPC powerpc 74xx_7xx elppc eltec
|
||||
CPCI750 powerpc 74xx_7xx cpci750 esd
|
||||
mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale
|
||||
|
|
|
@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
|
|||
|
||||
Board Arch CPU removed Commit last known maintainer/contact
|
||||
=============================================================================
|
||||
BAB7xx powerpc MPC740/MPC750 - 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
|
||||
xm250 arm pxa c746cdd 2011-25-11
|
||||
pleb2 arm pxa b185a1c 2011-25-11
|
||||
cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris <kharris@nexus-tech.net>
|
||||
|
|
|
@ -1,473 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define GTREGREAD(x) 0xffffffff /* needed for debug */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
/* these hardware addresses are pretty bogus, please change them to
|
||||
suit your needs */
|
||||
|
||||
/* first ethernet */
|
||||
#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
|
||||
|
||||
#define CONFIG_IPADDR 192.168.0.105
|
||||
#define CONFIG_SERVERIP 192.168.0.100
|
||||
|
||||
#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
|
||||
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate */
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp 1000000; " \
|
||||
"setenv bootargs root=ramfs console=ttyS00,9600 " \
|
||||
"ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:eth0:none; " \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_SCSI
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_FDC
|
||||
#define CONFIG_CMD_ELF
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
/*
|
||||
* choose between COM1 and COM2 as serial console
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
#define CONFIG_SYS_BOARD_ASM_INIT
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/*
|
||||
* Choose the address mapping scheme for the MPC106 mem controller.
|
||||
* Default is mapping B (CHRP), set this define to choose mapping A (PReP).
|
||||
*/
|
||||
#define CONFIG_SYS_ADDRESS_MAP_A
|
||||
#ifdef CONFIG_SYS_ADDRESS_MAP_A
|
||||
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#define CONFIG_SYS_PCI_MEM_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEM_PHYS 0xc0000000
|
||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x3f000000
|
||||
|
||||
#define CONFIG_SYS_ISA_MEM_BUS 0
|
||||
#define CONFIG_SYS_ISA_MEM_PHYS 0
|
||||
#define CONFIG_SYS_ISA_MEM_SIZE 0
|
||||
|
||||
#define CONFIG_SYS_PCI_IO_BUS 0x1000
|
||||
#define CONFIG_SYS_PCI_IO_PHYS 0x81000000
|
||||
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000-CONFIG_SYS_PCI_IO_BUS
|
||||
|
||||
#define CONFIG_SYS_ISA_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_ISA_IO_PHYS 0x80000000
|
||||
#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
|
||||
|
||||
#else
|
||||
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
|
||||
|
||||
#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
|
||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
|
||||
|
||||
#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
|
||||
#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
|
||||
#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
|
||||
|
||||
#define CONFIG_SYS_PCI_IO_BUS 0x00800000
|
||||
#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
|
||||
#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
|
||||
|
||||
#define CONFIG_SYS_ISA_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
|
||||
#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
|
||||
|
||||
#endif /*CONFIG_SYS_ADDRESS_MAP_A */
|
||||
|
||||
#define CONFIG_SYS_60X_PCI_MEM_OFFSET 0x00000000
|
||||
|
||||
/* driver defines FDC,IDE,... */
|
||||
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
|
||||
#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
|
||||
#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xfff00000
|
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Flash mapping/organization on the MPC10x.
|
||||
*/
|
||||
#define FLASH_BASE0_PRELIM 0xff800000
|
||||
#define FLASH_BASE1_PRELIM 0xffc00000
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*
|
||||
*/
|
||||
/* No command line, one static partition */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support
|
||||
*
|
||||
* Note: fake mtd_id used, no linux mtd map file
|
||||
*/
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=bab7xx-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
|
||||
#undef CONFIG_SYS_MEMTEST
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
||||
#define CONFIG_SYS_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
|
||||
#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
|
||||
/*
|
||||
* We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
|
||||
* user applications can use the remaining space for other purposes.
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
|
||||
#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
|
||||
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
|
||||
#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
|
||||
|
||||
/*
|
||||
* Serial devices
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK 1843200
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
|
||||
|
||||
/*
|
||||
* PCI stuff
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_SYS_EARLY_PCI_INIT
|
||||
#define CONFIG_PCI_PNP /* pci plug-and-play */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO
|
||||
#undef CONFIG_PCI_SCAN_SHOW
|
||||
|
||||
/*
|
||||
* Video console (graphic: SMI LynxEM, keyboard: i8042)
|
||||
*/
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VIDEO_SMI_LYNXEM
|
||||
#define CONFIG_I8042_KBD
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_CONSOLE_TIME
|
||||
#define CONFIG_CONSOLE_EXTRA_INFO
|
||||
#define CONFIG_CONSOLE_CURSOR
|
||||
#define CONFIG_SYS_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
|
||||
|
||||
/*
|
||||
* IDE/SCSI globals
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned int eltec_board;
|
||||
extern unsigned int ata_reset_time;
|
||||
extern unsigned int scsi_reset_time;
|
||||
extern unsigned short scsi_dev_id;
|
||||
extern unsigned int scsi_max_scsi_id;
|
||||
extern unsigned char scsi_sym53c8xx_ccf;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ATAPI Support (experimental)
|
||||
*/
|
||||
#define CONFIG_ATAPI
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_60X_PCI_IO_OFFSET /* base address */
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
|
||||
|
||||
#define ATA_RESET_TIME (ata_reset_time)
|
||||
|
||||
#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
|
||||
/*
|
||||
* SCSI support (experimental) only SYM53C8xx supported
|
||||
*/
|
||||
#define CONFIG_SCSI_SYM53C8XX
|
||||
#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
|
||||
#define CONFIG_SYS_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (15 * CONFIG_SYS_SCSI_MAX_LUN) /* max. Target devices */
|
||||
#define CONFIG_SYS_SCSI_SPIN_UP_TIME (scsi_reset_time)
|
||||
|
||||
/*
|
||||
* Partion suppport
|
||||
*/
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
/*
|
||||
* Winbond Configuration
|
||||
*/
|
||||
#define CONFIG_WINBOND_83C553 1 /* has a winbond bridge */
|
||||
#define CONFIG_SYS_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
|
||||
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
|
||||
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
|
||||
|
||||
/*
|
||||
* NS87308 Configuration
|
||||
*/
|
||||
#define CONFIG_NS87308 /* Nat Semi super-io cntr on ISA bus */
|
||||
#define CONFIG_SYS_NS87308_BADDR_10 1
|
||||
#define CONFIG_SYS_NS87308_DEVS (CONFIG_SYS_NS87308_UART1 | \
|
||||
CONFIG_SYS_NS87308_UART2 | \
|
||||
CONFIG_SYS_NS87308_KBC1 | \
|
||||
CONFIG_SYS_NS87308_MOUSE | \
|
||||
CONFIG_SYS_NS87308_FDC | \
|
||||
CONFIG_SYS_NS87308_RARP | \
|
||||
CONFIG_SYS_NS87308_GPIO | \
|
||||
CONFIG_SYS_NS87308_POWRMAN | \
|
||||
CONFIG_SYS_NS87308_RTC_APC )
|
||||
|
||||
#define CONFIG_SYS_NS87308_PS2MOD
|
||||
#define CONFIG_SYS_NS87308_GPIO_BASE 0x0220
|
||||
#define CONFIG_SYS_NS87308_PWMAN_BASE 0x0460
|
||||
#define CONFIG_SYS_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
|
||||
|
||||
/*
|
||||
* set up the NVRAM access registers
|
||||
* NVRAM's controlled by the configurable CS line from the 87308
|
||||
*/
|
||||
#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
|
||||
#define CONFIG_SYS_NS87308_CS0_CONF 0x40
|
||||
#define CONFIG_SYS_NS87308_CS1_BASE 0x0070
|
||||
#define CONFIG_SYS_NS87308_CS1_CONF 0x1C
|
||||
#define CONFIG_SYS_NS87308_CS2_BASE 0x0071
|
||||
#define CONFIG_SYS_NS87308_CS2_CONF 0x1C
|
||||
|
||||
#define CONFIG_RTC_MK48T59
|
||||
|
||||
/*
|
||||
* Initial BATs
|
||||
*/
|
||||
#if 1
|
||||
|
||||
#define CONFIG_SYS_IBAT0L 0
|
||||
#define CONFIG_SYS_IBAT0U 0
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
|
||||
|
||||
#define CONFIG_SYS_IBAT1L 0
|
||||
#define CONFIG_SYS_IBAT1U 0
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
|
||||
#define CONFIG_SYS_IBAT2L 0
|
||||
#define CONFIG_SYS_IBAT2U 0
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
#define CONFIG_SYS_IBAT3L 0
|
||||
#define CONFIG_SYS_IBAT3U 0
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
#else
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
|
||||
|
||||
/* address range for flashes */
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
|
||||
/* ISA IO space */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
/* ISA memory space */
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Speed settings are board specific
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long bab7xx_get_bus_freq (void);
|
||||
extern unsigned long bab7xx_get_gclk_freq (void);
|
||||
#endif
|
||||
#define CONFIG_SYS_BUS_CLK bab7xx_get_bus_freq()
|
||||
#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq()
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* L2 Cache Configuration is board specific for BAB740/BAB750
|
||||
* Init values read from revision srom.
|
||||
*/
|
||||
#undef CONFIG_SYS_L2
|
||||
#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
|
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
|
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E)
|
||||
|
||||
#define CONFIG_SYS_L2_BAB7xx
|
||||
|
||||
#define CONFIG_TULIP
|
||||
#define CONFIG_TULIP_SELECT_MEDIA
|
||||
|
||||
#endif /* __CONFIG_H */
|
Loading…
Reference in a new issue