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Ethernut 5 board support

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Add support for the Ethernut 5 open hardware design, based
on Atmel's AT91SAM9XE512 SoC.

V4
 - Fix several coding style issues.
 - Move machine type to config file.
 - Remove use of CONFIG_ATMEL_LEGACY.

Signed-off-by: Tim Schendekehl <tim.schendekehl@egnite.de>
This commit is contained in:
Tim Schendekehl 2011-11-01 23:55:01 +00:00 committed by Albert ARIBAUD
parent 28cb465f78
commit 14c3261497
7 changed files with 1016 additions and 0 deletions
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4
MAINTAINERS
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@ -142,6 +142,10 @@ Phil Edworthy <phil.edworthy@renesas.com>
rsk7264 SH7264
egnite GmbH <info@egnite.de>
ethernut5 ARM926EJS (AT91SAM9XE SoC)
Dirk Eibach <eibach@gdsys.de>
devconcenter PPC460EX

48
board/egnite/ethernut5/Makefile Normal file
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@ -0,0 +1,48 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010
# egnite GmbH
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += $(BOARD)_pwrman.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

270
board/egnite/ethernut5/ethernut5.c Normal file
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/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* (C) Copyright 2010
* Ole Reinhardt <ole.reinhardt@thermotemp.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Ethernut 5 general board support
*
* Ethernut is an open source hardware and software project for
* embedded Ethernet devices. Hardware layouts and CAD files are
* freely available under BSD-like license.
*
* Ethernut 5 is the first member of the Ethernut board family
* with U-Boot and Linux support. This implementation is based
* on the original work done by Ole Reinhardt, but heavily modified
* to support additional features and the latest board revision 5.0F.
*
* Main board components are by default:
*
* Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
* 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
* 512 MBytes Micron MT29F4G08ABADA NAND Flash
* 4 MBytes Atmel AT45DB321D DataFlash
* SMSC LAN8710 Ethernet PHY
* Atmel ATmega168 MCU used for power management
* Linear Technology LTC4411 PoE controller
*
* U-Boot relevant board interfaces are:
*
* 100 Mbit Ethernet with IEEE 802.3af PoE
* RS-232 serial port
* USB host and device
* MMC/SD-Card slot
* Expansion port with I2C, SPI and more...
*
* Typically the U-Boot image is loaded from serial DataFlash into
* SDRAM by the samboot boot loader, which is located in internal
* NOR Flash and provides all essential initializations like CPU
* and peripheral clocks and, of course, the SDRAM configuration.
*
* For testing purposes it is also possibly to directly transfer
* the image into SDRAM via JTAG. A tested configuration exists
* for the Turtelizer 2 hardware dongle and the OpenOCD software.
* In this case the latter will do the basic hardware configuration
* via its reset-init script.
*
* For additional information visit the project home page at
* http://www.ethernut.de/
*/
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <spi.h>
#include <dataflash.h>
#include <mmc.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_spi.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include "ethernut5_pwrman.h"
DECLARE_GLOBAL_DATA_PTR;
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
};
/*
* In fact we have 7 partitions, but u-boot supports 5 only. This is
* no big deal, because the first partition is reserved for applications
* and the last one is used by Nut/OS. Both need not to be visible here.
*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{ 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
{ 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
{ 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
{ 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
{ 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
};
/*
* This is called last during early initialization. Most of the basic
* hardware interfaces are up and running.
*
* The SDRAM hardware has been configured by the first stage boot loader.
* We only need to announce its size, using u-boot's memory check.
*/
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_CMD_NAND
static void ethernut5_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Assign CS3 to NAND/SmartMedia Interface */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
#ifdef CONFIG_SYS_NAND_READY_PIN
/* Ready pin is optional. */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
/*
* This is called first during late initialization.
*/
int board_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable clocks for all PIOs */
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
(1 << ATMEL_ID_PIOC),
&pmc->pcer);
/* Set adress of boot parameters. */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Initialize UARTs and power management. */
at91_seriald_hw_init();
ethernut5_power_init();
#ifdef CONFIG_CMD_NAND
ethernut5_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91_spi0_hw_init(1 << 0);
#endif
return 0;
}
#ifdef CONFIG_MACB
/*
* This is optionally called last during late initialization.
*/
int board_eth_init(bd_t *bis)
{
const char *devname;
unsigned short mode;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable on-chip EMAC clock. */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
/* Need to reset PHY via power management. */
ethernut5_phy_reset();
/* Set peripheral pins. */
at91_macb_hw_init();
/* Basic EMAC initialization. */
if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
return -1;
/*
* Early board revisions have a pull-down at the PHY's MODE0
* strap pin, which forces the PHY into power down. Here we
* switch to all-capable mode.
*/
devname = miiphy_get_current_dev();
if (miiphy_read(devname, 0, 18, &mode) == 0) {
/* Set mode[2:0] to 0b111. */
mode |= 0x00E0;
miiphy_write(devname, 0, 18, mode);
/* Soft reset overrides strap pins. */
miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
}
/* Sync environment with network devices, needed for nfsroot. */
return eth_init(gd->bd);
}
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bd)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable MCI clock. */
writel(1 << ATMEL_ID_MCI, &pmc->pcer);
/* Initialize MCI hardware. */
at91_mci_hw_init();
/* Register the device. */
return atmel_mci_init((void *)ATMEL_BASE_MCI);
}
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
*cd = at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0;
return 0;
}
#endif
#ifdef CONFIG_ATMEL_SPI
/*
* Note, that u-boot uses different code for SPI bus access. While
* memory routines use automatic chip select control, the serial
* flash support requires 'manual' GPIO control. Thus, we switch
* modes.
*/
void spi_cs_activate(struct spi_slave *slave)
{
/* Enable NPCS0 in GPIO mode. This disables peripheral control. */
at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* Disable NPCS0 in GPIO mode. */
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
/* Switch back to peripheral chip select control. */
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
#endif

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board/egnite/ethernut5/ethernut5_pwrman.c Normal file
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/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Ethernut 5 power management support
*
* This board may be supplied via USB, IEEE 802.3af PoE or an
* auxiliary DC input. An on-board ATmega168 microcontroller,
* the so called power management controller or PMC, is used
* to select the supply source and to switch on and off certain
* energy consuming board components. This allows to reduce the
* total stand-by consumption to less than 70mW.
*
* The main CPU communicates with the PMC via I2C. When
* CONFIG_CMD_BSP is defined in the board configuration file,
* then the board specific command 'pwrman' becomes available,
* which allows to manually deal with the PMC.
*
* Two distinct registers are provided by the PMC for enabling
* and disabling specific features. This avoids the often seen
* read-modify-write cycle or shadow register requirement.
* Additional registers are available to query the board
* status and temperature, the auxiliary voltage and to control
* the green user LED that is integrated in the reset switch.
*
* Note, that the AVR firmware of the PMC is released under BSDL.
*
* For additional information visit the project home page at
* http://www.ethernut.de/
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <i2c.h>
#include "ethernut5_pwrman.h"
/* PMC firmware version */
static int pwrman_major;
static int pwrman_minor;
/*
* Enable Ethernut 5 power management.
*
* This function must be called during board initialization.
* While we are using u-boot's I2C subsystem, it may be required
* to enable the serial port before calling this function,
* in particular when debugging is enabled.
*
* If board specific commands are not available, we will activate
* all board components.
*/
void ethernut5_power_init(void)
{
pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS);
pwrman_major = pwrman_minor >> 4;
pwrman_minor &= 15;
#ifndef CONFIG_CMD_BSP
/* Do not modify anything, if we do not have a known version. */
if (pwrman_major == 2) {
/* Without board specific commands we enable all features. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST);
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
}
#endif
}
/*
* Reset Ethernet PHY.
*
* This function allows the re-configure the PHY after
* changing its strap pins.
*/
void ethernut5_phy_reset(void)
{
/* Do not modify anything, if we do not have a known version. */
if (pwrman_major != 2)
return;
/*
* Make sure that the Ethernet clock is enabled and the PHY reset
* is disabled for at least 100 us.
*/
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK);
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
udelay(100);
/*
* LAN8710 strap pins are
* PA14 => PHY MODE0
* PA15 => PHY MODE1
* PA17 => PHY MODE2 => 111b all capable
* PA18 => PHY ADDR0 => 0b
*/
at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
at91_set_pio_input(AT91_PIO_PORTA, 15, 1);
at91_set_pio_input(AT91_PIO_PORTA, 17, 1);
at91_set_pio_input(AT91_PIO_PORTA, 18, 0);
/* Activate PHY reset for 100 us. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST);
udelay(100);
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
}
/*
* Output the firmware version we got during initialization.
*/
void ethernut5_print_version(void)
{
printf("%u.%u\n", pwrman_major, pwrman_minor);
}
/*
* All code below this point is optional and implements
* the 'pwrman' command.
*/
#ifdef CONFIG_CMD_BSP
/* Human readable names of PMC features */
char *pwrman_feat[8] = {
"board", "vbin", "vbout", "mmc",
"rs232", "ethclk", "ethrst", "wakeup"
};
/*
* Print all feature names, that have its related flags enabled.
*/
static void print_flagged_features(u8 flags)
{
int i;
for (i = 0; i < 8; i++) {
if (flags & (1 << i))
printf("%s ", pwrman_feat[i]);
}
}
/*
* Return flags of a given list of feature names.
*
* The function stops at the first unknown list entry and
* returns the number of detected names as a function result.
*/
static int feature_flags(char * const names[], int num, u8 *flags)
{
int i, j;
*flags = 0;
for (i = 0; i < num; i++) {
for (j = 0; j < 8; j++) {
if (strcmp(pwrman_feat[j], names[i]) == 0) {
*flags |= 1 << j;
break;
}
}
if (j > 7)
break;
}
return i;
}
void ethernut5_print_power(void)
{
u8 flags;
int i;
flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA);
for (i = 0; i < 2; i++) {
if (flags) {
print_flagged_features(flags);
printf("%s\n", i ? "off" : "on");
}
flags = ~flags;
}
}
void ethernut5_print_celsius(void)
{
int val;
/* Read ADC value from LM50 and return Celsius degrees. */
val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP);
val *= 5000; /* 100mV/degree with 5V reference */
val += 128; /* 8 bit resolution */
val /= 256;
val -= 450; /* Celsius offset, still x10 */
/* Output full degrees. */
printf("%d\n", (val + 5) / 10);
}
void ethernut5_print_voltage(void)
{
int val;
/* Read ADC value from divider and return voltage. */
val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX);
/* Resistors are 100k and 12.1k */
val += 5;
val *= 180948;
val /= 100000;
val++;
/* Calculation was done in 0.1V units. */
printf("%d\n", (val + 5) / 10);
}
/*
* Process the board specific 'pwrman' command.
*/
int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u8 val;
int i;
if (argc == 1) {
ethernut5_print_power();
} else if (argc == 2 && strcmp(argv[1], "reset") == 0) {
at91_set_pio_output(AT91_PIO_PORTB, 8, 1);
udelay(100);
at91_set_pio_output(AT91_PIO_PORTB, 8, 0);
udelay(100000);
} else if (argc == 2 && strcmp(argv[1], "temp") == 0) {
ethernut5_print_celsius();
} else if (argc == 2 && strcmp(argv[1], "vaux") == 0) {
ethernut5_print_voltage();
} else if (argc == 2 && strcmp(argv[1], "version") == 0) {
ethernut5_print_version();
} else if (strcmp(argv[1], "led") == 0) {
/* Control the green status LED. Blink frequency unit
** is 0.1s, very roughly. */
if (argc == 2) {
/* No more arguments, output current settings. */
val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL);
printf("led %u %u\n", val >> 4, val & 15);
} else {
/* First argument specifies the on-time. */
val = (u8) simple_strtoul(argv[2], NULL, 0);
val <<= 4;
if (argc > 3) {
/* Second argument specifies the off-time. */
val |= (u8) (simple_strtoul(argv[3], NULL, 0)
& 15);
}
/* Update the LED control register. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val);
}
} else {
/* We expect a list of features followed an optional status. */
argc--;
i = feature_flags(&argv[1], argc, &val);
if (argc == i) {
/* We got a list only, print status. */
val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA);
if (val) {
if (i > 1)
print_flagged_features(val);
printf("active\n");
} else {
printf("inactive\n");
}
} else {
/* More arguments. */
if (i == 0) {
/* No given feature, use despensibles. */
val = PWRMAN_DISPENSIBLE;
}
if (strcmp(argv[i + 1], "on") == 0) {
/* Enable features. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA,
val);
} else if (strcmp(argv[i + 1], "off") == 0) {
/* Disable features. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS,
val);
} else {
printf("Bad parameter %s\n", argv[i + 1]);
return 1;
}
}
}
return 0;
}
U_BOOT_CMD(
pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman,
"power management",
"- print settings\n"
"pwrman feature ...\n"
" - print status\n"
"pwrman [feature ...] on|off\n"
" - enable/disable specified or all dispensible features\n"
"pwrman led [on-time [off-time]]\n"
" - print or set led blink timer\n"
"pwrman temp\n"
" - print board temperature (Celsius)\n"
"pwrman vaux\n"
" - print auxiliary input voltage\n"
"pwrman reset\n"
" - reset power management controller\n"
"pwrman version\n"
" - print firmware version\n"
"\n"
" features, (*)=dispensible:\n"
" board - 1.8V and 3.3V supply\n"
" vbin - supply via USB device connector\n"
" vbout - USB host connector supply(*)\n"
" mmc - MMC slot supply(*)\n"
" rs232 - RS232 driver\n"
" ethclk - Ethernet PHY clock(*)\n"
" ethrst - Ethernet PHY reset\n"
" wakeup - RTC alarm"
);
#endif /* CONFIG_CMD_BSP */

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board/egnite/ethernut5/ethernut5_pwrman.h Normal file
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/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Ethernut 5 power management support
*
* For additional information visit the project home page at
* http://www.ethernut.de/
*/
/* I2C address of the PMC */
#define PWRMAN_I2C_ADDR 0x22
/* PMC registers */
#define PWRMAN_REG_VERS 0 /* Version register */
#define PWRMAN_REG_STA 1 /* Feature status register */
#define PWRMAN_REG_ENA 2 /* Feature enable register */
#define PWRMAN_REG_DIS 3 /* Feature disable register */
#define PWRMAN_REG_TEMP 4 /* Board temperature */
#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */
#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */
/* Feature flags used in status, enable and disable registers */
#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */
#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */
#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */
#define PWRMAN_MMC 0x08 /* Memory card supply */
#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */
#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */
#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */
#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */
/* Features, which are not essential to keep u-boot alive */
#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK)
/* Enable Ethernut 5 power management. */
extern void ethernut5_power_init(void);
/* Reset Ethernet PHY. */
extern void ethernut5_phy_reset(void);
extern void ethernut5_print_version(void);
#ifdef CONFIG_CMD_BSP
extern void ethernut5_print_power(void);
extern void ethernut5_print_celsius(void);
extern void ethernut5_print_voltage(void);
#endif

1
boards.cfg
View file

@ -110,6 +110,7 @@ cpu9G20 arm arm926ejs cpu9260 eukrea
cpu9G20_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,NANDBOOT
cpu9G20_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M
cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT
ethernut5 arm arm926ejs ethernut5 egnite at91 ethernut5:AT91SAM9XE
top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000
top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000
meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH

287
include/configs/ethernut5.h Normal file
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@ -0,0 +1,287 @@
/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* Configuation settings for Ethernut 5 with AT91SAM9XE.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/hardware.h>
/* The first stage boot loader expects u-boot running at this address. */
#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
/* The first stage boot loader takes care of low level initialization. */
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Set our official architecture number. */
#define MACH_TYPE_ETHERNUT5 1971
#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
/* CPU information */
#define CONFIG_ARM926EJS
#define CONFIG_AT91FAMILY
#define CONFIG_DISPLAY_CPUINFO /* Display at console. */
#define CONFIG_ARCH_CPU_INIT
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000
#undef CONFIG_USE_IRQ /* Running w/o interrupts */
/* 32kB internal SRAM */
#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
#define CONFIG_SRAM_SIZE (32 << 10)
#define CONFIG_STACKSIZE (CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_STACKSIZE)
/* 128MB SDRAM in 1 bank */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
- CONFIG_SYS_MALLOC_LEN)
/* 512kB on-chip NOR flash */
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
# define CONFIG_AT91_EFLASH
# define CONFIG_SYS_MAX_FLASH_SECT 32
# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
# define CONFIG_EFLASH_PROTSECTORS 1
/* 512kB DataFlash at NPCS0 */
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
#define CONFIG_HAS_DATAFLASH
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x3DE000
#define CONFIG_ENV_SECT_SIZE (132 << 10)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
+ CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
+ 0x042000)
/* SPI */
#define CONFIG_ATMEL_SPI
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
#define AT91_SPI_CLK 15000000
/* Serial port */
#define CONFIG_ATMEL_USART
#define CONFIG_USART3 /* USART 3 is DBGU */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/* Misc. hardware drivers */
#define CONFIG_AT91_GPIO
/* Command line configuration */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SPI
#ifdef MINIMAL_LOADER
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#else
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DNS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PING
#define CONFIG_CMD_RARP
#define CONFIG_CMD_REISER
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SF
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_USB
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_NAND_ATMEL
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#endif
/* JFFS2 */
#ifdef CONFIG_CMD_JFFS2
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_NAND
#endif
/* Ethernet */
#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_PHY_ID 0
#define CONFIG_MACB_SEARCH_PHY
/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#endif
/* RTC */
#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
#endif
/* I2C */
#define CONFIG_SYS_MAX_I2C_BUS 1
#define CONFIG_SYS_I2C_SLAVE 0
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SOFT_I2C
#define I2C_SOFT_DECLARATIONS
#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
#define I2C_INIT { \
at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
}
#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
#define I2C_DELAY udelay(100)
#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
/* DHCP/BOOTP options */
#ifdef CONFIG_CMD_DHCP
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_SYS_AUTOLOAD "n"
#endif
/* File systems */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
#define MTDIDS_DEFAULT "nand0=atmel_nand"
#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
#endif
#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_LZO
#define CONFIG_RBTREE
/* Boot command */
#define CONFIG_BOOTDELAY 3
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
#if defined(CONFIG_CMD_NAND)
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
MTDPARTS_DEFAULT \
" rw rootfstype=jffs2"
#endif
/* Misc. u-boot settings */
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
+ sizeof(CONFIG_SYS_PROMPT))
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#endif