mirror of
https://github.com/AsahiLinux/u-boot
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mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
396abba261
commit
1f5cb79374
1 changed files with 141 additions and 82 deletions
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@ -101,12 +101,13 @@
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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/* + 256M */
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#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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@ -131,24 +132,26 @@
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#if defined(CONFIG_DDR_II)
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#define CONFIG_SYS_DDRCDR 0x80080001
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
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#define CONFIG_SYS_DDR_TIMING_0 0x00220802
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#define CONFIG_SYS_DDR_TIMING_1 0x38357322
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#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
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#define CONFIG_SYS_DDR_TIMING_0 0x00220802
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#define CONFIG_SYS_DDR_TIMING_1 0x38357322
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#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
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#define CONFIG_SYS_DDR_MODE 0x47d00432
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
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#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#else
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_9)
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#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
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#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
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#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
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#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
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#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
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#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
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#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
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#endif
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#endif
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@ -173,8 +176,8 @@
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#endif
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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@ -182,34 +185,42 @@
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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| OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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@ -219,11 +230,13 @@
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/*
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* BCSR on the Local Bus
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*/
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#define CONFIG_SYS_BCSR 0xF8000000
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
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#define CONFIG_SYS_BCSR 0xF8000000
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/* Access window base at BCSR base */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
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/* Port size=8bit, MSEL=GPCM */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
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#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
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/*
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@ -271,8 +284,10 @@
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#define CONFIG_SYS_OR2 0xfc006901
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#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
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@ -315,7 +330,7 @@
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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@ -419,11 +434,12 @@
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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@ -476,17 +492,19 @@
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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/*
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* Core HID Setup
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@ -503,54 +521,94 @@
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR/LBC SDRAM: cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
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| BATU_BL_4M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* BCSR: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
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| BATU_BL_32M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/* DDR/LBC SDRAM next 256M: cacheable */
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#ifdef CONFIG_PCI
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/* PCI MEM space: cacheable */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#else
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@ -588,30 +646,31 @@
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskfile=ramfs.83xx\0" \
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"fdtaddr=780000\0" \
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"fdtfile=mpc836x_mds.dtb\0" \
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""
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskfile=ramfs.83xx\0" \
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"fdtaddr=780000\0" \
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"fdtfile=mpc836x_mds.dtb\0" \
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
||||
"$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||
|
|
|
|||
Loading…
Reference in a new issue