2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-11-25 00:18:02 +00:00
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
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#define __ASM_ARCH_MX6_IMX_REGS_H__
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2012-08-13 07:27:58 +00:00
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#define ARCH_MXC
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2011-11-25 00:18:02 +00:00
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#define ROMCP_ARB_BASE_ADDR 0x00000000
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#define ROMCP_ARB_END_ADDR 0x000FFFFF
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2013-04-10 09:32:57 +00:00
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#ifdef CONFIG_MX6SL
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#define GPU_2D_ARB_BASE_ADDR 0x02200000
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#define GPU_2D_ARB_END_ADDR 0x02203FFF
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#define OPENVG_ARB_BASE_ADDR 0x02204000
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#define OPENVG_ARB_END_ADDR 0x02207FFF
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2018-01-03 14:33:05 +00:00
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#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
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2014-06-24 20:40:58 +00:00
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#define CAAM_ARB_BASE_ADDR 0x00100000
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#define CAAM_ARB_END_ADDR 0x00107FFF
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#define GPU_ARB_BASE_ADDR 0x01800000
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#define GPU_ARB_END_ADDR 0x01803FFF
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#define APBH_DMA_ARB_BASE_ADDR 0x01804000
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#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
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#define M4_BOOTROM_BASE_ADDR 0x007F8000
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2016-12-11 11:24:22 +00:00
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#elif !defined(CONFIG_MX6SLL)
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2011-11-25 00:18:02 +00:00
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#define CAAM_ARB_BASE_ADDR 0x00100000
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#define CAAM_ARB_END_ADDR 0x00103FFF
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#define APBH_DMA_ARB_BASE_ADDR 0x00110000
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#define APBH_DMA_ARB_END_ADDR 0x00117FFF
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#define HDMI_ARB_BASE_ADDR 0x00120000
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#define HDMI_ARB_END_ADDR 0x00128FFF
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#define GPU_3D_ARB_BASE_ADDR 0x00130000
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#define GPU_3D_ARB_END_ADDR 0x00133FFF
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#define GPU_2D_ARB_BASE_ADDR 0x00134000
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#define GPU_2D_ARB_END_ADDR 0x00137FFF
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#define DTCP_ARB_BASE_ADDR 0x00138000
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#define DTCP_ARB_END_ADDR 0x0013BFFF
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2013-04-10 09:32:57 +00:00
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#endif /* CONFIG_MX6SL */
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2013-04-09 21:06:09 +00:00
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#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
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#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
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#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
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2011-11-25 00:18:02 +00:00
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/* GPV - PL301 configuration ports */
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2018-01-03 14:33:05 +00:00
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#if (defined(CONFIG_MX6SX) || \
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defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
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2016-12-11 11:24:22 +00:00
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defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
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2013-04-10 09:32:57 +00:00
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#define GPV2_BASE_ADDR 0x00D00000
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2014-06-24 20:40:58 +00:00
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#define GPV3_BASE_ADDR 0x00E00000
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#define GPV4_BASE_ADDR 0x00F00000
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#define GPV5_BASE_ADDR 0x01000000
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#define GPV6_BASE_ADDR 0x01100000
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#define PCIE_ARB_BASE_ADDR 0x08000000
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#define PCIE_ARB_END_ADDR 0x08FFFFFF
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#else
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2016-12-11 11:24:22 +00:00
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#define GPV2_BASE_ADDR 0x00200000
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2011-11-25 00:18:02 +00:00
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#define GPV3_BASE_ADDR 0x00300000
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#define GPV4_BASE_ADDR 0x00800000
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2014-06-24 20:40:58 +00:00
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#define PCIE_ARB_BASE_ADDR 0x01000000
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#define PCIE_ARB_END_ADDR 0x01FFFFFF
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#endif
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2011-11-25 00:18:02 +00:00
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#define IRAM_BASE_ADDR 0x00900000
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#define SCU_BASE_ADDR 0x00A00000
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#define IC_INTERFACES_BASE_ADDR 0x00A00100
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#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
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#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
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#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
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2014-01-29 19:39:49 +00:00
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#define L2_PL310_BASE 0x00A02000
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2011-11-25 00:18:02 +00:00
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#define GPV0_BASE_ADDR 0x00B00000
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#define GPV1_BASE_ADDR 0x00C00000
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#define AIPS1_ARB_BASE_ADDR 0x02000000
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#define AIPS1_ARB_END_ADDR 0x020FFFFF
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#define AIPS2_ARB_BASE_ADDR 0x02100000
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#define AIPS2_ARB_END_ADDR 0x021FFFFF
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2015-07-20 11:28:23 +00:00
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/* AIPS3 only on i.MX6SX */
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2015-01-14 09:18:12 +00:00
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#define AIPS3_ARB_BASE_ADDR 0x02200000
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#define AIPS3_ARB_END_ADDR 0x022FFFFF
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2015-07-20 11:28:23 +00:00
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#ifdef CONFIG_MX6SX
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2014-06-24 20:40:58 +00:00
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#define WEIM_ARB_BASE_ADDR 0x50000000
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#define WEIM_ARB_END_ADDR 0x57FFFFFF
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2014-12-31 03:01:38 +00:00
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#define QSPI0_AMBA_BASE 0x60000000
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#define QSPI0_AMBA_END 0x6FFFFFFF
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#define QSPI1_AMBA_BASE 0x70000000
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#define QSPI1_AMBA_END 0x7FFFFFFF
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2018-01-03 14:33:05 +00:00
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#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
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2015-07-20 11:28:23 +00:00
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#define WEIM_ARB_BASE_ADDR 0x50000000
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#define WEIM_ARB_END_ADDR 0x57FFFFFF
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#define QSPI0_AMBA_BASE 0x60000000
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#define QSPI0_AMBA_END 0x6FFFFFFF
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2016-12-11 11:24:22 +00:00
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#elif !defined(CONFIG_MX6SLL)
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2011-11-25 00:18:02 +00:00
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#define SATA_ARB_BASE_ADDR 0x02200000
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#define SATA_ARB_END_ADDR 0x02203FFF
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#define OPENVG_ARB_BASE_ADDR 0x02204000
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#define OPENVG_ARB_END_ADDR 0x02207FFF
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#define HSI_ARB_BASE_ADDR 0x02208000
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#define HSI_ARB_END_ADDR 0x0220BFFF
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#define IPU1_ARB_BASE_ADDR 0x02400000
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#define IPU1_ARB_END_ADDR 0x027FFFFF
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#define IPU2_ARB_BASE_ADDR 0x02800000
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#define IPU2_ARB_END_ADDR 0x02BFFFFF
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#define WEIM_ARB_BASE_ADDR 0x08000000
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#define WEIM_ARB_END_ADDR 0x0FFFFFFF
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2014-06-24 20:40:58 +00:00
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#endif
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2011-11-25 00:18:02 +00:00
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2016-12-11 11:24:22 +00:00
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#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
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2018-01-03 14:33:05 +00:00
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defined(CONFIG_MX6SX) || \
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defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
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2013-04-10 09:32:57 +00:00
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#define MMDC0_ARB_BASE_ADDR 0x80000000
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#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
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#define MMDC1_ARB_BASE_ADDR 0xC0000000
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#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
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#else
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2011-11-25 00:18:02 +00:00
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#define MMDC0_ARB_BASE_ADDR 0x10000000
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#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
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#define MMDC1_ARB_BASE_ADDR 0x80000000
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#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
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2013-04-10 09:32:57 +00:00
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#endif
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2011-11-25 00:18:02 +00:00
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2014-06-24 20:40:58 +00:00
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#ifndef CONFIG_MX6SX
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2012-05-31 07:23:55 +00:00
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#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
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#define IPU_SOC_OFFSET 0x00200000
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2014-06-24 20:40:58 +00:00
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#endif
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2012-05-31 07:23:55 +00:00
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2011-11-25 00:18:02 +00:00
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/* Defines for Blocks connected via AIPS (SkyBlue) */
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#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
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#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
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2015-09-02 18:54:15 +00:00
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#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
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2011-11-25 00:18:02 +00:00
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#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
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#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
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2015-09-02 18:54:15 +00:00
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#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
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2011-11-25 00:18:02 +00:00
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#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
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#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
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#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
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#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
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#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
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2016-12-11 11:24:22 +00:00
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#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
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2014-06-24 20:40:58 +00:00
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#ifndef CONFIG_MX6SX
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2011-11-25 00:18:02 +00:00
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#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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2014-06-24 20:40:58 +00:00
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#endif
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2016-12-11 11:24:22 +00:00
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#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
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2011-11-25 00:18:02 +00:00
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#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
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#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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2016-02-10 10:41:25 +00:00
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#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
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2011-11-25 00:18:02 +00:00
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#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
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#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
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#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
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#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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2013-04-10 09:32:57 +00:00
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2014-06-24 20:40:58 +00:00
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#ifndef CONFIG_MX6SX
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2011-11-25 00:18:02 +00:00
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#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
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#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
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2014-06-24 20:40:58 +00:00
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#endif
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2011-11-25 00:18:02 +00:00
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#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
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#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
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#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
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#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
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#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
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#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
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#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
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#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
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2016-12-11 11:24:22 +00:00
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/* QOSC on i.MX6SLL */
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#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
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2011-11-25 00:18:02 +00:00
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#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
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#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
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#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
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#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
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#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
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#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
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2016-08-11 06:02:51 +00:00
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#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
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2011-11-25 00:18:02 +00:00
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#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
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#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
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#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
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#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
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#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
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2012-02-08 22:33:25 +00:00
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#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
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#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
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#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
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2011-11-25 00:18:02 +00:00
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#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
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#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
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#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
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#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
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#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
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#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
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#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
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2016-12-11 11:24:22 +00:00
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#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
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#ifdef CONFIG_MX6SLL
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#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
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#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
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#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
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#elif defined(CONFIG_MX6SL)
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2013-04-10 09:32:57 +00:00
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#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
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#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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2016-12-11 11:24:22 +00:00
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#elif defined(CONFIG_MX6SX)
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2014-06-24 20:40:58 +00:00
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#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
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#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
|
|
|
|
|
#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
|
|
|
|
|
#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
|
2013-04-10 09:32:57 +00:00
|
|
|
#else
|
2011-11-25 00:18:02 +00:00
|
|
|
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
|
|
|
|
|
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
|
|
|
|
|
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
|
2013-04-10 09:32:57 +00:00
|
|
|
#endif
|
2011-11-25 00:18:02 +00:00
|
|
|
|
2016-12-11 11:24:22 +00:00
|
|
|
#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
|
|
|
|
|
#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
|
|
|
|
|
|
2011-11-25 00:18:02 +00:00
|
|
|
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
|
|
|
|
|
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
|
2015-09-02 18:54:15 +00:00
|
|
|
#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
|
|
|
|
|
#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
|
2018-01-11 14:14:17 +00:00
|
|
|
#if defined(CONFIG_MX6UL)
|
|
|
|
|
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
|
|
|
|
|
#else
|
2011-11-25 00:18:02 +00:00
|
|
|
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
|
2018-01-11 14:14:17 +00:00
|
|
|
#endif
|
2011-11-25 00:18:02 +00:00
|
|
|
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
|
2015-02-27 17:22:06 +00:00
|
|
|
|
2016-04-29 12:17:58 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_OFFSET 0
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
|
|
|
|
|
CONFIG_SYS_FSL_SEC_OFFSET)
|
|
|
|
|
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
|
|
|
|
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
|
|
|
|
|
CONFIG_SYS_FSL_JR0_OFFSET)
|
|
|
|
|
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
2015-02-27 17:22:06 +00:00
|
|
|
|
2014-09-15 09:23:14 +00:00
|
|
|
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
|
|
|
|
|
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
|
2013-04-10 09:32:57 +00:00
|
|
|
|
2011-11-25 00:18:02 +00:00
|
|
|
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
|
2013-04-10 09:32:57 +00:00
|
|
|
#ifdef CONFIG_MX6SL
|
|
|
|
|
#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
|
|
|
|
|
#else
|
2011-11-25 00:18:02 +00:00
|
|
|
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
|
2013-04-10 09:32:57 +00:00
|
|
|
#endif
|
|
|
|
|
|
2011-11-25 00:18:02 +00:00
|
|
|
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
|
|
|
|
|
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
|
|
|
|
|
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
|
|
|
|
|
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
|
|
|
|
|
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
|
|
|
|
|
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
|
|
|
|
|
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
|
|
|
|
|
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
|
|
|
|
|
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
|
2016-12-11 11:24:22 +00:00
|
|
|
/* i.MX6SL/SLL */
|
2013-04-10 09:32:57 +00:00
|
|
|
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
|
2018-01-03 14:33:05 +00:00
|
|
|
#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
|
2015-07-20 11:28:23 +00:00
|
|
|
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
|
2013-04-10 09:32:57 +00:00
|
|
|
#else
|
2015-07-20 11:28:23 +00:00
|
|
|
/* i.MX6SX */
|
|
|
|
|
#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
|
2013-04-10 09:32:57 +00:00
|
|
|
#endif
|
2015-07-20 11:28:23 +00:00
|
|
|
/* i.MX6DQ/SDL */
|
|
|
|
|
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
|
2013-04-10 09:32:57 +00:00
|
|
|
|
2011-11-25 00:18:02 +00:00
|
|
|
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
|
|
|
|
|
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
|
|
|
|
|
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
|
2016-12-11 11:24:22 +00:00
|
|
|
#ifdef CONFIG_MX6SLL
|
|
|
|
|
#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
|
|
|
|
|
#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
|
|
|
|
|
#endif
|
2011-11-25 00:18:02 +00:00
|
|
|
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
|
|
|
|
|
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
|
2015-10-29 07:54:45 +00:00
|
|
|
#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
|
2016-08-11 06:02:48 +00:00
|
|
|
#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
|
2014-06-24 20:40:58 +00:00
|
|
|
#ifdef CONFIG_MX6SX
|
|
|
|
|
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
|
|
|
|
|
#else
|
2011-11-25 00:18:02 +00:00
|
|
|
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
|
2014-06-24 20:40:58 +00:00
|
|
|
#endif
|
2011-11-25 00:18:02 +00:00
|
|
|
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
|
2018-01-03 14:33:05 +00:00
|
|
|
#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
|
2018-01-05 14:08:19 +00:00
|
|
|
#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
|
2015-07-20 11:28:23 +00:00
|
|
|
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
|
2016-04-18 12:56:15 +00:00
|
|
|
#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
|
2015-07-20 11:28:23 +00:00
|
|
|
#elif defined(CONFIG_MX6SX)
|
2014-06-24 20:40:58 +00:00
|
|
|
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
|
2011-11-25 00:18:02 +00:00
|
|
|
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
|
2014-06-24 20:40:58 +00:00
|
|
|
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
|
2014-12-31 03:01:38 +00:00
|
|
|
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
|
|
|
|
|
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
|
2014-06-24 20:40:58 +00:00
|
|
|
#else
|
2015-07-20 11:28:23 +00:00
|
|
|
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
|
2011-11-25 00:18:02 +00:00
|
|
|
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
|
|
|
|
|
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
|
|
|
|
|
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
|
2014-06-24 20:40:58 +00:00
|
|
|
#endif
|
2015-07-20 11:28:23 +00:00
|
|
|
#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
|
2011-11-25 00:18:02 +00:00
|
|
|
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
|
|
|
|
|
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
|
|
|
|
|
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
|
|
|
|
|
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
|
2015-05-18 08:56:24 +00:00
|
|
|
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
|
2011-11-25 00:18:02 +00:00
|
|
|
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
|
|
|
|
|
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
|
2016-12-11 11:24:22 +00:00
|
|
|
/* i.MX6SLL */
|
|
|
|
|
#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
|
2011-11-25 00:18:02 +00:00
|
|
|
|
2014-06-24 20:40:58 +00:00
|
|
|
#ifdef CONFIG_MX6SX
|
|
|
|
|
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
|
|
|
|
|
#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
|
|
|
|
|
#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
|
|
|
|
|
#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
|
|
|
|
|
#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
|
|
|
|
|
#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
|
|
|
|
|
#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
|
|
|
|
|
#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
|
|
|
|
|
#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
|
|
|
|
|
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
|
|
|
|
|
#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
|
|
|
|
|
#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
|
|
|
|
|
#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
|
|
|
|
|
#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
|
|
|
|
|
#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
|
|
|
|
|
#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
|
|
|
|
|
#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
|
|
|
|
|
#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
|
|
|
|
|
#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
|
|
|
|
|
#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
|
|
|
|
|
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
|
|
|
|
|
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
|
2018-01-03 14:33:05 +00:00
|
|
|
#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
|
2016-08-11 06:02:48 +00:00
|
|
|
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
|
|
|
|
|
#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
|
|
|
|
|
#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
|
|
|
|
|
#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
|
|
|
|
|
#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
|
|
|
|
|
#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
|
|
|
|
|
#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
|
2014-06-24 20:40:58 +00:00
|
|
|
#endif
|
2017-10-14 12:17:54 +00:00
|
|
|
|
|
|
|
|
#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
|
|
|
|
|
|
2015-10-29 07:54:45 +00:00
|
|
|
/* Only for i.MX6SX */
|
|
|
|
|
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
|
|
|
|
|
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
|
2015-07-20 11:28:23 +00:00
|
|
|
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
|
|
|
|
|
|
2018-01-03 14:33:05 +00:00
|
|
|
#if !(defined(CONFIG_MX6SX) || \
|
|
|
|
|
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
|
2016-12-11 11:24:22 +00:00
|
|
|
defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
|
2011-11-25 00:18:02 +00:00
|
|
|
#define IRAM_SIZE 0x00040000
|
2014-06-24 20:40:58 +00:00
|
|
|
#else
|
|
|
|
|
#define IRAM_SIZE 0x00020000
|
|
|
|
|
#endif
|
2012-02-07 14:08:46 +00:00
|
|
|
#define FEC_QUIRK_ENET_MAC
|
2011-11-25 00:18:02 +00:00
|
|
|
|
2017-06-29 08:16:06 +00:00
|
|
|
#include <asm/mach-imx/regs-lcdif.h>
|
2011-11-25 00:18:02 +00:00
|
|
|
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
|
|
|
|
#include <asm/types.h>
|
2020-05-10 17:40:13 +00:00
|
|
|
#include <linux/bitops.h>
|
2011-11-25 00:18:02 +00:00
|
|
|
|
2015-10-29 07:54:45 +00:00
|
|
|
/* only for i.MX6SX/UL */
|
2017-11-23 11:18:53 +00:00
|
|
|
#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
|
2015-11-30 08:04:51 +00:00
|
|
|
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
|
2016-12-11 11:24:22 +00:00
|
|
|
#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
|
|
|
|
|
MX6SLL_LCDIF_BASE_ADDR : \
|
|
|
|
|
(is_cpu_type(MXC_CPU_MX6SL)) ? \
|
|
|
|
|
MX6SL_LCDIF_BASE_ADDR : \
|
|
|
|
|
((is_cpu_type(MXC_CPU_MX6UL)) ? \
|
2016-08-11 06:02:48 +00:00
|
|
|
MX6UL_LCDIF1_BASE_ADDR : \
|
|
|
|
|
((is_mx6ull()) ? \
|
2016-12-11 11:24:22 +00:00
|
|
|
MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
|
2015-10-29 07:54:45 +00:00
|
|
|
|
|
|
|
|
|
2011-12-20 05:46:31 +00:00
|
|
|
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
|
2011-11-25 00:18:02 +00:00
|
|
|
|
2014-07-26 18:35:43 +00:00
|
|
|
#define SRC_SCR_CORE_1_RESET_OFFSET 14
|
|
|
|
|
#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
|
|
|
|
|
#define SRC_SCR_CORE_2_RESET_OFFSET 15
|
|
|
|
|
#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
|
|
|
|
|
#define SRC_SCR_CORE_3_RESET_OFFSET 16
|
|
|
|
|
#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
|
|
|
|
|
#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
|
|
|
|
|
#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
|
|
|
|
|
#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
|
|
|
|
|
#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
|
|
|
|
|
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
|
|
|
|
|
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
|
|
|
|
|
|
2016-01-28 08:54:59 +00:00
|
|
|
struct rdc_regs {
|
|
|
|
|
u32 vir; /* Version information */
|
|
|
|
|
u32 reserved1[8];
|
|
|
|
|
u32 stat; /* Status */
|
|
|
|
|
u32 intctrl; /* Interrupt and Control */
|
|
|
|
|
u32 intstat; /* Interrupt Status */
|
|
|
|
|
u32 reserved2[116];
|
|
|
|
|
u32 mda[32]; /* Master Domain Assignment */
|
|
|
|
|
u32 reserved3[96];
|
|
|
|
|
u32 pdap[104]; /* Peripheral Domain Access Permissions */
|
|
|
|
|
u32 reserved4[88];
|
|
|
|
|
struct {
|
|
|
|
|
u32 mrsa; /* Memory Region Start Address */
|
|
|
|
|
u32 mrea; /* Memory Region End Address */
|
|
|
|
|
u32 mrc; /* Memory Region Control */
|
|
|
|
|
u32 mrvs; /* Memory Region Violation Status */
|
|
|
|
|
} mem_region[55];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct rdc_sema_regs {
|
|
|
|
|
u8 gate[64]; /* Gate */
|
|
|
|
|
u16 rstgt; /* Reset Gate */
|
|
|
|
|
};
|
|
|
|
|
|
2014-11-14 13:27:22 +00:00
|
|
|
/* WEIM registers */
|
|
|
|
|
struct weim {
|
|
|
|
|
u32 cs0gcr1;
|
|
|
|
|
u32 cs0gcr2;
|
|
|
|
|
u32 cs0rcr1;
|
|
|
|
|
u32 cs0rcr2;
|
|
|
|
|
u32 cs0wcr1;
|
|
|
|
|
u32 cs0wcr2;
|
|
|
|
|
|
|
|
|
|
u32 cs1gcr1;
|
|
|
|
|
u32 cs1gcr2;
|
|
|
|
|
u32 cs1rcr1;
|
|
|
|
|
u32 cs1rcr2;
|
|
|
|
|
u32 cs1wcr1;
|
|
|
|
|
u32 cs1wcr2;
|
|
|
|
|
|
|
|
|
|
u32 cs2gcr1;
|
|
|
|
|
u32 cs2gcr2;
|
|
|
|
|
u32 cs2rcr1;
|
|
|
|
|
u32 cs2rcr2;
|
|
|
|
|
u32 cs2wcr1;
|
|
|
|
|
u32 cs2wcr2;
|
|
|
|
|
|
|
|
|
|
u32 cs3gcr1;
|
|
|
|
|
u32 cs3gcr2;
|
|
|
|
|
u32 cs3rcr1;
|
|
|
|
|
u32 cs3rcr2;
|
|
|
|
|
u32 cs3wcr1;
|
|
|
|
|
u32 cs3wcr2;
|
|
|
|
|
|
|
|
|
|
u32 unused[12];
|
|
|
|
|
|
|
|
|
|
u32 wcr;
|
|
|
|
|
u32 wiar;
|
|
|
|
|
u32 ear;
|
|
|
|
|
};
|
|
|
|
|
|
2011-11-25 00:18:02 +00:00
|
|
|
/* System Reset Controller (SRC) */
|
|
|
|
|
struct src {
|
|
|
|
|
u32 scr;
|
|
|
|
|
u32 sbmr1;
|
|
|
|
|
u32 srsr;
|
|
|
|
|
u32 reserved1[2];
|
|
|
|
|
u32 sisr;
|
|
|
|
|
u32 simr;
|
|
|
|
|
u32 sbmr2;
|
|
|
|
|
u32 gpr1;
|
|
|
|
|
u32 gpr2;
|
|
|
|
|
u32 gpr3;
|
|
|
|
|
u32 gpr4;
|
|
|
|
|
u32 gpr5;
|
|
|
|
|
u32 gpr6;
|
|
|
|
|
u32 gpr7;
|
|
|
|
|
u32 gpr8;
|
|
|
|
|
u32 gpr9;
|
|
|
|
|
u32 gpr10;
|
|
|
|
|
};
|
|
|
|
|
|
2017-02-24 10:15:15 +00:00
|
|
|
#define src_base ((struct src *)SRC_BASE_ADDR)
|
|
|
|
|
|
2018-01-10 05:20:32 +00:00
|
|
|
#define SRC_M4_REG_OFFSET 0
|
|
|
|
|
#define SRC_M4_ENABLE_OFFSET 22
|
|
|
|
|
#define SRC_M4_ENABLE_MASK BIT(22)
|
|
|
|
|
#define SRC_M4C_NON_SCLR_RST_OFFSET 4
|
|
|
|
|
#define SRC_M4C_NON_SCLR_RST_MASK BIT(4)
|
2016-01-28 08:55:05 +00:00
|
|
|
|
2014-01-03 17:55:58 +00:00
|
|
|
/* GPR1 bitfields */
|
2015-09-25 10:31:48 +00:00
|
|
|
#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
|
|
|
|
|
#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
|
|
|
|
|
#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
|
|
|
|
|
#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
|
|
|
|
|
#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
|
|
|
|
|
#define IOMUXC_GPR1_DPI_OFF BIT(24)
|
|
|
|
|
#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
|
2014-01-03 17:55:58 +00:00
|
|
|
#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
|
|
|
|
|
#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
|
2015-09-25 10:31:48 +00:00
|
|
|
#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
|
|
|
|
|
#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
|
|
|
|
|
#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
|
|
|
|
|
#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
|
|
|
|
|
#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
|
|
|
|
|
#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
|
|
|
|
|
#define IOMUXC_GPR1_PCIE_INT BIT(14)
|
2014-07-18 04:07:17 +00:00
|
|
|
#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
|
|
|
|
|
#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
|
2015-09-25 10:31:48 +00:00
|
|
|
#define IOMUXC_GPR1_GINT BIT(12)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
|
|
|
|
|
#define IOMUXC_GPR1_ACT_CS3 BIT(9)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
|
|
|
|
|
#define IOMUXC_GPR1_ACT_CS2 BIT(6)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
|
|
|
|
|
#define IOMUXC_GPR1_ACT_CS1 BIT(3)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
|
|
|
|
|
#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
|
|
|
|
|
#define IOMUXC_GPR1_ACT_CS0 BIT(0)
|
2014-01-03 17:55:58 +00:00
|
|
|
|
2012-09-21 11:41:42 +00:00
|
|
|
/* GPR3 bitfields */
|
|
|
|
|
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
|
|
|
|
|
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
|
|
|
|
|
#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
|
|
|
|
|
#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
|
|
|
|
|
#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
|
|
|
|
|
#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
|
|
|
|
|
#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
|
|
|
|
|
#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
|
|
|
|
|
#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
|
|
|
|
|
#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
|
|
|
|
|
#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
|
|
|
|
|
#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
|
|
|
|
|
#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
|
|
|
|
|
#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
|
|
|
|
|
#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
|
|
|
|
|
#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
|
|
|
|
|
#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
|
|
|
|
|
#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
|
|
|
|
|
#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
|
|
|
|
|
#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
|
|
|
|
|
#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
|
|
|
|
|
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
|
|
|
|
|
|
2015-09-25 10:31:48 +00:00
|
|
|
/* gpr12 bitfields */
|
|
|
|
|
#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
|
|
|
|
|
#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
|
|
|
|
|
#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
|
|
|
|
|
#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
|
|
|
|
|
#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
|
|
|
|
|
#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
|
|
|
|
|
#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
|
2012-09-21 11:41:42 +00:00
|
|
|
|
2012-09-19 08:32:31 +00:00
|
|
|
struct iomuxc {
|
2018-01-03 14:33:05 +00:00
|
|
|
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
|
2014-07-09 20:59:55 +00:00
|
|
|
u8 reserved[0x4000];
|
|
|
|
|
#endif
|
2012-09-19 08:32:31 +00:00
|
|
|
u32 gpr[14];
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-25 17:26:44 +00:00
|
|
|
struct gpc {
|
|
|
|
|
u32 cntr;
|
|
|
|
|
u32 pgr;
|
|
|
|
|
u32 imr1;
|
|
|
|
|
u32 imr2;
|
|
|
|
|
u32 imr3;
|
|
|
|
|
u32 imr4;
|
|
|
|
|
u32 isr1;
|
|
|
|
|
u32 isr2;
|
|
|
|
|
u32 isr3;
|
|
|
|
|
u32 isr4;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-19 08:32:31 +00:00
|
|
|
#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
|
|
|
|
|
#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
|
|
|
|
|
#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
|
|
|
|
|
#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
|
|
|
|
|
#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
|
|
|
|
|
#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_BITMAP_SPWG 0
|
|
|
|
|
#define IOMUXC_GPR2_BITMAP_JEIDA 1
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_18 0
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_24 1
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
|
|
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
|
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|
|
#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
|
|
|
|
|
#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
|
|
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|
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|
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|
|
#define IOMUXC_GPR2_MODE_DISABLED 0
|
|
|
|
|
#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
|
2013-06-19 09:16:13 +00:00
|
|
|
#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
|
2012-09-19 08:32:31 +00:00
|
|
|
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
|
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|
|
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
|
|
|
|
|
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
|
|
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|
|
|
2012-01-31 07:52:04 +00:00
|
|
|
/* ECSPI registers */
|
|
|
|
|
struct cspi_regs {
|
|
|
|
|
u32 rxdata;
|
|
|
|
|
u32 txdata;
|
|
|
|
|
u32 ctrl;
|
|
|
|
|
u32 cfg;
|
|
|
|
|
u32 intr;
|
|
|
|
|
u32 dma;
|
|
|
|
|
u32 stat;
|
|
|
|
|
u32 period;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CSPI register definitions
|
|
|
|
|
*/
|
|
|
|
|
#define MXC_ECSPI
|
|
|
|
|
#define MXC_CSPICTRL_EN (1 << 0)
|
|
|
|
|
#define MXC_CSPICTRL_MODE (1 << 1)
|
|
|
|
|
#define MXC_CSPICTRL_XCH (1 << 2)
|
2013-04-09 13:06:25 +00:00
|
|
|
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
|
2012-01-31 07:52:04 +00:00
|
|
|
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
|
|
|
|
|
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
|
|
|
|
|
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
|
|
|
|
|
#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
|
|
|
|
|
#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
|
|
|
|
|
#define MXC_CSPICTRL_MAXBITS 0xfff
|
|
|
|
|
#define MXC_CSPICTRL_TC (1 << 7)
|
|
|
|
|
#define MXC_CSPICTRL_RXOVF (1 << 6)
|
|
|
|
|
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
|
|
|
|
|
#define MAX_SPI_BYTES 32
|
2014-07-18 04:07:20 +00:00
|
|
|
#define SPI_MAX_NUM 4
|
2012-01-31 07:52:04 +00:00
|
|
|
|
|
|
|
|
/* Bit position inside CTRL register to be associated with SS */
|
|
|
|
|
#define MXC_CSPICTRL_CHAN 18
|
|
|
|
|
|
|
|
|
|
/* Bit position inside CON register to be associated with SS */
|
2014-02-17 16:33:16 +00:00
|
|
|
#define MXC_CSPICON_PHA 0 /* SCLK phase control */
|
|
|
|
|
#define MXC_CSPICON_POL 4 /* SCLK polarity */
|
|
|
|
|
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
|
|
|
|
|
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
|
2016-12-11 11:24:22 +00:00
|
|
|
#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
|
2018-01-03 14:33:05 +00:00
|
|
|
defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
|
2013-04-10 09:32:57 +00:00
|
|
|
#define MXC_SPI_BASE_ADDRESSES \
|
|
|
|
|
ECSPI1_BASE_ADDR, \
|
|
|
|
|
ECSPI2_BASE_ADDR, \
|
|
|
|
|
ECSPI3_BASE_ADDR, \
|
|
|
|
|
ECSPI4_BASE_ADDR
|
|
|
|
|
#else
|
2012-01-31 07:52:04 +00:00
|
|
|
#define MXC_SPI_BASE_ADDRESSES \
|
|
|
|
|
ECSPI1_BASE_ADDR, \
|
|
|
|
|
ECSPI2_BASE_ADDR, \
|
|
|
|
|
ECSPI3_BASE_ADDR, \
|
|
|
|
|
ECSPI4_BASE_ADDR, \
|
|
|
|
|
ECSPI5_BASE_ADDR
|
2013-04-10 09:32:57 +00:00
|
|
|
#endif
|
2012-01-31 07:52:04 +00:00
|
|
|
|
2013-04-23 10:17:38 +00:00
|
|
|
struct ocotp_regs {
|
2011-11-25 00:18:02 +00:00
|
|
|
u32 ctrl;
|
|
|
|
|
u32 ctrl_set;
|
|
|
|
|
u32 ctrl_clr;
|
|
|
|
|
u32 ctrl_tog;
|
|
|
|
|
u32 timing;
|
|
|
|
|
u32 rsvd0[3];
|
|
|
|
|
u32 data;
|
|
|
|
|
u32 rsvd1[3];
|
|
|
|
|
u32 read_ctrl;
|
|
|
|
|
u32 rsvd2[3];
|
2013-04-23 10:17:38 +00:00
|
|
|
u32 read_fuse_data;
|
2011-11-25 00:18:02 +00:00
|
|
|
u32 rsvd3[3];
|
2013-04-23 10:17:38 +00:00
|
|
|
u32 sw_sticky;
|
2011-11-25 00:18:02 +00:00
|
|
|
u32 rsvd4[3];
|
|
|
|
|
u32 scs;
|
|
|
|
|
u32 scs_set;
|
|
|
|
|
u32 scs_clr;
|
|
|
|
|
u32 scs_tog;
|
|
|
|
|
u32 crc_addr;
|
|
|
|
|
u32 rsvd5[3];
|
|
|
|
|
u32 crc_value;
|
|
|
|
|
u32 rsvd6[3];
|
|
|
|
|
u32 version;
|
2011-12-19 02:38:13 +00:00
|
|
|
u32 rsvd7[0xdb];
|
2011-11-25 00:18:02 +00:00
|
|
|
|
mxc: ocotp fix hole in shadow registers
There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-26 07:40:47 +00:00
|
|
|
/* fuse banks */
|
2011-11-25 00:18:02 +00:00
|
|
|
struct fuse_bank {
|
|
|
|
|
u32 fuse_regs[0x20];
|
mxc: ocotp fix hole in shadow registers
There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-26 07:40:47 +00:00
|
|
|
} bank[0];
|
2011-11-25 00:18:02 +00:00
|
|
|
};
|
|
|
|
|
|
2013-04-23 10:17:39 +00:00
|
|
|
struct fuse_bank0_regs {
|
|
|
|
|
u32 lock;
|
|
|
|
|
u32 rsvd0[3];
|
|
|
|
|
u32 uid_low;
|
|
|
|
|
u32 rsvd1[3];
|
|
|
|
|
u32 uid_high;
|
2013-06-27 22:20:21 +00:00
|
|
|
u32 rsvd2[3];
|
2015-01-09 08:59:40 +00:00
|
|
|
u32 cfg2;
|
|
|
|
|
u32 rsvd3[3];
|
|
|
|
|
u32 cfg3;
|
|
|
|
|
u32 rsvd4[3];
|
|
|
|
|
u32 cfg4;
|
|
|
|
|
u32 rsvd5[3];
|
2013-06-27 22:20:21 +00:00
|
|
|
u32 cfg5;
|
|
|
|
|
u32 rsvd6[3];
|
2015-01-09 08:59:40 +00:00
|
|
|
u32 cfg6;
|
|
|
|
|
u32 rsvd7[3];
|
2013-04-23 10:17:39 +00:00
|
|
|
};
|
|
|
|
|
|
2015-05-18 13:56:44 +00:00
|
|
|
struct fuse_bank1_regs {
|
|
|
|
|
u32 mem0;
|
|
|
|
|
u32 rsvd0[3];
|
|
|
|
|
u32 mem1;
|
|
|
|
|
u32 rsvd1[3];
|
|
|
|
|
u32 mem2;
|
|
|
|
|
u32 rsvd2[3];
|
|
|
|
|
u32 mem3;
|
|
|
|
|
u32 rsvd3[3];
|
|
|
|
|
u32 mem4;
|
|
|
|
|
u32 rsvd4[3];
|
|
|
|
|
u32 ana0;
|
|
|
|
|
u32 rsvd5[3];
|
|
|
|
|
u32 ana1;
|
|
|
|
|
u32 rsvd6[3];
|
|
|
|
|
u32 ana2;
|
|
|
|
|
u32 rsvd7[3];
|
|
|
|
|
};
|
|
|
|
|
|
2014-06-24 20:40:58 +00:00
|
|
|
struct fuse_bank4_regs {
|
|
|
|
|
u32 sjc_resp_low;
|
|
|
|
|
u32 rsvd0[3];
|
|
|
|
|
u32 sjc_resp_high;
|
|
|
|
|
u32 rsvd1[3];
|
2016-02-01 02:41:31 +00:00
|
|
|
u32 mac_addr0;
|
2014-06-24 20:40:58 +00:00
|
|
|
u32 rsvd2[3];
|
2016-02-01 02:41:31 +00:00
|
|
|
u32 mac_addr1;
|
2014-06-24 20:40:58 +00:00
|
|
|
u32 rsvd3[3];
|
2016-02-01 02:41:31 +00:00
|
|
|
u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
|
2014-06-24 20:40:58 +00:00
|
|
|
u32 rsvd4[7];
|
|
|
|
|
u32 gp1;
|
2015-07-20 11:28:23 +00:00
|
|
|
u32 rsvd5[3];
|
|
|
|
|
u32 gp2;
|
|
|
|
|
u32 rsvd6[3];
|
2014-06-24 20:40:58 +00:00
|
|
|
};
|
2011-11-25 00:18:02 +00:00
|
|
|
|
2012-01-10 00:52:59 +00:00
|
|
|
struct aipstz_regs {
|
|
|
|
|
u32 mprot0;
|
|
|
|
|
u32 mprot1;
|
|
|
|
|
u32 rsvd[0xe];
|
|
|
|
|
u32 opacr0;
|
|
|
|
|
u32 opacr1;
|
|
|
|
|
u32 opacr2;
|
|
|
|
|
u32 opacr3;
|
|
|
|
|
u32 opacr4;
|
|
|
|
|
};
|
|
|
|
|
|
2012-03-20 04:21:45 +00:00
|
|
|
struct anatop_regs {
|
|
|
|
|
u32 pll_sys; /* 0x000 */
|
|
|
|
|
u32 pll_sys_set; /* 0x004 */
|
|
|
|
|
u32 pll_sys_clr; /* 0x008 */
|
|
|
|
|
u32 pll_sys_tog; /* 0x00c */
|
|
|
|
|
u32 usb1_pll_480_ctrl; /* 0x010 */
|
|
|
|
|
u32 usb1_pll_480_ctrl_set; /* 0x014 */
|
|
|
|
|
u32 usb1_pll_480_ctrl_clr; /* 0x018 */
|
|
|
|
|
u32 usb1_pll_480_ctrl_tog; /* 0x01c */
|
|
|
|
|
u32 usb2_pll_480_ctrl; /* 0x020 */
|
|
|
|
|
u32 usb2_pll_480_ctrl_set; /* 0x024 */
|
|
|
|
|
u32 usb2_pll_480_ctrl_clr; /* 0x028 */
|
|
|
|
|
u32 usb2_pll_480_ctrl_tog; /* 0x02c */
|
|
|
|
|
u32 pll_528; /* 0x030 */
|
|
|
|
|
u32 pll_528_set; /* 0x034 */
|
|
|
|
|
u32 pll_528_clr; /* 0x038 */
|
|
|
|
|
u32 pll_528_tog; /* 0x03c */
|
|
|
|
|
u32 pll_528_ss; /* 0x040 */
|
|
|
|
|
u32 rsvd0[3];
|
|
|
|
|
u32 pll_528_num; /* 0x050 */
|
|
|
|
|
u32 rsvd1[3];
|
|
|
|
|
u32 pll_528_denom; /* 0x060 */
|
|
|
|
|
u32 rsvd2[3];
|
|
|
|
|
u32 pll_audio; /* 0x070 */
|
|
|
|
|
u32 pll_audio_set; /* 0x074 */
|
|
|
|
|
u32 pll_audio_clr; /* 0x078 */
|
|
|
|
|
u32 pll_audio_tog; /* 0x07c */
|
|
|
|
|
u32 pll_audio_num; /* 0x080 */
|
|
|
|
|
u32 rsvd3[3];
|
|
|
|
|
u32 pll_audio_denom; /* 0x090 */
|
|
|
|
|
u32 rsvd4[3];
|
|
|
|
|
u32 pll_video; /* 0x0a0 */
|
|
|
|
|
u32 pll_video_set; /* 0x0a4 */
|
|
|
|
|
u32 pll_video_clr; /* 0x0a8 */
|
|
|
|
|
u32 pll_video_tog; /* 0x0ac */
|
|
|
|
|
u32 pll_video_num; /* 0x0b0 */
|
|
|
|
|
u32 rsvd5[3];
|
|
|
|
|
u32 pll_video_denom; /* 0x0c0 */
|
|
|
|
|
u32 rsvd6[3];
|
|
|
|
|
u32 pll_mlb; /* 0x0d0 */
|
|
|
|
|
u32 pll_mlb_set; /* 0x0d4 */
|
|
|
|
|
u32 pll_mlb_clr; /* 0x0d8 */
|
|
|
|
|
u32 pll_mlb_tog; /* 0x0dc */
|
|
|
|
|
u32 pll_enet; /* 0x0e0 */
|
|
|
|
|
u32 pll_enet_set; /* 0x0e4 */
|
|
|
|
|
u32 pll_enet_clr; /* 0x0e8 */
|
|
|
|
|
u32 pll_enet_tog; /* 0x0ec */
|
|
|
|
|
u32 pfd_480; /* 0x0f0 */
|
|
|
|
|
u32 pfd_480_set; /* 0x0f4 */
|
|
|
|
|
u32 pfd_480_clr; /* 0x0f8 */
|
|
|
|
|
u32 pfd_480_tog; /* 0x0fc */
|
|
|
|
|
u32 pfd_528; /* 0x100 */
|
|
|
|
|
u32 pfd_528_set; /* 0x104 */
|
|
|
|
|
u32 pfd_528_clr; /* 0x108 */
|
|
|
|
|
u32 pfd_528_tog; /* 0x10c */
|
|
|
|
|
u32 reg_1p1; /* 0x110 */
|
|
|
|
|
u32 reg_1p1_set; /* 0x114 */
|
|
|
|
|
u32 reg_1p1_clr; /* 0x118 */
|
|
|
|
|
u32 reg_1p1_tog; /* 0x11c */
|
|
|
|
|
u32 reg_3p0; /* 0x120 */
|
|
|
|
|
u32 reg_3p0_set; /* 0x124 */
|
|
|
|
|
u32 reg_3p0_clr; /* 0x128 */
|
|
|
|
|
u32 reg_3p0_tog; /* 0x12c */
|
|
|
|
|
u32 reg_2p5; /* 0x130 */
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|
|
|
u32 reg_2p5_set; /* 0x134 */
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|
|
u32 reg_2p5_clr; /* 0x138 */
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|
|
|
|
u32 reg_2p5_tog; /* 0x13c */
|
|
|
|
|
u32 reg_core; /* 0x140 */
|
|
|
|
|
u32 reg_core_set; /* 0x144 */
|
|
|
|
|
u32 reg_core_clr; /* 0x148 */
|
|
|
|
|
u32 reg_core_tog; /* 0x14c */
|
|
|
|
|
u32 ana_misc0; /* 0x150 */
|
|
|
|
|
u32 ana_misc0_set; /* 0x154 */
|
|
|
|
|
u32 ana_misc0_clr; /* 0x158 */
|
|
|
|
|
u32 ana_misc0_tog; /* 0x15c */
|
|
|
|
|
u32 ana_misc1; /* 0x160 */
|
|
|
|
|
u32 ana_misc1_set; /* 0x164 */
|
|
|
|
|
u32 ana_misc1_clr; /* 0x168 */
|
|
|
|
|
u32 ana_misc1_tog; /* 0x16c */
|
|
|
|
|
u32 ana_misc2; /* 0x170 */
|
|
|
|
|
u32 ana_misc2_set; /* 0x174 */
|
|
|
|
|
u32 ana_misc2_clr; /* 0x178 */
|
|
|
|
|
u32 ana_misc2_tog; /* 0x17c */
|
|
|
|
|
u32 tempsense0; /* 0x180 */
|
|
|
|
|
u32 tempsense0_set; /* 0x184 */
|
|
|
|
|
u32 tempsense0_clr; /* 0x188 */
|
|
|
|
|
u32 tempsense0_tog; /* 0x18c */
|
|
|
|
|
u32 tempsense1; /* 0x190 */
|
|
|
|
|
u32 tempsense1_set; /* 0x194 */
|
|
|
|
|
u32 tempsense1_clr; /* 0x198 */
|
|
|
|
|
u32 tempsense1_tog; /* 0x19c */
|
|
|
|
|
u32 usb1_vbus_detect; /* 0x1a0 */
|
|
|
|
|
u32 usb1_vbus_detect_set; /* 0x1a4 */
|
|
|
|
|
u32 usb1_vbus_detect_clr; /* 0x1a8 */
|
|
|
|
|
u32 usb1_vbus_detect_tog; /* 0x1ac */
|
|
|
|
|
u32 usb1_chrg_detect; /* 0x1b0 */
|
|
|
|
|
u32 usb1_chrg_detect_set; /* 0x1b4 */
|
|
|
|
|
u32 usb1_chrg_detect_clr; /* 0x1b8 */
|
|
|
|
|
u32 usb1_chrg_detect_tog; /* 0x1bc */
|
|
|
|
|
u32 usb1_vbus_det_stat; /* 0x1c0 */
|
|
|
|
|
u32 usb1_vbus_det_stat_set; /* 0x1c4 */
|
|
|
|
|
u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
|
|
|
|
|
u32 usb1_vbus_det_stat_tog; /* 0x1cc */
|
|
|
|
|
u32 usb1_chrg_det_stat; /* 0x1d0 */
|
|
|
|
|
u32 usb1_chrg_det_stat_set; /* 0x1d4 */
|
|
|
|
|
u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
|
|
|
|
|
u32 usb1_chrg_det_stat_tog; /* 0x1dc */
|
|
|
|
|
u32 usb1_loopback; /* 0x1e0 */
|
|
|
|
|
u32 usb1_loopback_set; /* 0x1e4 */
|
|
|
|
|
u32 usb1_loopback_clr; /* 0x1e8 */
|
|
|
|
|
u32 usb1_loopback_tog; /* 0x1ec */
|
|
|
|
|
u32 usb1_misc; /* 0x1f0 */
|
|
|
|
|
u32 usb1_misc_set; /* 0x1f4 */
|
|
|
|
|
u32 usb1_misc_clr; /* 0x1f8 */
|
|
|
|
|
u32 usb1_misc_tog; /* 0x1fc */
|
|
|
|
|
u32 usb2_vbus_detect; /* 0x200 */
|
|
|
|
|
u32 usb2_vbus_detect_set; /* 0x204 */
|
|
|
|
|
u32 usb2_vbus_detect_clr; /* 0x208 */
|
|
|
|
|
u32 usb2_vbus_detect_tog; /* 0x20c */
|
|
|
|
|
u32 usb2_chrg_detect; /* 0x210 */
|
|
|
|
|
u32 usb2_chrg_detect_set; /* 0x214 */
|
|
|
|
|
u32 usb2_chrg_detect_clr; /* 0x218 */
|
|
|
|
|
u32 usb2_chrg_detect_tog; /* 0x21c */
|
|
|
|
|
u32 usb2_vbus_det_stat; /* 0x220 */
|
|
|
|
|
u32 usb2_vbus_det_stat_set; /* 0x224 */
|
|
|
|
|
u32 usb2_vbus_det_stat_clr; /* 0x228 */
|
|
|
|
|
u32 usb2_vbus_det_stat_tog; /* 0x22c */
|
|
|
|
|
u32 usb2_chrg_det_stat; /* 0x230 */
|
|
|
|
|
u32 usb2_chrg_det_stat_set; /* 0x234 */
|
|
|
|
|
u32 usb2_chrg_det_stat_clr; /* 0x238 */
|
|
|
|
|
u32 usb2_chrg_det_stat_tog; /* 0x23c */
|
|
|
|
|
u32 usb2_loopback; /* 0x240 */
|
|
|
|
|
u32 usb2_loopback_set; /* 0x244 */
|
|
|
|
|
u32 usb2_loopback_clr; /* 0x248 */
|
|
|
|
|
u32 usb2_loopback_tog; /* 0x24c */
|
|
|
|
|
u32 usb2_misc; /* 0x250 */
|
|
|
|
|
u32 usb2_misc_set; /* 0x254 */
|
|
|
|
|
u32 usb2_misc_clr; /* 0x258 */
|
|
|
|
|
u32 usb2_misc_tog; /* 0x25c */
|
|
|
|
|
u32 digprog; /* 0x260 */
|
2012-10-23 10:57:46 +00:00
|
|
|
u32 reserved1[7];
|
|
|
|
|
u32 digprog_sololite; /* 0x280 */
|
2012-03-20 04:21:45 +00:00
|
|
|
};
|
|
|
|
|
|
2013-08-29 19:37:35 +00:00
|
|
|
#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
|
|
|
|
|
#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
|
|
|
|
|
#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
|
|
|
|
|
#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
|
|
|
|
|
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
|
|
|
|
|
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
|
2012-09-19 08:29:46 +00:00
|
|
|
|
2013-02-07 06:45:23 +00:00
|
|
|
struct wdog_regs {
|
|
|
|
|
u16 wcr; /* Control */
|
|
|
|
|
u16 wsr; /* Service */
|
|
|
|
|
u16 wrsr; /* Reset Status */
|
|
|
|
|
u16 wicr; /* Interrupt Control */
|
|
|
|
|
u16 wmcr; /* Miscellaneous Control */
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-18 04:07:18 +00:00
|
|
|
#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
|
|
|
|
|
#define PWMCR_DOZEEN (1 << 24)
|
|
|
|
|
#define PWMCR_WAITEN (1 << 23)
|
|
|
|
|
#define PWMCR_DBGEN (1 << 22)
|
|
|
|
|
#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
|
|
|
|
|
#define PWMCR_CLKSRC_IPG (1 << 16)
|
|
|
|
|
#define PWMCR_EN (1 << 0)
|
|
|
|
|
|
|
|
|
|
struct pwm_regs {
|
|
|
|
|
u32 cr;
|
|
|
|
|
u32 sr;
|
|
|
|
|
u32 ir;
|
|
|
|
|
u32 sar;
|
|
|
|
|
u32 pr;
|
|
|
|
|
u32 cnr;
|
|
|
|
|
};
|
2018-05-30 17:01:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
|
|
|
|
|
* If boot from the other mode, USB0_PWD will keep reset value
|
|
|
|
|
*/
|
|
|
|
|
#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
|
|
|
|
|
|
2020-05-10 17:40:12 +00:00
|
|
|
#endif /* __ASSEMBLY__ */
|
2011-11-25 00:18:02 +00:00
|
|
|
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
|
