mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
imx: mx6sll: update register address
Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
36e40142f4
commit
56612bf6c6
1 changed files with 50 additions and 27 deletions
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@ -26,7 +26,7 @@
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#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
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#define M4_BOOTROM_BASE_ADDR 0x007F8000
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#else
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#elif !defined(CONFIG_MX6SLL)
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#define CAAM_ARB_BASE_ADDR 0x00100000
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#define CAAM_ARB_END_ADDR 0x00103FFF
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#define APBH_DMA_ARB_BASE_ADDR 0x00110000
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@ -46,13 +46,9 @@
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#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
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/* GPV - PL301 configuration ports */
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#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
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#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
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defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
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#define GPV2_BASE_ADDR 0x00D00000
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#else
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#define GPV2_BASE_ADDR 0x00200000
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#endif
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#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
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#define GPV3_BASE_ADDR 0x00E00000
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#define GPV4_BASE_ADDR 0x00F00000
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#define GPV5_BASE_ADDR 0x01000000
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@ -61,6 +57,7 @@
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#define PCIE_ARB_END_ADDR 0x08FFFFFF
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#else
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#define GPV2_BASE_ADDR 0x00200000
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#define GPV3_BASE_ADDR 0x00300000
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#define GPV4_BASE_ADDR 0x00800000
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#define PCIE_ARB_BASE_ADDR 0x01000000
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@ -96,7 +93,7 @@
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#define WEIM_ARB_END_ADDR 0x57FFFFFF
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#define QSPI0_AMBA_BASE 0x60000000
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#define QSPI0_AMBA_END 0x6FFFFFFF
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#else
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#elif !defined(CONFIG_MX6SLL)
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#define SATA_ARB_BASE_ADDR 0x02200000
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#define SATA_ARB_END_ADDR 0x02203FFF
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#define OPENVG_ARB_BASE_ADDR 0x02204000
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@ -111,7 +108,8 @@
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#define WEIM_ARB_END_ADDR 0x0FFFFFFF
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#endif
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#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
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#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
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defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
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#define MMDC0_ARB_BASE_ADDR 0x80000000
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#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
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#define MMDC1_ARB_BASE_ADDR 0xC0000000
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@ -141,19 +139,21 @@
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#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
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#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
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#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
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#ifdef CONFIG_MX6SL
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#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
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#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
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#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
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#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
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#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
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#else
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#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
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#ifndef CONFIG_MX6SX
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#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#endif
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#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
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#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
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#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
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@ -161,7 +161,6 @@
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#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
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#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
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#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#endif
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#ifndef CONFIG_MX6SX
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#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
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@ -176,6 +175,8 @@
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#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
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#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
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#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
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/* QOSC on i.MX6SLL */
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#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
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#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
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#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
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#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
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@ -198,11 +199,18 @@
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#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
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#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
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#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
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#ifdef CONFIG_MX6SL
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#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
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#ifdef CONFIG_MX6SLL
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#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
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#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
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#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
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#elif defined(CONFIG_MX6SL)
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#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
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#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#elif CONFIG_MX6SX
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#elif defined(CONFIG_MX6SX)
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#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
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@ -215,6 +223,9 @@
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#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#endif
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#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
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#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
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#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
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#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
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#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
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@ -249,7 +260,7 @@
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#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
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#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
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#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
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/* i.MX6SL */
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/* i.MX6SL/SLL */
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#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
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#ifdef CONFIG_MX6UL
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#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
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@ -263,6 +274,10 @@
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#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
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#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
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#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
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#ifdef CONFIG_MX6SLL
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#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
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#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
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#endif
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#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
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#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
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#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
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@ -296,6 +311,8 @@
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#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
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#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
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#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
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/* i.MX6SLL */
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#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
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#ifdef CONFIG_MX6SX
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#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
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@ -334,7 +351,8 @@
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#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
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#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
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#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
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#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
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defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
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#define IRAM_SIZE 0x00040000
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#else
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#define IRAM_SIZE 0x00020000
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@ -348,10 +366,14 @@
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/* only for i.MX6SX/UL */
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#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
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MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
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#define LCDIF1_BASE_ADDR ((is_mx6ul()) ? \
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#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
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MX6SLL_LCDIF_BASE_ADDR : \
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(is_cpu_type(MXC_CPU_MX6SL)) ? \
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MX6SL_LCDIF_BASE_ADDR : \
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((is_cpu_type(MXC_CPU_MX6UL)) ? \
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MX6UL_LCDIF1_BASE_ADDR : \
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((is_mx6ull()) ? \
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MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))
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MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
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extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
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@ -672,7 +694,8 @@ struct cspi_regs {
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
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#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
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defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
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#define MXC_SPI_BASE_ADDRESSES \
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ECSPI1_BASE_ADDR, \
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ECSPI2_BASE_ADDR, \
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