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i.MX6: Correct ANATOP_PFD (Phase Fractional Divider) register declarations

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Some _CLKGATE_MASK and _FRAC_MASK macros were wrong for PFD_480
and the PFD_528 macros were missing.

Fortunately, the incorrect macros weren't being used.

Since both the PFD_480 and PFD_528 registers have the same
structure, and the fields are identical for [0..3] in bytes
[0..3], so a single set of macros will suffice.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This commit is contained in:
Eric Nelson 2013-08-29 12:37:35 -07:00 committed by Stefano Babic
parent 1ca244ded5
commit 3fc4176dc4
1 changed files with 6 additions and 23 deletions
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29
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -635,29 +635,12 @@ struct anatop_regs {
u32 digprog_sololite; /* 0x280 */
};
#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
struct iomuxc_base_regs {
u32 gpr[14]; /* 0x000 */