2011-01-19 09:05:26 +00:00
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/*
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powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-04-24 20:16:49 +00:00
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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2011-01-19 09:05:26 +00:00
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-01-19 09:05:26 +00:00
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*/
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#ifndef _ASM_MPC85xx_CONFIG_H_
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#define _ASM_MPC85xx_CONFIG_H_
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/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
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2011-08-04 23:03:41 +00:00
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#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
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#endif
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2012-10-28 08:12:54 +00:00
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/*
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* This macro should be removed when we no longer care about backwards
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* compatibility with older operating systems.
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*/
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#define CONFIG_PPC_SPINTABLE_COMPATIBLE
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2014-03-28 00:54:47 +00:00
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#include <fsl_ddrc_version.h>
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#define CONFIG_SYS_FSL_DDR_BE
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2012-10-08 07:44:22 +00:00
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2014-01-18 06:58:30 +00:00
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/* IP endianness */
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#define CONFIG_SYS_FSL_IFC_BE
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2014-09-09 06:20:31 +00:00
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#define CONFIG_SYS_FSL_SEC_BE
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2015-02-27 04:13:49 +00:00
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#define CONFIG_SYS_FSL_SFP_BE
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2015-02-27 04:16:17 +00:00
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#define CONFIG_SYS_FSL_SEC_MON_BE
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2014-01-18 06:58:30 +00:00
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2011-01-19 09:05:26 +00:00
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/* Number of TLB CAM entries we have on FSL Book-E chips */
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#if defined(CONFIG_E500MC)
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#define CONFIG_SYS_NUM_TLBCAMS 64
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#elif defined(CONFIG_E500)
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#define CONFIG_SYS_NUM_TLBCAMS 16
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#endif
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2016-11-16 19:06:47 +00:00
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#if defined(CONFIG_ARCH_MPC8536)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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2012-08-15 04:12:43 +00:00
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:13:06 +00:00
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#elif defined(CONFIG_ARCH_MPC8540)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN1
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:18:31 +00:00
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#elif defined(CONFIG_ARCH_MPC8541)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN1
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-01-19 09:05:26 +00:00
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2016-11-15 21:57:15 +00:00
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#elif defined(CONFIG_ARCH_MPC8544)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN2
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2012-08-15 04:12:43 +00:00
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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2011-01-19 09:05:26 +00:00
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2016-11-15 21:52:34 +00:00
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#elif defined(CONFIG_ARCH_MPC8548)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN2
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2012-08-15 04:12:43 +00:00
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-09-16 14:54:30 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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2011-10-03 13:37:57 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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2011-10-03 13:38:50 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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2012-03-08 00:33:14 +00:00
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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2013-08-16 07:10:37 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:23:23 +00:00
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#elif defined(CONFIG_ARCH_MPC8555)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN1
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:26:45 +00:00
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#elif defined(CONFIG_ARCH_MPC8560)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN1
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:32:17 +00:00
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#elif defined(CONFIG_ARCH_MPC8568)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN2
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-02-01 05:09:25 +00:00
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#define QE_MURAM_SIZE 0x10000UL
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2012-03-08 00:33:14 +00:00
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:34:52 +00:00
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#elif defined(CONFIG_ARCH_MPC8569)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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2011-02-01 05:09:25 +00:00
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#define QE_MURAM_SIZE 0x20000UL
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#define MAX_QE_RISC 4
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#define QE_NUM_OF_SNUM 46
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2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2012-03-08 00:33:14 +00:00
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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2011-01-19 09:05:26 +00:00
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2016-11-16 19:39:20 +00:00
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#elif defined(CONFIG_ARCH_MPC8572)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-08-15 04:12:43 +00:00
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2011-08-04 23:03:41 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-01-26 05:51:27 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_DDR_115
|
2011-01-26 06:05:49 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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2011-01-19 09:05:26 +00:00
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2016-11-16 21:08:52 +00:00
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#elif defined(CONFIG_ARCH_P1010)
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2011-01-19 09:05:26 +00:00
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#define CONFIG_MAX_CPUS 1
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2011-02-09 03:54:10 +00:00
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#define CONFIG_FSL_SDHC_V2_3
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2011-01-19 09:05:26 +00:00
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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2012-04-29 23:57:12 +00:00
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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2011-01-19 09:05:26 +00:00
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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2011-02-06 06:01:44 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
|
2013-10-18 12:10:17 +00:00
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2013-05-16 02:18:13 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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2011-02-06 06:01:44 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2011-05-20 05:39:21 +00:00
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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2011-03-23 09:50:43 +00:00
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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2011-06-30 08:00:28 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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2011-06-29 11:02:52 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
|
2013-08-15 01:31:47 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
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2011-07-07 15:06:47 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2013-08-16 07:10:37 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
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#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2014-02-26 12:13:15 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A007075
|
2016-08-17 06:17:53 +00:00
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
2014-02-26 08:59:12 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A006261
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2014-11-21 11:55:21 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A004477
|
2013-08-16 07:10:37 +00:00
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
|
2014-01-10 05:52:19 +00:00
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#define CONFIG_ESDHC_HC_BLK_ADDR
|
2011-01-19 09:05:26 +00:00
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2011-02-05 19:45:07 +00:00
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/* P1011 is single core version of P1020 */
|
2016-11-16 23:54:15 +00:00
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#elif defined(CONFIG_ARCH_P1011)
|
2011-01-19 09:05:26 +00:00
|
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-04-29 23:57:12 +00:00
|
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|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_TSECV2
|
2011-02-01 15:55:58 +00:00
|
|
|
#define CONFIG_FSL_PCIE_DISABLE_ASPM
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2011-02-04 04:14:19 +00:00
|
|
|
|
2016-11-18 18:02:14 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P1020)
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-04-29 23:57:12 +00:00
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_TSECV2
|
2011-02-01 15:55:58 +00:00
|
|
|
#define CONFIG_FSL_PCIE_DISABLE_ASPM
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2014-05-13 10:06:07 +00:00
|
|
|
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2014-05-13 10:06:07 +00:00
|
|
|
#endif
|
2011-01-19 09:05:26 +00:00
|
|
|
|
2016-11-18 18:59:02 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P1021)
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-04-29 23:57:12 +00:00
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_TSECV2
|
2011-02-01 15:55:58 +00:00
|
|
|
#define CONFIG_FSL_PCIE_DISABLE_ASPM
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2011-02-11 07:25:30 +00:00
|
|
|
#define QE_MURAM_SIZE 0x6000UL
|
|
|
|
|
#define MAX_QE_RISC 1
|
|
|
|
|
#define QE_NUM_OF_SNUM 28
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2011-01-19 09:05:26 +00:00
|
|
|
|
2016-11-16 23:23:52 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P1022)
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-04-29 23:57:12 +00:00
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_TSECV2
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2015-01-30 06:52:11 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-01-30 23:06:20 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
|
|
|
#define CONFIG_FSL_SATA_ERRATUM_A001
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2014-11-21 11:55:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
2011-01-19 09:05:26 +00:00
|
|
|
|
2016-11-16 23:45:31 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P1023)
|
2011-02-04 04:14:19 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 2
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2011-02-04 04:14:19 +00:00
|
|
|
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
|
|
|
|
|
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
|
2011-02-04 06:43:34 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
|
2011-05-20 05:39:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
|
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
2011-02-04 04:14:19 +00:00
|
|
|
|
2011-02-05 19:45:07 +00:00
|
|
|
/* P1024 is lower end variant of P1020 */
|
2016-11-18 19:00:57 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P1024)
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-04-29 23:57:12 +00:00
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_TSECV2
|
|
|
|
|
#define CONFIG_FSL_PCIE_DISABLE_ASPM
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2011-02-05 19:45:07 +00:00
|
|
|
|
|
|
|
|
/* P1025 is lower end variant of P1021 */
|
2016-11-18 19:05:38 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P1025)
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2015-05-21 03:37:53 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2012-04-29 23:57:12 +00:00
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_TSECV2
|
|
|
|
|
#define CONFIG_FSL_PCIE_DISABLE_ASPM
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-02-05 19:45:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2011-02-11 07:25:30 +00:00
|
|
|
#define QE_MURAM_SIZE 0x6000UL
|
|
|
|
|
#define MAX_QE_RISC 1
|
|
|
|
|
#define QE_NUM_OF_SNUM 28
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2011-02-05 19:45:07 +00:00
|
|
|
|
2016-11-18 19:08:43 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P2020)
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
2012-04-29 23:57:12 +00:00
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
2011-01-26 07:43:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2011-01-29 21:36:10 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
|
2012-03-08 00:33:14 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
|
|
|
#define CONFIG_SYS_FSL_RMU
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2014-11-21 11:55:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
|
|
|
|
2016-11-18 19:15:21 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
|
2012-10-08 07:44:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
2013-06-25 18:37:39 +00:00
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
2011-05-13 06:16:07 +00:00
|
|
|
#define CONFIG_MAX_CPUS 4
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2011-05-13 06:16:07 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
|
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
|
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2011-05-13 06:16:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
2011-04-13 05:19:10 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
2011-05-13 06:16:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2012-05-07 07:26:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
|
2013-03-11 17:56:34 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
2011-11-22 12:51:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
|
2013-03-25 07:30:11 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
2011-11-20 18:01:35 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
2012-03-08 00:33:14 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
|
|
|
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
2012-09-28 21:26:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
2012-10-25 12:40:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
2014-02-26 08:59:12 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
2011-05-13 06:16:07 +00:00
|
|
|
|
2016-11-18 19:20:40 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P3041)
|
2012-10-08 07:44:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
2013-06-25 18:37:39 +00:00
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 4
|
2011-02-16 08:03:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
2011-01-25 18:42:32 +00:00
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
2014-03-28 00:54:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
|
2011-02-04 06:43:34 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
2011-02-18 11:40:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
2011-05-20 05:39:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2011-04-13 05:08:51 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
2011-04-13 05:19:10 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2011-04-19 07:28:41 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2012-08-08 18:04:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
|
2013-03-11 17:56:34 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
2011-11-22 12:51:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
|
2013-03-25 07:30:11 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
2011-11-20 18:01:35 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
2012-03-08 00:33:14 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
|
|
|
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
2012-09-28 21:26:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
2012-10-25 12:40:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
2013-06-25 18:37:49 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
2014-02-26 08:59:12 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
2011-01-19 09:05:26 +00:00
|
|
|
|
2016-11-18 19:24:40 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
|
2012-10-08 07:44:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
2013-06-25 18:37:39 +00:00
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 8
|
2011-02-16 08:03:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 2
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
2014-03-28 00:54:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2011-02-04 06:43:34 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
2011-02-18 11:40:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
2011-05-20 05:39:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
|
2011-01-10 12:03:01 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
2012-09-18 09:50:08 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_P4080_ERRATUM_CPU22
|
2012-05-07 07:26:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
|
2010-09-01 03:57:38 +00:00
|
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
|
2011-04-18 22:16:00 +00:00
|
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
|
2011-04-01 18:19:36 +00:00
|
|
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
|
2011-11-22 12:51:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
|
2011-11-20 18:01:35 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
2012-03-08 00:33:14 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
|
|
|
#define CONFIG_SYS_FSL_RMU
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
|
|
|
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
2012-09-28 21:26:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
2012-10-25 12:40:00 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
2012-11-01 08:20:23 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004580
|
2012-11-26 23:49:45 +00:00
|
|
|
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
|
2013-06-25 18:37:49 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
2014-02-26 12:13:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A007075
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
2011-01-19 09:05:26 +00:00
|
|
|
|
2016-11-18 19:30:56 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
|
2012-10-08 07:44:30 +00:00
|
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
2012-10-08 07:44:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
2013-06-25 18:37:39 +00:00
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
2011-02-16 08:03:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
2011-01-19 09:05:26 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
2011-01-25 18:42:32 +00:00
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
2014-03-28 00:54:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2011-02-04 06:43:34 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
2011-02-18 11:40:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
2011-05-20 05:39:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
2011-08-04 23:03:41 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2011-04-13 05:08:51 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
2011-04-13 05:19:10 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
2011-04-19 07:28:41 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2013-03-11 17:56:34 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
2013-03-25 07:30:11 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
2011-11-20 18:01:35 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
2012-03-08 00:33:14 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
|
|
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
|
2012-09-28 21:26:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
2014-02-26 08:59:12 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
2011-01-19 09:05:26 +00:00
|
|
|
|
2016-11-18 19:39:36 +00:00
|
|
|
#elif defined(CONFIG_ARCH_P5040)
|
2012-10-23 10:48:09 +00:00
|
|
|
#define CONFIG_SYS_PPC64
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
2013-06-25 18:37:39 +00:00
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#define CONFIG_MAX_CPUS 4
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 2
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 5
|
|
|
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
2014-03-28 00:54:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
|
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
|
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2013-03-11 17:56:34 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_USB14
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004699
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
2014-02-26 08:59:12 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
2013-06-25 18:37:49 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
|
2016-11-15 22:09:50 +00:00
|
|
|
#elif defined(CONFIG_ARCH_BSC9131)
|
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-04-24 20:16:49 +00:00
|
|
|
#define CONFIG_MAX_CPUS 1
|
|
|
|
|
#define CONFIG_FSL_SDHC_V2_3
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
|
|
|
|
#define CONFIG_TSECV2
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
2014-03-28 00:54:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2013-04-04 04:01:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
|
|
|
|
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
2013-05-16 02:18:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-04-24 20:16:49 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
|
|
|
|
#define CONFIG_NAND_FSL_IFC
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2014-11-21 11:55:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
2014-01-10 05:52:19 +00:00
|
|
|
#define CONFIG_ESDHC_HC_BLK_ADDR
|
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-04-24 20:16:49 +00:00
|
|
|
|
2016-11-15 22:09:50 +00:00
|
|
|
#elif defined(CONFIG_ARCH_BSC9132)
|
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-23 17:59:57 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
|
|
|
|
#define CONFIG_FSL_SDHC_V2_3
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
|
|
|
|
#define CONFIG_TSECV2
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
2014-03-28 00:54:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2013-07-02 03:51:04 +00:00
|
|
|
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
|
|
|
|
|
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
|
|
|
|
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
|
|
|
|
|
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
2013-04-19 02:31:01 +00:00
|
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-23 17:59:57 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
|
|
|
|
#define CONFIG_NAND_FSL_IFC
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
|
|
|
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
|
|
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
2013-08-20 22:09:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
2014-05-07 02:50:20 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005434
|
2014-11-21 11:55:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
2013-08-16 07:10:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
|
|
|
|
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
2014-01-10 05:52:19 +00:00
|
|
|
#define CONFIG_ESDHC_HC_BLK_ADDR
|
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-23 17:59:57 +00:00
|
|
|
|
2014-04-25 08:31:22 +00:00
|
|
|
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
|
|
|
|
|
defined(CONFIG_PPC_T4080)
|
2013-03-25 07:40:05 +00:00
|
|
|
#define CONFIG_E6500
|
2012-10-08 07:44:30 +00:00
|
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
2012-10-08 07:44:19 +00:00
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
2013-03-25 07:40:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
2012-10-08 07:44:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
2013-03-25 07:40:05 +00:00
|
|
|
#ifdef CONFIG_PPC_T4240
|
2012-10-08 07:44:19 +00:00
|
|
|
#define CONFIG_MAX_CPUS 12
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
|
2012-10-08 07:44:19 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
|
|
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 8
|
|
|
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 2
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261
Apply the erratum A006261 for the following Socs:
P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1
Do not apply erratum A006261 for the following Socs:
T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081
Erratum A006261 is applicable for the following Socs:
P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1),
P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0),
P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1).
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-17 06:17:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
2013-03-25 07:40:05 +00:00
|
|
|
#else
|
2014-04-25 08:31:22 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
2013-03-25 07:40:05 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
2014-04-25 08:31:22 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM2_DTSEC 8
|
2013-03-25 07:40:05 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
2014-04-25 08:31:22 +00:00
|
|
|
#if defined(CONFIG_PPC_T4160)
|
|
|
|
|
#define CONFIG_MAX_CPUS 8
|
|
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
|
|
|
|
#elif defined(CONFIG_PPC_T4080)
|
|
|
|
|
#define CONFIG_MAX_CPUS 4
|
|
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
|
|
|
|
|
#endif
|
2013-03-25 07:40:05 +00:00
|
|
|
#endif
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
2013-07-31 11:26:41 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
|
|
|
#define CONFIG_SYS_FSL_SRDS_2
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRDS_3
|
|
|
|
|
#define CONFIG_SYS_FSL_SRDS_4
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 2
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_PME_CLK 0
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
2013-05-16 02:18:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FMAN_V3
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_FM1_CLK 3
|
|
|
|
|
#define CONFIG_SYS_FM2_CLK 3
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
2013-06-25 10:12:14 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_LIODN
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
2013-09-16 19:49:31 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
2014-05-28 08:48:55 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A007186
|
2013-05-15 22:50:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
2014-10-17 03:42:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A007798
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2014-05-28 08:48:55 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
2013-03-25 07:33:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
|
|
|
|
|
2016-11-18 19:56:57 +00:00
|
|
|
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
|
2013-03-25 07:40:20 +00:00
|
|
|
#define CONFIG_E6500
|
2012-12-23 19:24:16 +00:00
|
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
|
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
|
|
|
|
|
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
|
|
|
|
|
#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
|
2012-12-23 19:24:16 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
2013-07-31 11:26:41 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
|
|
|
#define CONFIG_SYS_FSL_SRDS_2
|
powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
#define CONFIG_SYS_MAPLE
|
|
|
|
|
#define CONFIG_SYS_CPRI
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
2012-12-23 19:24:16 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_FM1_CLK 0
|
powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
#define CONFIG_SYS_CPRI_CLK 3
|
|
|
|
|
#define CONFIG_SYS_ULB_CLK 4
|
|
|
|
|
#define CONFIG_SYS_ETVPE_CLK 1
|
2012-12-23 19:24:16 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
2013-05-16 02:18:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
2012-12-23 19:24:16 +00:00
|
|
|
#define CONFIG_SYS_FMAN_V3
|
|
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
|
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
2013-02-27 21:56:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
2013-09-16 19:49:31 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
2014-05-28 08:48:55 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A007186
|
2013-05-15 22:50:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
2014-02-26 12:13:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A007075
|
2014-02-26 10:38:22 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006475
|
|
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A006384
|
2014-03-28 22:07:27 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A007212
|
2014-11-21 11:55:21 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
2012-12-23 19:24:16 +00:00
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2014-05-28 08:48:55 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
2012-12-23 19:24:16 +00:00
|
|
|
|
2016-11-18 19:44:43 +00:00
|
|
|
#ifdef CONFIG_ARCH_B4860
|
2013-03-25 07:40:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:20 +00:00
|
|
|
#define CONFIG_MAX_CPUS 4
|
powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
#define CONFIG_MAX_DSP_CPUS 12
|
|
|
|
|
#define CONFIG_NUM_DSP_CPUS 6
|
2014-02-26 10:37:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:20 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
2012-12-23 19:22:33 +00:00
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:20 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
|
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
2013-06-25 10:12:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRIO_LIODN
|
2013-03-25 07:40:20 +00:00
|
|
|
#else
|
|
|
|
|
#define CONFIG_MAX_CPUS 2
|
powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
#define CONFIG_MAX_DSP_CPUS 2
|
2014-02-26 10:37:37 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
|
2013-03-25 07:40:20 +00:00
|
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
|
2013-03-25 07:40:20 +00:00
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 0
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
|
|
|
#endif
|
powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:20 +00:00
|
|
|
|
2016-11-18 21:36:39 +00:00
|
|
|
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
|
2013-10-18 07:00:21 +00:00
|
|
|
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_E5500
|
|
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
2013-03-25 07:40:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
2014-03-28 00:54:47 +00:00
|
|
|
#ifdef CONFIG_SYS_FSL_DDR4
|
|
|
|
|
#define CONFIG_SYS_FSL_DDRC_GEN4
|
|
|
|
|
#endif
|
2016-11-18 21:36:39 +00:00
|
|
|
#if defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_MAX_CPUS 4
|
2013-09-03 05:49:54 +00:00
|
|
|
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 16
|
2013-09-03 05:49:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
|
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
2013-10-18 12:10:17 +00:00
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_PME_PLAT_CLK_DIV 2
|
|
|
|
|
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
|
2013-09-03 05:49:54 +00:00
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
|
|
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
2014-10-29 17:03:09 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A008044
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_SYS_FMAN_V3
|
2013-09-03 05:50:15 +00:00
|
|
|
#define CONFIG_FM_PLAT_CLK_DIV 1
|
|
|
|
|
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
|
2015-04-22 05:57:40 +00:00
|
|
|
#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
|
|
|
|
|
per rcw field value */
|
|
|
|
|
#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
|
2013-09-03 05:49:54 +00:00
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
|
2013-12-17 08:55:52 +00:00
|
|
|
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
2013-12-11 07:19:13 +00:00
|
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
2014-01-27 09:51:58 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
2013-03-25 07:40:06 +00:00
|
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
|
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
2014-03-18 09:04:23 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
|
|
|
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
2014-03-21 08:21:45 +00:00
|
|
|
#define QE_MURAM_SIZE 0x6000UL
|
|
|
|
|
#define MAX_QE_RISC 1
|
|
|
|
|
#define QE_NUM_OF_SNUM 28
|
2015-03-26 10:22:47 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
2015-11-20 07:52:04 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A008378
|
2015-12-16 08:45:41 +00:00
|
|
|
#define CONFIG_SYS_FSL_ERRATUM_A009663
|
2013-03-25 07:40:06 +00:00
|
|
|
|
2016-11-18 21:01:34 +00:00
|
|
|
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
|
2014-11-24 09:11:54 +00:00
|
|
|
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|
|
|
|
#define CONFIG_E5500
|
|
|
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
|
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
|
|
|
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
|
|
|
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
|
|
|
|
#define CONFIG_SYS_FMAN_V3
|
|
|
|
|
#ifdef CONFIG_SYS_FSL_DDR4
|
|
|
|
|
#define CONFIG_SYS_FSL_DDRC_GEN4
|
|
|
|
|
#endif
|
2016-11-18 21:01:34 +00:00
|
|
|
#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
|
2014-11-24 09:11:54 +00:00
|
|
|
#define CONFIG_MAX_CPUS 2
|
|
|
|
|
#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|
|
|
|
#define CONFIG_MAX_CPUS 1
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
|
|
|
|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 16
|
|
|
|
|
#define CONFIG_SYS_FSL_SRDS_1
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
|
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
2014-11-24 09:11:57 +00:00
|
|
|
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
|
2014-11-24 09:11:54 +00:00
|
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
|
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
|
|
|
|
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
|
|
|
|
#define CONFIG_SYS_FM1_CLK 0
|
2015-04-22 05:57:40 +00:00
|
|
|
#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
|
|
|
|
|
per rcw field value */
|
2014-11-24 09:11:54 +00:00
|
|
|
#define CONFIG_QBMAN_CLK_DIV 1
|
|
|
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
|
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#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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2015-11-20 07:52:04 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A008378
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2015-12-16 08:45:41 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A009663
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2014-11-24 09:11:54 +00:00
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2016-11-21 20:54:19 +00:00
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#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
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2013-11-22 09:39:10 +00:00
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#define CONFIG_E6500
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_QMAN_V3
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_PCI_VER_3_X
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2016-11-21 20:54:19 +00:00
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#if defined(CONFIG_ARCH_T2080)
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2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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#define CONFIG_SYS_NUM_FM1_10GEC 4
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_FSL_SRIO_LIODN
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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2016-11-21 20:54:19 +00:00
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#elif defined(CONFIG_ARCH_T2081)
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2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_NUM_FM1_DTSEC 6
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#define CONFIG_SYS_NUM_FM1_10GEC 2
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#endif
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2013-12-18 02:27:55 +00:00
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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2013-11-22 09:39:10 +00:00
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_PME_PLAT_CLK_DIV 1
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#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
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#define CONFIG_SYS_FM1_CLK 0
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2015-04-22 05:57:40 +00:00
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#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
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per rcw field value */
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#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
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2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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2014-03-28 22:07:27 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A007212
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2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ISBC_VER 2
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2014-03-18 09:04:23 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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2014-04-24 03:10:09 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A006593
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2014-05-28 08:48:55 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A007186
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2014-04-24 03:10:09 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A006379
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2014-03-18 09:04:23 +00:00
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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2014-05-28 08:48:55 +00:00
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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2014-03-18 09:04:23 +00:00
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2013-11-22 09:39:10 +00:00
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2016-11-16 02:44:22 +00:00
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#elif defined(CONFIG_ARCH_C29X)
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2013-07-04 09:30:36 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2_1
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#define CONFIG_SYS_FSL_SEC_COMPAT 6
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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2014-03-28 00:54:47 +00:00
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
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2013-07-04 09:30:36 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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2013-08-20 22:09:43 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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2016-04-29 12:17:59 +00:00
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
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#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
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2013-07-04 09:30:36 +00:00
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2016-11-18 20:29:51 +00:00
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#elif defined(CONFIG_ARCH_QEMU_E500)
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2014-04-11 15:09:45 +00:00
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
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2011-01-19 09:05:26 +00:00
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#else
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#error Processor type not defined for this platform
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#endif
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2011-08-04 23:03:41 +00:00
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#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
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#endif
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2013-03-25 07:40:07 +00:00
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#ifdef CONFIG_E6500
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#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
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#else
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#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
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#endif
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2013-09-30 16:22:09 +00:00
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#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
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!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
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2014-03-28 00:54:47 +00:00
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!defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
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!defined(CONFIG_SYS_FSL_DDRC_GEN4)
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2013-09-30 16:22:09 +00:00
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#define CONFIG_SYS_FSL_DDRC_GEN3
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#endif
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2016-11-16 02:44:22 +00:00
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#if !defined(CONFIG_ARCH_C29X)
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2016-04-29 12:17:59 +00:00
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#endif
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2011-01-19 09:05:26 +00:00
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#endif /* _ASM_MPC85xx_CONFIG_H_ */
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