Yu Chien Peter Lin 8a0d5f2f51 riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode ... The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>		2023-10-04 18:23:54 +08:00
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andesv5	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	2023-10-04 18:23:54 +08:00
fu540	common: return type board_get_usable_ram_top	2023-08-15 18:21:17 +02:00
fu740	common: return type board_get_usable_ram_top	2023-08-15 18:21:17 +02:00
generic	common: return type board_get_usable_ram_top	2023-08-15 18:21:17 +02:00
jh7110	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	2023-09-05 10:53:46 +08:00
cpu.c	riscv: Correct event usage for riscv_cpu_probe/setup	2023-09-06 13:47:24 -04:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	2023-08-10 10:58:12 +08:00
u-boot-spl.lds	riscv: Update alignment for some sections in linker scripts	2023-04-20 20:45:08 +08:00
u-boot.lds	riscv: Fix alignment of RELA sections in the linker scripts	2023-06-27 10:09:51 +08:00