Shengyu Qu 64339bc1f2 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT ... Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-09-05 10:53:46 +08:00
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cpu.c	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
dram.c	common: return type board_get_usable_ram_top	2023-08-15 18:21:17 +02:00
Kconfig	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	2023-09-05 10:53:46 +08:00
Makefile	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
spl.c	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	2023-08-10 10:58:12 +08:00