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riscv: Move trap handler codes to mtrap.S
Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Bin Meng
Andes
parent
485e822346
commit
4b3f5ed5ac
3 changed files with 112 additions and 90 deletions
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@ -4,4 +4,4 @@
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extra-y = start.o
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obj-y += cpu.o
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obj-y += cpu.o mtrap.o
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111
arch/riscv/cpu/mtrap.S
Normal file
111
arch/riscv/cpu/mtrap.S
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@ -0,0 +1,111 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* M-mode Trap Handler Code for RISC-V Core
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*
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* Copyright (c) 2017 Microsemi Corporation.
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* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
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*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <asm/encoding.h>
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#ifdef CONFIG_32BIT
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#define LREG lw
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#define SREG sw
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#define REGBYTES 4
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#else
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#define LREG ld
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#define SREG sd
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#define REGBYTES 8
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#endif
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.text
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/* trap entry */
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.align 2
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.global trap_entry
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trap_entry:
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addi sp, sp, -32 * REGBYTES
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SREG x1, 1 * REGBYTES(sp)
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SREG x2, 2 * REGBYTES(sp)
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SREG x3, 3 * REGBYTES(sp)
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SREG x4, 4 * REGBYTES(sp)
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SREG x5, 5 * REGBYTES(sp)
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SREG x6, 6 * REGBYTES(sp)
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SREG x7, 7 * REGBYTES(sp)
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SREG x8, 8 * REGBYTES(sp)
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SREG x9, 9 * REGBYTES(sp)
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SREG x10, 10 * REGBYTES(sp)
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SREG x11, 11 * REGBYTES(sp)
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SREG x12, 12 * REGBYTES(sp)
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SREG x13, 13 * REGBYTES(sp)
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SREG x14, 14 * REGBYTES(sp)
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SREG x15, 15 * REGBYTES(sp)
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SREG x16, 16 * REGBYTES(sp)
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SREG x17, 17 * REGBYTES(sp)
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SREG x18, 18 * REGBYTES(sp)
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SREG x19, 19 * REGBYTES(sp)
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SREG x20, 20 * REGBYTES(sp)
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SREG x21, 21 * REGBYTES(sp)
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SREG x22, 22 * REGBYTES(sp)
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SREG x23, 23 * REGBYTES(sp)
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SREG x24, 24 * REGBYTES(sp)
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SREG x25, 25 * REGBYTES(sp)
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SREG x26, 26 * REGBYTES(sp)
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SREG x27, 27 * REGBYTES(sp)
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SREG x28, 28 * REGBYTES(sp)
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SREG x29, 29 * REGBYTES(sp)
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SREG x30, 30 * REGBYTES(sp)
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SREG x31, 31 * REGBYTES(sp)
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csrr a0, MODE_PREFIX(cause)
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csrr a1, MODE_PREFIX(epc)
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mv a2, sp
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jal handle_trap
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csrw MODE_PREFIX(epc), a0
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#ifdef CONFIG_RISCV_SMODE
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/* Remain in S-mode after sret */
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li t0, SSTATUS_SPP
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#else
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/* Remain in M-mode after mret */
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li t0, MSTATUS_MPP
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#endif
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csrs MODE_PREFIX(status), t0
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LREG x1, 1 * REGBYTES(sp)
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LREG x2, 2 * REGBYTES(sp)
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LREG x3, 3 * REGBYTES(sp)
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LREG x4, 4 * REGBYTES(sp)
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LREG x5, 5 * REGBYTES(sp)
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LREG x6, 6 * REGBYTES(sp)
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LREG x7, 7 * REGBYTES(sp)
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LREG x8, 8 * REGBYTES(sp)
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LREG x9, 9 * REGBYTES(sp)
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LREG x10, 10 * REGBYTES(sp)
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LREG x11, 11 * REGBYTES(sp)
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LREG x12, 12 * REGBYTES(sp)
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LREG x13, 13 * REGBYTES(sp)
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LREG x14, 14 * REGBYTES(sp)
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LREG x15, 15 * REGBYTES(sp)
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LREG x16, 16 * REGBYTES(sp)
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LREG x17, 17 * REGBYTES(sp)
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LREG x18, 18 * REGBYTES(sp)
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LREG x19, 19 * REGBYTES(sp)
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LREG x20, 20 * REGBYTES(sp)
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LREG x21, 21 * REGBYTES(sp)
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LREG x22, 22 * REGBYTES(sp)
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LREG x23, 23 * REGBYTES(sp)
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LREG x24, 24 * REGBYTES(sp)
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LREG x25, 25 * REGBYTES(sp)
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LREG x26, 26 * REGBYTES(sp)
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LREG x27, 27 * REGBYTES(sp)
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LREG x28, 28 * REGBYTES(sp)
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LREG x29, 29 * REGBYTES(sp)
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LREG x30, 30 * REGBYTES(sp)
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LREG x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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MODE_PREFIX(ret)
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@ -198,92 +198,3 @@ call_board_init_r:
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* jump to it ...
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*/
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jr t4 /* jump to board_init_r() */
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/*
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* trap entry
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*/
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.align 2
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trap_entry:
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addi sp, sp, -32*REGBYTES
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SREG x1, 1*REGBYTES(sp)
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SREG x2, 2*REGBYTES(sp)
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SREG x3, 3*REGBYTES(sp)
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SREG x4, 4*REGBYTES(sp)
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SREG x5, 5*REGBYTES(sp)
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SREG x6, 6*REGBYTES(sp)
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SREG x7, 7*REGBYTES(sp)
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SREG x8, 8*REGBYTES(sp)
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SREG x9, 9*REGBYTES(sp)
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SREG x10, 10*REGBYTES(sp)
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SREG x11, 11*REGBYTES(sp)
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SREG x12, 12*REGBYTES(sp)
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SREG x13, 13*REGBYTES(sp)
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SREG x14, 14*REGBYTES(sp)
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SREG x15, 15*REGBYTES(sp)
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SREG x16, 16*REGBYTES(sp)
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SREG x17, 17*REGBYTES(sp)
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SREG x18, 18*REGBYTES(sp)
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SREG x19, 19*REGBYTES(sp)
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SREG x20, 20*REGBYTES(sp)
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SREG x21, 21*REGBYTES(sp)
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SREG x22, 22*REGBYTES(sp)
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SREG x23, 23*REGBYTES(sp)
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SREG x24, 24*REGBYTES(sp)
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SREG x25, 25*REGBYTES(sp)
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SREG x26, 26*REGBYTES(sp)
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SREG x27, 27*REGBYTES(sp)
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SREG x28, 28*REGBYTES(sp)
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SREG x29, 29*REGBYTES(sp)
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SREG x30, 30*REGBYTES(sp)
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SREG x31, 31*REGBYTES(sp)
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csrr a0, MODE_PREFIX(cause)
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csrr a1, MODE_PREFIX(epc)
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mv a2, sp
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jal handle_trap
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csrw MODE_PREFIX(epc), a0
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#ifdef CONFIG_RISCV_SMODE
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/*
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* Remain in S-mode after sret
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*/
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li t0, SSTATUS_SPP
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#else
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/*
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* Remain in M-mode after mret
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*/
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li t0, MSTATUS_MPP
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#endif
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csrs MODE_PREFIX(status), t0
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LREG x1, 1*REGBYTES(sp)
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LREG x2, 2*REGBYTES(sp)
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LREG x3, 3*REGBYTES(sp)
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LREG x4, 4*REGBYTES(sp)
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LREG x5, 5*REGBYTES(sp)
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LREG x6, 6*REGBYTES(sp)
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LREG x7, 7*REGBYTES(sp)
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LREG x8, 8*REGBYTES(sp)
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LREG x9, 9*REGBYTES(sp)
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LREG x10, 10*REGBYTES(sp)
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LREG x11, 11*REGBYTES(sp)
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LREG x12, 12*REGBYTES(sp)
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LREG x13, 13*REGBYTES(sp)
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LREG x14, 14*REGBYTES(sp)
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LREG x15, 15*REGBYTES(sp)
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LREG x16, 16*REGBYTES(sp)
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LREG x17, 17*REGBYTES(sp)
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LREG x18, 18*REGBYTES(sp)
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LREG x19, 19*REGBYTES(sp)
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LREG x20, 20*REGBYTES(sp)
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LREG x21, 21*REGBYTES(sp)
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LREG x22, 22*REGBYTES(sp)
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LREG x23, 23*REGBYTES(sp)
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LREG x24, 24*REGBYTES(sp)
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LREG x25, 25*REGBYTES(sp)
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LREG x26, 26*REGBYTES(sp)
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LREG x27, 27*REGBYTES(sp)
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LREG x28, 28*REGBYTES(sp)
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LREG x29, 29*REGBYTES(sp)
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LREG x30, 30*REGBYTES(sp)
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LREG x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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MODE_PREFIX(ret)
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