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riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT

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Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
would be triggered. Currently, we use DDR ram for SPL malloc arena on
Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
SPL malloc arena. To avoid triggering ECC error in this scenario, we
imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Shengyu Qu 2023-08-25 00:25:20 +08:00 committed by Leo Yu-Chi Liang
parent c9db9a2ef5
commit 64339bc1f2
1 changed files with 1 additions and 0 deletions
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1
arch/riscv/cpu/jh7110/Kconfig
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@ -28,3 +28,4 @@ config STARFIVE_JH7110
imply SPL_LOAD_FIT
imply SPL_OPENSBI
imply SPL_RISCV_ACLINT
imply SPL_SYS_MALLOC_CLEAR_ON_INIT