riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.

Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Yu Chien Peter Lin 2023-09-29 12:03:07 +08:00 committed by Leo Yu-Chi Liang
parent 5f25297637
commit 8a0d5f2f51
3 changed files with 11 additions and 3 deletions

View file

@ -4,8 +4,9 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply ANDES_PLMT_TIMER
imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply V5L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI

View file

@ -59,7 +59,14 @@ config ALTERA_TIMER
config ANDES_PLMT_TIMER
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
depends on RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config SPL_ANDES_PLMT_TIMER
bool
depends on SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.

View file

@ -4,7 +4,7 @@
obj-y += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o