Heinrich Schuchardt 9385c9b0cd riscv: remove dram_init_banksize() ... Remove dram_init_banksize() on the architecture level. Limiting used RAM to under 4 GiB is only necessary for CPUs which have a DMA issue. SoC specific code already exists for FU540, FU740, JH7110. Not all RISC-V boards will have memory below 4 GiB. A weak implementation of dram_init_banksize() exists in common/board_f.c. See the discussion in https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>		2023-10-19 17:29:32 +08:00
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andesv5	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	2023-10-04 18:23:54 +08:00
fu540	common: return type board_get_usable_ram_top	2023-08-15 18:21:17 +02:00
fu740	common: return type board_get_usable_ram_top	2023-08-15 18:21:17 +02:00
generic	riscv: remove dram_init_banksize()	2023-10-19 17:29:32 +08:00
jh7110	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	2023-09-05 10:53:46 +08:00
cpu.c	riscv: Correct event usage for riscv_cpu_probe/setup	2023-09-06 13:47:24 -04:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	2023-08-10 10:58:12 +08:00
u-boot-spl.lds	riscv: Update alignment for some sections in linker scripts	2023-04-20 20:45:08 +08:00
u-boot.lds	riscv: Fix alignment of RELA sections in the linker scripts	2023-06-27 10:09:51 +08:00