Randolph 04b2123b4d riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy ... Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-10-19 17:29:33 +08:00
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cpu	riscv: remove dram_init_banksize()	2023-10-19 17:29:32 +08:00
dts	riscv: binman: Fix compilation error	2023-10-19 17:29:32 +08:00
include/asm	Merge branch 'next'	2023-10-02 10:55:44 -04:00
lib	riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy	2023-10-19 17:29:33 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	configs: andes: add vender prefix for target name	2023-10-04 18:00:51 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00