Ajay Kumar 1673f199d9 EXYNOS5: Change parent clock of FIMD to MPLL ... With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2013-01-10 10:19:47 +09:00
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clock.c	EXYNOS5: Change parent clock of FIMD to MPLL	2013-01-10 10:19:47 +09:00
Makefile	EXYNOS5: PINMUX: Added default pinumx settings	2012-07-07 14:07:25 +02:00
pinmux.c	EXYNOS5: FDT : Decode peripheral id	2013-01-08 10:54:32 +09:00
power.c	EXYNOS5: support display port phy control function	2012-09-01 14:58:24 +02:00
soc.c	arm:exynos: Enable data cache at exynos based processors.	2012-09-01 14:58:24 +02:00
system.c	EXYNOS5: support display system register control	2012-09-01 14:58:24 +02:00