Ajay Kumar 1673f199d9 EXYNOS5: Change parent clock of FIMD to MPLL ... With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2013-01-10 10:19:47 +09:00
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cpu	EXYNOS5: Change parent clock of FIMD to MPLL	2013-01-10 10:19:47 +09:00
dts	EXYNOS5: Add device node for USB.	2013-01-08 21:14:34 +09:00
imx-common	imx-common: cpu: add imx_ddr_size	2012-11-10 08:15:40 +01:00
include/asm	EXYNOS5: Add support for FIMD and DP	2013-01-10 10:19:47 +09:00
lib	Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged	2012-12-19 13:02:36 -08:00
config.mk	arm: work around assembler bug	2012-10-04 14:19:04 +02:00