Commit graph

174 commits

Author SHA1 Message Date
Bin Meng
cdcc17d73d x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:05 -08:00
Bin Meng
9d74f03460 x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
5c564b0d2f x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
b2439aecd3 x86: fsp: Drop get_hob_type() and get_hob_length()
These two are not worth having separate inline functions as they are
really simple, so drop them.

Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
c72f74e278 x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.

For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
801d70ce02 x86: Disable CAR before relocation on platforms that need it
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
7b00896ade x86: ivybridge: Add a way to turn off the CAR
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
aaafcd6c3f x86: ivybridge: Request MTRRs for DRAM regions
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
9818a00eea x86: ivybridge: Set up an MTRR for the video frame buffer
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
aff2523f69 x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
3a5659f7cf x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
d19ee5c27e x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is
not considered at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Bin Meng
949dbc12db x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
8f9052fd98 pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
fa5530b85d x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
4722c035cf x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
255fd5caa5 x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
aada6276c6 x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
adfe3b247a x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
8c5224c9f5 x86: Use consistent name XXX_ADDR for binary blob flash address
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
58f542de30 x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
240a79d95c x86: Enable the queensbay cpu directory build
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Simon Glass
0f61de8d9d x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:06 -07:00
Bin Meng
b2e02d2865 x86: Add basic support to queensbay platform and crownbay board
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Simon Glass
b591ee3913 x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.

Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
cf29e3e303 x86: ivybridge: Update the microcode
There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Bin Meng
bceb9f0fc8 x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
95a5a47466 x86: Add post failure codes for bist and car
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
8e04d4c537 x86: queensbay: Adapt FSP support codes
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 22:32:05 -07:00
Bin Meng
752a0b085b x86: Initial import from Intel FSP release for Queensbay platform
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.

For more details, check http://www.intel.com/fsp.

Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 22:32:05 -07:00
Bin Meng
fe0c33a5ac x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
e34aef1de3 x86: Add GDT descriptors for option ROMs
Option ROMs require a few additional descriptors. Add these, and remove the
enum since we now have to access several descriptors from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
24774278c9 x86: ivybridge: Add northbridge init functions
Add init for the northbridge, another part of the platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
0c9075e9ad x86: Add LAPIC setup code
Add code to set up the Local Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:11 -07:00
Simon Glass
b636dd1079 x86: Drop old CONFIG_INTEL_CORE_ARCH code
This is no-longer used, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:03 -07:00
Bin Meng
1dae2e0eb6 x86: Refactor interrupt_init()
Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
a549f7497b x86: Remove cpu_init_r() for x86
Since cpu_init_interrupts() was moved out of cpu_init_r(), it is
useless to keep cpu_init_r() for x86, thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
4372a9eca5 x86: Call cpu_init_interrupts() from interrupt_init()
Currently cpu_init_interrupts() is called from cpu_init_r() to
setup the interrupt and exception of the cpu core, but at that
time the i8259 has not been initialized to mask all the irqs
and remap the master i8259 interrupt vector base, so the whole
system is at risk of being interrupted, and if interrupted,
wrong interrupt/exception message is shown.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
18739e2ccc x86: Add Intel speedstep and turbo mode code
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
a6d4c45306 x86: ivybridge: Set up XHCI USB
Add init for XHCI so that high-speed USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
9baeca4b89 x86: ivybridge: Set up EHCI USB
Add init for EHCI so that USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
3ac839352d x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
72cd085aae x86: ivybridge: Add additional LPC init
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
8c74a57318 x86: ivybridge: Add PCH init
Add required init for the Intel Platform Controller Hub in ivybridge.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
4e7a6acac7 x86: ivybridge: Add support for BD82x6x PCH
Add basic setup for the PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
e94ea6f656 x86: pci: Add handlers before and after a PCI hose scan
Some boards will want to do some setup before and after a PCI hose
is scanned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:00 -07:00
Simon Glass
a6a957849a x86: Factor out common values in the link script
Define the reset base in config.mk so that it does not need to be calculated
twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values
to fit with this new approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00