u-boot/arch/x86/cpu
Bin Meng bceb9f0fc8 x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
..
coreboot Replace <compiler.h> with <linux/compiler.h> 2014-12-08 09:35:46 -05:00
ivybridge x86: Add post failure codes for bist and car 2014-12-13 22:32:05 -07:00
queensbay x86: queensbay: Adapt FSP support codes 2014-12-13 22:32:05 -07:00
call64.S x86: Add support for starting 64-bit kernel 2014-10-28 20:43:47 -06:00
config.mk x86: Factor out common values in the link script 2014-11-25 06:33:59 -07:00
cpu.c x86: Add GDT descriptors for option ROMs 2014-11-25 06:34:14 -07:00
interrupts.c x86: Drop old CONFIG_INTEL_CORE_ARCH code 2014-11-25 06:34:03 -07:00
lapic.c x86: Add LAPIC setup code 2014-11-25 06:34:11 -07:00
Makefile x86: Add LAPIC setup code 2014-11-25 06:34:11 -07:00
pci.c x86: pci: Add handlers before and after a PCI hose scan 2014-11-25 06:34:00 -07:00
resetvec.S Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
start.S x86: Support Intel FSP initialization path in start.S 2014-12-13 22:32:05 -07:00
start16.S x86: Save the BIST value on reset 2014-11-21 07:24:10 +01:00
turbo.c x86: Add Intel speedstep and turbo mode code 2014-11-25 06:34:02 -07:00
u-boot.lds x86: Factor out common values in the link script 2014-11-25 06:33:59 -07:00