Commit graph

20724 commits

Author SHA1 Message Date
Bin Meng
18cb82c35c riscv: dts: Sort build targets in alphabetical order
Sort the RISC-V DTS build targets by their Kconfig target names in
alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19 17:01:50 +08:00
Bin Meng
0784510f74 riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19 17:01:50 +08:00
Michal Simek
a502a87bc0 arm64: zynqmp: Add description for SOM/Kria boards
The patch contains several DT files for SOM platform.
Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter
kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC.

Files are divided in this way to make sure that SOM can be plugged to
different carrier card and all peripherals on SOM (or defined by a spec) can
be used by U-Boot. Full DT for SOM+CC can be merged together as overlays.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
3195840c94 arm64: zynqmp: Add psgtr DT descriptions
Mainline kernel has psgtr driver that's why it is good to add description
to DT files. Some boards are just missing description for USB3 and sata.
zc1751-dc1 and p-a2197 are also missing clock descriptions for input
clocks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
bd00849ae9 arm64: zynqmp: Add pinctrl description
ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it
DT files can be extended by pinctrl configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
T Karthik Reddy
50a6bd000f arm64: zynqmp: Add zynqmp firmware specific DT nodes
Probe zynqmp firmware driver by adding zynqmp firmware, power &
ipi mailbox device tree nodes for mini emmc.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
26d8eccea7 arm64: zynqmp: Add missing mio-bank properties to sdhci
Add missing xlnx,mio-bank property to sdhci node. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
fddff6815a arm64: zynqmp: Remove comment about clock chips
These comments weren't push to mainline that's why remove them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Raviteja Narayanam
486f25c727 arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property
I2C muxes that have the slave devices with same address are
falling into the below problem.

VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts
I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50
I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50

1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then
2. SC accesses I2C1 - Mux2 (0x75) - Channel 0.

Now it results in 2 slave devices with same address (0x50)
on the I2C bus, making the communication un-reliable.

When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux
channel output is disconnected, making none of the channels
available to the I2C1. So, there is no question of having the
same addressed slave (0x50) present on the bus when we are doing '2'.

Same pattern is seen in below two boards also.

ZCU208 - zynqmp-zcu208-revA.dts
ZCU216 - zynqmp-zcu216-revA.dts

Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
2021-05-19 09:44:50 +02:00
Saeed Nowshadi
000b862325 arm64: zynqmp: Add label to all GPIO lines for VCK190 SC
Add label to GPIO lines so the user-level applications can find any line
without knowing its physical path on System Controller on VCK190/VMK180.

These labels are describing EMIO gpio connection which depends on PL which
we normally don't describe but that's only way to go for now. Lately this
should be done out of this source code.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Saeed Nowshadi
65a572b1d0 arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node
The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed.  Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
a34a12fabc arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodes
All si570 which are used for ps reference clock generation should contain
silabs,skip-recall property not to cause break on ps clock.
On Versal boards this will cause hang on Versal cpu when it is booted at
the same time with SC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Tom Rini
52993fcb76 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-05-18 11:09:41 -04:00
Bin Meng
89419279f4 riscv: Group assembly optimized implementation of memory routines into a submenu
Currently all assembly optimized implementation of memory routines
show up at the top level of the RISC-V architecture Kconfig menu.
Let's group them together into a submenu.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-17 16:47:33 +08:00
Bin Meng
703b84ec29 riscv: Fix memmove and optimise memcpy when misalign
At present U-Boot SPL fails to boot on SiFive Unleashed board, due
to a load address misaligned exception happens when loading the FIT
image in spl_load_simple_fit(). The exception happens in memmove()
which is called by fdt_splice_().

Commit 8f0dc4cfd1 introduces an assembly version of memmove but
it does take misalignment into account (it checks if length is a
multiple of machine word size but pointers need also be aligned).
As a result it will generate misaligned load/store for the majority
of cases and causes significant performance regression on hardware
that traps misaligned load/store and emulate them using firmware.

The current behaviour of memcpy is that it checks if both src and
dest pointers are co-aligned (aka congruent modular SZ_REG). If
aligned, it will copy data word-by-word after first aligning
pointers to word boundary. If src and dst are not co-aligned,
however, byte-wise copy will be performed.

This patch was taken from the Linux kernel patch [1], which has not
been applied at the time being. It fixes the memmove and optimises
memcpy for misaligned cases. It will first align destination pointer
to word-boundary regardless whether src and dest are co-aligned or
not. If they indeed are, then wordwise copy is performed. If they
are not co-aligned, then it will load two adjacent words from src
and use shifts to assemble a full machine word. Some additional
assembly level micro-optimisation is also performed to ensure more
instructions can be compressed (e.g. prefer a0 to t6).

With this patch, U-Boot boots again on SiFive Unleashed board.

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/

Fixes: 8f0dc4cfd1 ("riscv: assembler versions of memcpy, memmove, memset")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-17 16:47:33 +08:00
Sean Anderson
e90cb0db34 riscv: Fix arch_fixup_fdt always failing without /chosen
If /chosen was missing, chosen_offset would never get updated with the new
/chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes
this by setting chosen_offset. In addition, log any errors from setting
boot-hartid as well.

Fixes: 5370478d1c ("riscv: Add boot hartid to device tree")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2021-05-17 16:46:33 +08:00
Bin Meng
a6d7e8c914 riscv: Split SiFive CLINT support between SPL and U-Boot proper
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-05-17 16:42:24 +08:00
Konstantin Porotchkin
f29eaadeb5 arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Grzegorz Jaszczyk
7d8e1651da arm64: mvebu: extend the mmio region
Some of the setups including cn9130 opens mmio window starting from
0xc0000000, reflect it in the u-boot code.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Grzegorz Jaszczyk
32a1a5b374 arm64: mvebu: a8k: move firmware related definitions to fw info
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Grzegorz Jaszczyk
a2122d8bab arm64: mvebu: do not map firmware RT service region
There is region left by ATF, which needs to remain in memory to provide RT
services. To prevent overwriting it by u-boot, do not provide any mapping
for this memory region, so any attempt to access it will trigger
synchronous exception.

Update sr 2021-04-12:
Don't update armada3700/cpu.c mmu table, as this has specific changes
included in mainline.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
jinghua
762f9fba0f arm64: mvebu: a8k: align memory regions
1. RAM: base address 0x0 size 2Gbytes
2. MMIO: base address 0xf0000000 size 1Gbytes

Signed-off-by: Ofir Fedida <ofedida@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Tom Rini
8054d80b04 Merge https://source.denx.de/u-boot/custodians/u-boot-sh 2021-05-14 23:00:24 -04:00
Tom Rini
666afca0df - dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
 - net: dwmac_meson8b: do not set TX delay in TXID & RXID
 - net: designware: meson8b: add g12a compatible
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Merge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
- net: dwmac_meson8b: do not set TX delay in TXID & RXID
- net: designware: meson8b: add g12a compatible
2021-05-14 22:59:59 -04:00
Neil Armstrong
d39620e045 ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
This lacks the right u-boot specific DT include to make HDMI work.

Reported-by: B1oHazard <ty3uk@mail.ua>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14 17:41:11 +02:00
Bin Meng
ffdc71bc09 Revert "riscv: cpu: fu740: clear feature disable CSR"
This reverts commit bc8bbb77f7.

This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-14 16:26:20 +08:00
Sean Anderson
81dadfa4bc riscv: Don't reserve AI ram in k210 dts
It is no longer necessary to disallow ai ram, since it is enabled by the
sram driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:50 +08:00
Sean Anderson
2111f4e8bf riscv: k210: Use AI as the parent clock of aisram, not PLL1
Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:49 +08:00
Sean Anderson
2d64e3829b riscv: k210: Rename airam to aisram
This is more consistent with the naming of other ram banks, and matches
what Linux is doing.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:49 +08:00
Sean Anderson
2eebe5b373 riscv: Enable some devices pre-relocation
These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:48 +08:00
Kory Maincent
1569847e7c am335x: add support for cape detect functionality
Update the Kconfig and the board file to make the am335x board compatible
with cape detection.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
d705527a89 arm: am335x: add support for i2c2 bus
The am335x from BeagleBone use i2c EEPROM to detect capes.
The memory is wired to i2c bus 2 therefore it need to be enabled.

Add i2c2 clock, pinmux description and pinmux enable function.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
6c2c7e9cb9 arm: sunxi: add support for DIP detection to CHIP board
Add the extension_board_scan specific function to scan the information
of the EEPROM on one-wire and fill the extension struct.
Add the Kconfig symbol to enable the needs to detect DIPs.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
0705e25cd0 am57xx: add support for cape detect functionality
This commit enables using the extension board detection mechanism on
AM57xx based platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
95300f203f pytest: add sandbox test for "extension" command
This commit extends the sandbox to implement a dummy
extension_board_scan() function and enables the extension command in
the sandbox configuration. It then adds a test that checks the proper
functionality of the extension command by applying two Device Tree
overlays to the sandbox Device Tree.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
[trini: Limit to running on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-13 13:09:09 -04:00
Marek Vasut
8f76c9d73a ARM: renesas: Scrub duplicate memory nodes from DT on Gen3
Scrub duplicate /memory@* node entries here. Some R-Car DTs might
contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
either generates single /memory node or updates the first /memory
node. Any remaining memory nodes are thus potential duplicates.

However, it is not possible to delete all the memory nodes right
away, since some of those might not be DRAM memory nodes, but some
sort of other memory. Thus, delete only the memory nodes which are
in the R-Car3 DBSC ranges.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-12 21:36:27 +02:00
Tom Rini
ea184cbff9 Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
2021-05-12 10:07:21 -04:00
Vignesh Raghavendra
bbc9da58b3 ARM: dts: k3-am642-sk: Add ethernet related DT nodes
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Vignesh Raghavendra
bc17fccbd0 ARM: dts: k3-am64-main: Add CPSW DT nodes
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).

Disable second port as its by default set to ICSS usage on EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Lokesh Vutla
a66b9149a3 arm: dts: am642-r5-sk: Add r5 specific dts
Add R5 specific dts for AM64 SK

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2021-05-12 16:36:38 +05:30
Lokesh Vutla
c88a9ae1fe arm: dts: am642-sk: Add initial sk dts
AM642 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM642 SoC. It supports the following interfaces:
* 2 GB LPDDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode
* x1 USB 3.0 Type-A port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x2 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin Raspberry Pi compatible GPIO header
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 54-pin header for Programmable Realtime Unit (PRU) IO pins
* Interface for remote automation. Includes:
	* power measurement and reset control
	* boot mode change

Add basic support for AM642 SK.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:36:38 +05:30
Lokesh Vutla
45b7a9fc08 arm: dts: am642-evm: Add I2C nodes
Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Lokesh Vutla
e922b5a963 arm: dts: k3-am642-r5-evm: Do not use power-domains for I2C
I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for I2C.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Lokesh Vutla
93e0bfb829 arm: dts: k3-am64-evm: Make chip id available before pre-reloc
Chipid will be needed for SoC detection for all stages of U-Boot.
So make it u-boot,dm-spl

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Lokesh Vutla
b5425a9676 arm: am64x: Add support for selecting DT based on EEPROM
Enable support for selecting DTB within SPL based on EEPROM.
This will help to use single defconfig for both EVM and SK

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Lokesh Vutla
2ee76314a7 board: ti: am64x: Add support for reading eeprom data
I2C EEPROM data contains the board name and its revision.
Add support for:
- Reading EEPROM data and store a copy at end of SRAM
- Updating env variable with relevant board info
- Printing board info during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Nishanth Menon
ab4c072ddd arm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulator
Add DDR VTT regulator.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:31:16 +05:30
Nishanth Menon
d3fd37b8a1 arm: dts: k3-am64-main: Add GPIO nodes
Add main domain GPIO nodes.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:31:16 +05:30
Dave Gerlach
d411f0973a arm: mach-k3: am642: Add support for triggering ddr init from SPL
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:31:16 +05:30
Dave Gerlach
fe0f3e3697 arm: dts: k3-am642: Add ddr node
Introduce ddr node for am642 needed for all ddr configurations.

Also, introduce the 1600MTs DDR4 configuration that is supported on the
am642-evm.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:31:15 +05:30
Dave Gerlach
b6059ddc45 arm: dts: k3-am642: Add r5 specific dt support
Add initial support for dt that runs on r5.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:28 +05:30
Dave Gerlach
5db2915a72 arm: dts: k3-am642: Add initial support for EVM
The AM642 EValuation Module (EVM) is a board that provides access to
various peripherals available on the AM642 SoC, such as PCIe, USB 2.0,
CPSW Ethernet, ADC, and more.

Add basic support.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
58211db0a8 arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
33b7258947 board: ti: am64x: Add board support for am64x evm
Add board specific initialization for am64x based boards.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Keerthy
7fe7713c2e armv8: mach-k3: am642: Add custom MMU support
Change the memory attributes for the DDR regions used by the remote
processors on AM65x so that the cores can see and execute the proper code.

A separate table based on the previous K3 SoCs is introduced since the
number of remote processors and their DDR usage is different between the
SoC families.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Suman Anna
078332cee3 arm: mach-k3: am642: Shut down R5 core after ATF startup on A53
The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs
the R5 SPL that performs the initialization of the System Controller
processor and starting the Arm Trusted Firmware (ATF) on the Arm
Cortex A53 cluster. The Core0 serves as this boot processor and is
parked in WFE after all the initialization. Core1 does not directly
participate in the boot flow, and is simply parked in a WFI.

Power down these R5 cores (and the associated RTI timer resources
that were indirectly powered up) after starting up ATF on A53 by
using the appropriate SYSFW API in release_resources_for_core_shutdown().
This allows these Main R5F cores to be further controlled from the
A53 to run regular applications.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
f4686c3d5b arm: mach-k3: am642: Use mmc start and stop callbacks
To avoid any glitches on MMC clock line, make use of pm per and post
callbacks when loading sysfw.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
d2edabfa8d arm: mach-k3: am642: Load SYSFW binary and config from boot media
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the AM642 early initialization sequence. Also
make use of existing logic to detect if ROM has already loaded sysfw
and avoided attempting to reload and instead just prepare to use already
running firmware.

While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW
to print diagnostic messages.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
6d52c9dd90 arm: mach-k3: am642: Store boot info from ROM
For AM642, ROM supports loading system firmware directly
from boot image. ROM passes information about the number of
images that are loaded to bootloader at a specific address
that is temporary.  Add support for storing this information
somewhere permanent before it gets corrupted.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
b4a8c3b242 arm: mach-k3: am642: Unlock all applicable control MMR registers
To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MAIN domain.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Keerthy
57dba04afb arm: mach-k3: am642: Add support for boot device detection
AM642 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
eb54168bb0 arm: mach-k3: Add basic support for AM642 SoC definition
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dario Binacchi
a47abd7bf4 Revert "fdt: translate address if #size-cells = <0>"
This reverts commit d64b9cdcd4.

As pointed by [1] and [2], the reverted patch made every DT 'reg'
property translatable. What the patch was trying to fix was fixed in a
different way from previously submitted patches which instead of
correcting the generic address translation function fixed the issue with
appropriate platform code.

[1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/
[2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-12 16:27:57 +05:30
Tom Rini
59a2b9e605 u-boot-imx-20210502
-------------------
 
 - mx6:   fixes for Ventana
 -        local fixes from maintainer
 - imx7d: Ronetix's iMX7-CM
 - imx8:  Ronetix iMX8MQ-CM
 	 Engicam i.Core MX8M
 	 Compulab iot-gate-imx8
 - Fixes i.MX8 documentation
 - Fixes phy usage with fec
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 =wVb3
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20210502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20210502
-------------------

- mx6:   fixes for Ventana
-        local fixes from maintainer
- imx7d: Ronetix's iMX7-CM
- imx8:  Ronetix iMX8MQ-CM
	 Engicam i.Core MX8M
	 Compulab iot-gate-imx8
- Fixes i.MX8 documentation
- Fixes phy usage with fec
2021-05-11 12:23:11 -04:00
Tom Rini
8c245fe7ea boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabled
There are a number of platforms that depend on a SATA driver that has
been converted to require AHCI but the platforms themselves are behind
on other migrations that would make it trivial to enable AHCI.  Disable
SATA in these cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-11 09:14:56 -04:00
Tom Rini
07b53103b7 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-05-07 08:57:32 -04:00
Green Wan
bc8bbb77f7 riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-05 16:11:27 +08:00
Green Wan
edd9ad8194 riscv: cpu: Add callback to init each core
Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-05 16:11:22 +08:00
Rasmus Villemoes
8c72842af5 sandbox: add test of CONFIG_ENV_IMPORT_FDT
Check that a variable defined in /config/environment is found in the
run-time environment, and that clearing fdt_env_path from within that
node works.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: Conditionalize the test being linked in]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-04 12:52:30 -04:00
Sean Anderson
1cbfed8d3e test: Add gpio-sysinfo test
This adds a test for the gpio-sysinfo driver.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04 07:57:18 -04:00
Ilko Iliev
7666cccf4f ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CM
Supported peripherals: Ethernet, eMMC, Serial.

U-Boot SPL 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14
+0200)
Normal Boot
Trying to boot from MMC2

U-Boot 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200)

CPU:   Freescale i.MX8MQ rev2.1 at 1000 MHz
Reset cause: POR
Model: Ronetix iMX8M-CM SoM
DRAM:  1 GiB
WDT:   Started with servicing (60s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 (eth0) using random MAC address -
42:0d:e7:78:da:53
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
u-boot=>

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2021-05-02 12:46:54 +02:00
Ilko Iliev
fdd2f359e4 imx: Add support for Ronetix's iMX7-CM board
Console boot log:

U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200)
Trying to boot from MMC1

U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200)

CPU:   Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 44C
Reset cause: POR
Model: Ronetix iMX7-CM Board
Board: iMX7-CM
DRAM:  512 MiB
PMIC:  PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2021-05-02 12:46:54 +02:00
Tim Harvey
35fc3713a3 imx: mkimage_fit_atf: fix file size reporting
instead using ls and awk to determine file size use stat instead.
This fixes an invalid size reporting for user or group names that have
spaces in them.

This adds a dependency on the stat application which is part of
the coreutils package which also includes ls.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-05-02 12:46:54 +02:00
Ying-Chun Liu (PaulLiu)
53b516c58d arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate)
Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate).
The initial support includes:
 - MMC
 - eMMC
 - I2C
 - FEC
 - Serial console

Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>
2021-05-02 12:46:54 +02:00
Ying-Chun Liu (PaulLiu)
8350211af4 arm: dts: add imx8mm-cl-iot-gate dts file
Add board dts for imx8mm-cl-iot-gate

Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>
2021-05-02 12:46:54 +02:00
Tim Harvey
566c537c60 arm: dts: imx6qdl-gw552x.dtsi: fix VBUS supply
Remove the invalid 'regulator-always-on' property to resolve:
starting USB...
Bus usb@2184000: Error enabling VBUS supply (ret=-13)
probe failed, error -13
Bus usb@2184200: USB EHCI 1.00

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-05-02 12:46:54 +02:00
Jagan Teki
7e0daa924a board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Linux dts commit details:

commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
C.TOUCH 2.0")

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2021-05-02 12:46:54 +02:00
Jagan Teki
e3409a4cb7 board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

Linux dts commit details:

commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
EDIMM2.2 Starter Kit")

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2021-05-02 12:46:54 +02:00
Jagan Teki
b6c332c6fd arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.

General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features

i.Core MX8M Mini needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Linux dts commit details:

commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
SoM")

Add support for it.

Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2021-05-02 12:46:54 +02:00
Jagan Teki
c1f09505d5 arm64: dts: imx8mm: Add common -u-boot.dtsi
/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m

are common node enablements across imx8mm platform for dm-spi,
dm-pre-reloc stages.

Move them into common dtsi, imx8mm-u-boot.dtsi

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2021-05-02 12:46:54 +02:00
Sebastian Reichel
4ac026a937 board: ge: bx50v3: add phy reset GPIO
Add PHY's reset GPIO, so that U-Boot does a PHY hard reset.
This is needed, since the PHY might become unresponsive if
watchdog reboots the system while a transaction is ongoing.

The reset GPIO is added to the U-Boot specific DT files, since
the kernel does not setup the reserved registers correctly after
resetting the PHY and thus must not reset it.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2021-05-02 12:46:54 +02:00
Tom Rini
f3a0d2c1af Xilinx changes for v2021.07-rc2
xilinx:
 - Enable saving variables based on bootmode
 - Cleanup usb dfu setup and wire it up with usb bootmode
 - Fix bootscript address logic
 - Remove GD references (spi, Versal)
 - Enable capsule update
 
 clk:
 - Small Kconfig fix
 
 net:
 - Fix gmii2rgmii bridge binding
 
 usb:
 - Propagate error (dfu gadget)
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Merge tag 'xilinx-for-v2021.07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.07-rc2

xilinx:
- Enable saving variables based on bootmode
- Cleanup usb dfu setup and wire it up with usb bootmode
- Fix bootscript address logic
- Remove GD references (spi, Versal)
- Enable capsule update

clk:
- Small Kconfig fix

net:
- Fix gmii2rgmii bridge binding

usb:
- Propagate error (dfu gadget)
2021-04-29 11:31:06 -04:00
Igal Liberman
341e548eb8 phy: marvell: add support for SFI1
In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
a007f23626 phy: marvell: fix pll initialization for second utmi port
According to Design Reference Specification the PHY PLL and Calibration
register from PHY0 are shared for multi-port PHY. PLL control registers
inside other PHY channels are not used.

This commit reworks utmi device tree nodes in a way that common PHY PLL
registers are moved to main utmi node. Accordingly both child nodes
utmi-unit range is reduced and register offsets in utmi_phy.h are updated
to this change.

This fixes issues in scenarios when only utmi port1 was in use, which
resulted with lack of correct pll initialization.

Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Marcin Wojtas
5ed3dc27bb phy: marvell: cp110: remove unused definitions
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of
1.5G/3G/6.25G were referenced in the driver non configuration (dts)
was using it.

This patch removes unused definitions.

Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
2dbba24088 phy: marvell: rename comphy related definitions to COMPHY_XX
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.

This patch does the following changes:
 - PHY_TYPE_XX --> COMPHY_TYPE_XX
 - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
Stefan Roese
1c817c27e6 arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for now
Because of the incorrectly supported SGMII_2500 mode, this patch
disables eth2 for now until this issue will be fixed in mainline.

Also fix an incorrect comment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Marek Behun <marek.behun@nic.cz>
2021-04-29 07:45:23 +02:00
Konstantin Porotchkin
c405226c34 arm: octeontx2: Add Octeon TX2 CN9130 CRB support
This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB.
Not all interfaces are supported fully yet.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:45:13 +02:00
Konstantin Porotchkin
236f17ce14 arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN9130 CRB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
b1c81b4ced arm: armada: dts: Add support for ap807-based platforms
Add support for SoCs based on AP807 die.
Remove unused include file for Armada-8020 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
a0ba97e561 arm: armada: dts: Use a single dtsi for cp110 die description
Use a single dtsi file for CP110 die instead of master/slave.
Moving to single file will allow miltiple DTSI inclusions with
re-defined CP index and name.
This change will also allow support for SoCs containing more than
two CP110 dies on board.
Move pin control definitions from CP110 DTS to board DTS files

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Neil Armstrong
49f352dc33 test: reset: Extend base reset test to catch error
With this extended test, we get the following failure :

=> ut dm reset_base
Test: dm_test_reset_base: reset.c
test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2)
Test: dm_test_reset_base: reset.c (flat tree)
test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2)
Failures: 2

A fix is needed in reset_get_by_index_nodev() when introduced in [1].

[1] ea9dc35aab ("reset: Get the RESET by index without device")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-28 10:05:13 +02:00
Samuel Holland
2e1af1e3e7 arm: zimage: Use correct symbol to hide messages in SPL
When zImage support was added to SPL, the messages were hidden to reduce
code size. However, the wrong config symbol was used. Since this file is
only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden.

Use the correct symbol so the messages are printed in U-Boot proper.
Also use IS_ENABLED to drop the #ifdef.

Fixes: 431889d6ad ("spl: zImage support in Falcon mode")
Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
4b37a83dc4 powerpc: introduce CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD
When flush_cache() is called during boot on our ~7M kernel image, the
hundreds of thousands of WATCHDOG_RESET calls end up adding
significantly to boottime. Flushing a single cache line doesn't take
many microseconds, so doing these calls for every cache line is
complete overkill.

The generic watchdog_reset() provided by wdt-uclass.c actually
contains some rate-limiting logic that should in theory mitigate this,
but alas, that rate-limiting must be disabled on powerpc because of
its get_timer() implementation - get_timer() works just fine until
interrupts are disabled, but it just so happens that the "big"
flush_cache() call happens in the part of bootm where interrupts are
indeed disabled. [1] [2] [3]

I have checked with objdump that the generated code doesn't change
when this option is left at its default value of 0: gcc is smart
enough to see that the ">=" comparison is tautologically true, hence
all assignments to "flushed" are eliminated as dead stores.

On our board, setting the option to something like 65536 ends up
reducing total boottime by about 0.8 seconds.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/
[2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html
[3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
b18352f2ba powerpc: lib: remove leftover CONFIG_5xx
CONFIG_5xx hasn't existed since commit 5025897774 (powerpc, 5xx:
remove support for 5xx). Remove this last mention of it.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
17bd5cce7e allow opting out of WATCHDOG_RESET() from timer interrupt
Having WATCHDOG_RESET() called automatically from the timer interrupt
runs counter to the idea of a watchdog device - if the board runs into
an infinite loops with interrupts still enabled, the watchdog will
never fire.

When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more
complicated than just poking a few SOC-specific registers - it
involves accessing all kinds of global data, and if the interrupt
happens at the wrong time (say, in the middle of an WATCHDOG_RESET()
call from ordinary code), that can end up corrupting said global data.

Allow the board to opt out of calling WATCHDOG_RESET() from the timer
interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that
setting is currently nonsensical (it would be compile-time
divide-by-zero), it cannot affect any existing boards.

Add documentation for both the existing and extended meaning of
CONFIG_SYS_WATCHDOG_FREQ.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Andre Przywara
fbe127f7b5 sunxi: DT: A64: Update devicetree files from Linux 5.12
Import updated devicetree files from the Linux v5.12 release.

Besides some node and audio port renames this changes the PHY modes to
either rgmii-id or rgmii-txid. From the board files the Pinephone sees
a lot of updates.

This also adds the long missing USB PHY property for controller 0, which
allows the U-Boot PHY driver to eventually use port 0 in host mode
(pending another U-Boot patch).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2021-04-28 10:05:12 +02:00
Ivan Uvarov
c83f63ae54 sunxi: DT: R40: Update device tree files from Linux 5.12
Update R40 .dts{,i} and dt-binding headers to current version from kernel.

Files taken from Linux 5.12-rc1 release
(commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8)

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-28 10:05:12 +02:00
Aaron Williams
594312eb8b mips: octeon: ebb7304: Add support for some I2C devices
This patch adds support for the following I2C devices connected to
I2C bus 0 on the Octeon EBB7304:
- Dallas DS1337 RTC
- TLV EEPROM

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28 10:05:12 +02:00
Aaron Williams
0ba39cded6 mips: octeon: dts/dtsi: Change UART DT node to use clocks property
We already have a clock driver for MIPS Octeon. This patch changes the
Octeon DT nodes to supply the clock property via the clock driver
instead of using an hard-coded value, which is not correct in all cases.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28 10:05:12 +02:00
Stefan Roese
5d2d5c4f23 mips: octeon: Add Octeon III NIC23 board support
This patch adds the basic support for the PCIe target board equipped
with the Octeon III CN2350 SoC.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Stefan Roese
b8f0146473 mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node
Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28 10:05:12 +02:00
Stefan Roese
dd6d82150f mips: octeon: cpu.c: Enable AHCI/SATA support
For easy AHCI/ SATA integration, this patch adds board_ahci_enable()
for the MVEBU AHCI driver, which will be used by this platform. This
platform specific "enable" function will setup the proper endian
swapping in the AHCI controller so that it can be used by the common
AHCI code.

Additionally the endian swizzle entry for AHCI in
octeon_should_swizzle_table[] is removed, as this enabled the original
lowlevel code function, e.g. octeon_configure_qlm(), for the QLM setup
to work correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28 10:05:12 +02:00
Stefan Roese
47dedfb5b9 mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd
This patch adds the necessary platform infrastructure code, so that the
MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can
be used. This is e.g. the bootmem initialization in a compatible way to
the Marvell 2013 U-Boot, so that the exisiting PC remote tools like
"oct-remote-console" & "oct-remote-load" can be used. This is be done in
the newly introduced arch_misc_init(), which calls the necessary init
functions when enabled.

These patches are in preparation for the MIPS Octeon NIC23 board
support, which is a desktop PCIe target board enabling these features.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28 10:05:12 +02:00
Stefan Roese
5cbe3bb1e2 mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG defined
As DEBUG is no Kconfig symbol, we can't use the IS_ENABLED() macros.
This patch switches to the unfortunately necessary #ifdef usage again
to make it work correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Stefan Roese
a8e338a229 mips: octeon: cvmx-bootmem: Fix compare in "if" statement
While porting from the Marvell source, I introduced a bug by misplacing
the parenthesis. This patch fixes this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Stefan Roese
ae404af8dc mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h
This makes is easier to use this macro from non-DDR related files.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Stefan Roese
8e3a87578e mips: octeon: mrvl, cn73xx.dtsi: Add PCIe controller DT node
This patch adds the PCIe controller node to the MIPS Octeon 73xx dtsi
file.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Stefan Roese
1ba8d5fe88 mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT
Setting CONFIG_SYS_PCI_64BIT is needed for correct PCIe functionality on
MIPS Octeon.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Stefan Roese
c7cf89791b mips: octeon: Makefile: Enable building of the newly added C files
This patch adds the newly added C files to the Makefile to enable
compilation. This is done in a separate step, to not introduce build
breakage while adding the single files with potentially missing
externals.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Aaron Williams
fc6c9c50d1 mips: octeon: Add octeon_qlm.c
Import octeon_qlm.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Aaron Williams
107d3f5771 mips: octeon: Add octeon_fdt.c
Import octeon_fdt.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Aaron Williams
198cffde05 mips: octeon: Add cvmx-qlm.c
Import cvmx-qlm.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Aaron Williams
646ed331b6 mips: octeon: Add cvmx-pcie.c
Import cvmx-pcie.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Aaron Williams
a6d4ffc565 mips: octeon: Add cvmx-helper.c
Import cvmx-helper.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:12 +02:00
Aaron Williams
3b883dea28 mips: octeon: Add cvmx-helper-util.c
Import cvmx-helper-util.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
23753c6c4d mips: octeon: Add cvmx-helper-jtag.c
Import cvmx-helper-jtag.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
f9174d6a92 mips: octeon: Add cvmx-helper-fdt.c
Import cvmx-helper-fdt.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
b8eaf8c563 mips: octeon: Add cvmx-helper-cfg.c
Import cvmx-helper-cfg.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Stefan Roese
29d0897045 mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach
To match all other cvmx-* header, this patch moves the already existing
cvmx-lmcx-defs.h header one directory up.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Stefan Roese
cbcf35850a mips: octeon: Misc changes required because of the newly added headers
With the newly added headers and their restructuring (which macro is
defined where), some changes in the already existing Octeon files are
necessary. This patch makes the necessary changes.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
2335cf39f6 mips: octeon: Add misc remaining header files
Import misc remaining header files from 2013 U-Boot. These will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28 10:05:11 +02:00
Aaron Williams
78265141cb mips: octeon: Add cvmx-sso-defs.h header file
Import cvmx-sso-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
0ad3593fca mips: octeon: Add cvmx-sriox-defs.h header file
Import cvmx-sriox-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
1374315375 mips: octeon: Add cvmx-sriomaintx-defs.h header file
Import cvmx-sriomaintx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
fa84c78f74 mips: octeon: Add cvmx-smix-defs.h header file
Import cvmx-smix-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
9505a7cee5 mips: octeon: Add cvmx-sli-defs.h header file
Import cvmx-sli-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
0e686b39d5 mips: octeon: Add cvmx-sata-defs.h header file
Import cvmx-sata-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
0b4c6885a7 mips: octeon: Add cvmx-rst-defs.h header file
Import cvmx-rst-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
f56633987c mips: octeon: Add cvmx-pow-defs.h header file
Import cvmx-pow-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
50a7649a38 mips: octeon: Add cvmx-pko-defs.h header file
Import cvmx-pko-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
8ba9b0a24c mips: octeon: Add cvmx-pki-defs.h header file
Import cvmx-pki-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
784ad918d1 mips: octeon: Add cvmx-pip-defs.h header file
Import cvmx-pip-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
bbd0e2c75d mips: octeon: Add cvmx-pepx-defs.h header file
Import cvmx-pepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
8f8383880f mips: octeon: Add cvmx-pemx-defs.h header file
Import cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
def92cec9e mips: octeon: Add cvmx-pcsx-defs.h header file
Import cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
7d9f6609e1 mips: octeon: Add cvmx-pciercx-defs.h header file
Import cvmx-pciercx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
c7ccfde739 mips: octeon: Add cvmx-pcieepx-defs.h header file
Import cvmx-pcieepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
0b9dce59e6 mips: octeon: Add cvmx-npi-defs.h header file
Import cvmx-npi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
779f25eee5 mips: octeon: Add cvmx-mio-defs.h header file
Import cvmx-mio-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
cae9e5763f mips: octeon: Add cvmx-l2c-defs.h header file
Import cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
0a48b0bd63 mips: octeon: Add cvmx-ipd-defs.h header file
Import cvmx-ipd-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
c9084e5f39 mips: octeon: Add cvmx-gserx-defs.h header file
Import cvmx-gserx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
297a3d5850 mips: octeon: Add cvmx-gmxx-defs.h header file
Import cvmx-gmxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
fc3e91081c mips: octeon: Add cvmx-fpa-defs.h header file
Import cvmx-fpa-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:11 +02:00
Aaron Williams
f3b9767827 mips: octeon: Add cvmx-dtx-defs.h header file
Import cvmx-dtx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:10 +02:00
Aaron Williams
c5b1b18e4d mips: octeon: Add cvmx-dpi-defs.h header file
Import cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:10 +02:00
Aaron Williams
66b75ef6e7 mips: octeon: Add cvmx-dbg-defs.h header file
Import cvmx-dbg-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:10 +02:00
Aaron Williams
646af4d96c mips: octeon: Add cvmx-ciu-defs.h header file
Import cvmx-ciu-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:10 +02:00
Aaron Williams
e6ce36344d mips: octeon: Add cvmx-bgxx-defs.h header file
Import cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:10 +02:00