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phy: marvell: add support for SFI1
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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a007f23626
commit
341e548eb8
10 changed files with 26 additions and 22 deletions
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@ -132,7 +132,8 @@
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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phy3 {
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@ -154,7 +154,7 @@
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* CP0 Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: Not connected
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* Lane 2: SFI (10G)
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* Lane 2: SFI0 (10G)
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* Lane 3: Not connected
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* Lane 4: USB 3.0 host port1 (can be PCIe)
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* Lane 5: Not connected
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@ -166,7 +166,7 @@
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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@ -95,7 +95,7 @@
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SATA1>;
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@ -194,7 +194,7 @@
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SATA1>;
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@ -183,7 +183,7 @@
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SATA1>;
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@ -299,7 +299,7 @@
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phy-type = <COMPHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SGMII2>;
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@ -234,7 +234,7 @@
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SATA1>;
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@ -380,7 +380,7 @@
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SGMII2>;
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@ -31,7 +31,7 @@
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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@ -31,7 +31,7 @@
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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phy-type = <COMPHY_TYPE_SFI0>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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@ -41,7 +41,7 @@ static const char *get_type_string(u32 type)
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"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
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"SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
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"USB3", "USB3_HOST0", "USB3_HOST1",
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"USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
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"USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
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"IGNORE"
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};
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@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane)
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{
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int ret;
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u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
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debug_enter();
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if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
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if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
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pr_err("Comphy %d isn't configured to SFI\n", lane);
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return 0;
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}
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@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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ptr_chip_cfg->comphy_base_addr, lane,
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mode);
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break;
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case COMPHY_TYPE_SFI:
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mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
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COMPHY_UNIT_ID0,
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case COMPHY_TYPE_SFI0:
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case COMPHY_TYPE_SFI1:
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/* Calculate SFI id */
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id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
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mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
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ptr_comphy_map->speed);
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ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
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ptr_chip_cfg->comphy_base_addr, lane,
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mode);
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ptr_chip_cfg->comphy_base_addr, lane, mode);
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break;
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case COMPHY_TYPE_RXAUI0:
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case COMPHY_TYPE_RXAUI1:
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@ -32,10 +32,11 @@
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#define COMPHY_TYPE_USB3_DEVICE 13
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#define COMPHY_TYPE_RXAUI0 14
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#define COMPHY_TYPE_RXAUI1 15
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#define COMPHY_TYPE_SFI 16
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#define COMPHY_TYPE_AP 17
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#define COMPHY_TYPE_IGNORE 18
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#define COMPHY_TYPE_MAX 19
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#define COMPHY_TYPE_SFI0 16
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#define COMPHY_TYPE_SFI1 17
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#define COMPHY_TYPE_AP 18
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#define COMPHY_TYPE_IGNORE 19
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#define COMPHY_TYPE_MAX 20
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#define COMPHY_TYPE_INVALID 0xff
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#define COMPHY_POLARITY_NO_INVERT 0
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