Commit graph

1965 commits

Author SHA1 Message Date
Olav Morken
d8f2aa3298 AVR32: Make cacheflush cpu-dependent
The AT32UC3A series of processors doesn't contain any cache, and issuing
cache control instructions on those will cause an exception. This commit
makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support.

Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com>
Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com>
Signed-off-by: Olav Morken <olavmrk@gmail.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-02-23 10:34:23 +01:00
Haavard Skinnemoen
ea393eb1d6 Merge branch 'cleanups' into next 2009-02-23 10:27:15 +01:00
Wolfgang Denk
9d34d0a0c1 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-02-22 22:51:25 +01:00
Dirk Behme
6530a8bf8a OMAP3: Add OMAP3 auto detection
This patch adds OMAP3 cpu type auto detection based on OMAP3 register
and removes hardcoded values.

Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-02-22 18:29:10 +01:00
Mike Frysinger
e1ffaee728 Blackfin: disable syscontrol code for now
Looks like the initcode updates fell out of order during my merges.  The
patch that really fixes up this code is part of power-on overhaul and so
is too large for merging at this point.  Instead, we can disable the code
as no currently in-tree board depends on it.  The next merge window will
fix things up properly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-21 19:23:20 -05:00
Shinya Kuribayashi
35c9e14d80 MIPS: cpu/mips/Makefile: Add a missing START line
In the commit 79b51ff820 ([MIPS] cpu/mips/
Makefile: Split [CS]OBJS onto separate lines), I wrongly deleted a START
line.  This patch puts it back.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
2009-02-21 22:03:24 +01:00
Jean-Christophe PLAGNIOL-VILLARD
b03d92e558 pxa: move mmc drivers to drivers/mmc
introduce new macro CONFIG_PXA_MMC to activate it

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-02-20 03:47:50 +01:00
Tom Rix
9490f46564 ARM:PXA Remove redefinition of mmc_cid and mmc_csd.
These structures are defined in the common mmc.h

This was compile checked on cerf250.
2009-02-20 03:47:44 +01:00
Micha Kalfon
94a3312920 pxa: fixing get_timer to return time in miliseconds.
Fixing the get_timer function to return time in miliseconds instead of
ticks. Also fixed PXA boards to use the conventional value of 1000 for
CONFIG_SYS_HZ.

Signed-off-by: Micha Kalfon <smichak.uv@gmail.com>
2009-02-20 03:24:08 +01:00
Wolfgang Denk
44a01a73e8 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-02-19 00:50:08 +01:00
Wolfgang Denk
1bba30efe1 Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-02-19 00:41:08 +01:00
Stefan Roese
b4996d6b21 ppc4xx: PCIe: Change 16GB inbound memory to 4GB
This patch fixes a problem recently seen on some 4xx platforms. For
example on Kilauea PCIe slot #0.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-18 15:59:20 +01:00
Andy Fleming
e1ac387f46 83xx: Add eSDHC support on 8379 EMDS board
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:43 -06:00
Andy Fleming
80522dc836 85xx: Add eSDHC support for 8536 DS
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:43 -06:00
Andy Fleming
1de97f9856 Eliminated arch-specific mmc header requirement
The current MMC infrastructure relies on the existence of an
arch-specific header file.  This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:41 -06:00
Andy Fleming
abb5466ccf Convert mmc_init to mmc_legacy_init
This is to get it out of the way of incoming MMC framework

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:40 -06:00
Andy Fleming
b2e2ed0233 Eliminate support for using MMC as memory
MMC cards are not memory, so we stop treating them that way.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:40 -06:00
Poonam_Aggrwal-b10812
e1be0d25ec 32bit BUg fix for DDR2 on 8572
This errata fix is required for 32 bit DDR2 controller on 8572.
May  also be required for P10XX20XX platforms

Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
2009-02-16 18:06:03 -06:00
Peter Tyser
a1c8a71926 86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:57 -06:00
Peter Tyser
4ef630df77 86xx: Reset update
Update the 86xx reset sequence to try executing a board-specific reset
function.  If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ.  Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:56 -06:00
Kumar Gala
edf0e2524a fsl-ddr: Allow system to boot if we have more than 4G of memory
Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang.  Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Srikanth Srinivasan
8d949aff38 mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Kumar Gala
f8523cb081 85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:51 -06:00
Kumar Gala
1542fbdeec fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller
If we only have one controller we can completely ignore how
memctl_intlv_ctl is set.  Otherwise other levels of code get confused
and think we have twice as much memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:50 -06:00
Kumar Gala
b29dee3c90 85xx: Format cpu freq printing to handle 8 cores
Only print 4 cpu freq per line.  This way when we have 8 cores its a
bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:50 -06:00
Carolyn Smith
7369f0e384 ppc4xx: Fix initialization of the SDRAM_CODT register
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.

Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-12 06:15:48 +01:00
Adam Graham
c645012aef ppc4xx: Autocalibration can set RDCC to over aggressive value.
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.

On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".

This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.

The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.

The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration.  The default will be the
"T2 Sample" value.  A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".

Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-12 06:08:07 +01:00
Wolfgang Denk
f15c6515fc Coding style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-02-12 00:08:39 +01:00
Heiko Schocher
255d28e164 8xx serial, smc: Coding-Style cleanup serial SMC driver
Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-11 23:18:14 +01:00
Heiko Schocher
2b3f12c214 8xx serial, smc: add configurable SMC Rx buffer len
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 8xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.

When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-11 23:18:13 +01:00
ksi@koi8.net
2bc2a8f6dc Fix MPC8260 with ethernet on SCC
This fixes MPC8260 compilation with ethernet on SCC. Probably was a
typo or something...

Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-02-09 22:47:06 -08:00
Heiko Schocher
ae5d8f613c 82xx serial, smc: Coding-Style cleanup serial SMC driver
Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-10 00:55:12 +01:00
Heiko Schocher
c92fac91a0 82xx serial, smc: add configurable SMC Rx buffer len
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 82xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.

When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-02-10 00:54:42 +01:00
Kumar Gala
87c9063963 ppc: Move CONFIG_MAX_MEM_MAPPED to common config.h
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
between the two current users (lib_ppc/board.c, 44x SPD DDR2).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
2009-02-10 00:44:13 +01:00
Becky Bruce
c9315e6b4f mpc86xx: Add support to populate addr map based on BATs
If CONFIG_ADDR_MAP is enabled, update the address map
whenever we write a bat.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-10 00:29:49 +01:00
Kumar Gala
ff4e66e93c pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.

Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-07 23:50:04 +01:00
Wolfgang Denk
0cfa6a9de6 Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2009-02-07 23:24:38 +01:00
Wolfgang Denk
045639397d Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2009-02-07 22:53:45 +01:00
Wolfgang Denk
e70ef33b6b Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-02-07 22:17:19 +01:00
Wolfgang Denk
1b33a62bf9 Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2009-02-07 22:08:53 +01:00
Richard Retanubun
e0db344fab Coldfire: M5271: Allow board header file to specify clock multiplier
M5271 dynamic clock multiplier. It is currently fixed at 100MHz.

Allow the board header file to set their own multiplier and divider.
Added the #define for the multiplier and divider to the cpu header file.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
2009-02-06 14:54:47 -07:00
Richard Retanubun
d1ef25dd81 Coldfire: M5271EVB: Remove usage of CONFIG_SYS_FECI2C
Discontinue the use of CONFIG_SYS_FECI2C (only used by M5271EVB).
Use read-modify-write to activate the FEC pins without disabling I2C.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
2009-02-06 14:54:47 -07:00
Richard Retanubun
4ffc39050a Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core list
Added the CONFIG_M5271 to the list of Coldfire V2 processor. This
was causing the bus clock (not CPU clock) to be declared twice as
fast as it actually is. This causes UARTS to operate at half the
specified baudrate.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
2009-02-06 14:54:46 -07:00
Dirk Eibach
59d1bda7f9 ppc4xx: Make PCIE support selectable
On some platforms PCIE support is not required, but would be included
because the cpu supports it. To reduce fooprint it is now configurable
via CONFIG_PCI_DISABLE_PCIE.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-06 11:06:19 +01:00
Matthias Fuchs
b129eff5ed ppc4xx: Only fixup opb attached UARTs
This patch updates the fdt UART clock fixup code to
only touch CPU internal UARTs on 4xx systems.
Only these UARTs are definitely clocked by gd->uart_clk.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-06 10:53:15 +01:00
Mike Frysinger
f790ef6ff1 Blackfin: dynamically update UART speed when initializing
Previously, booting over the UART required the baud rate to be known ahead
of time.  Using a bit of tricky simple math, we can calculate the new board
rate based on the old divisors.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
2009-02-05 21:25:35 -05:00
Mike Frysinger
97f265f14f Blackfin: add support for fast SPI reads with Boot ROM
Newer Blackfin boot roms support using the fast SPI read command rather than
just the slow one.  If the functionality is available, then use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:35 -05:00
Mike Frysinger
67619982bf Blackfin: check for reserved settings in DDR MMRs
Some bits of the DDR MMRs should not be set.  If they do, bad things may
happen (like random failures or hardware destruction).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:35 -05:00
Mike Frysinger
622a8dc095 Blackfin: set default voltage levels for BF538/BF539 parts
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:34 -05:00
Mike Frysinger
09dc6b0bbd Blackfin: use on-chip syscontrol() rom function when available
Newer Blackfin's have an on-chip rom with a syscontrol() function that needs
to be used to properly program the memory and voltage settings as it will
include (possibly critical) factory tested bias values.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-05 21:25:28 -05:00