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1000 commits

Author SHA1 Message Date
Heiko Schocher
c1ec406282 mtd: atmel_nand: add missing include
using this driver in SPL code with CONFIG_SPL_NAND_ECC
configured leads in an compileerror. Fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:17 -05:00
Tom Rini
625509ab0e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-11-05 12:48:09 -05:00
Marek Vasut
f9cfe17b3d mtd: nand: mxs: Add ECC geometry for 2048b/112b NAND
Add ECC geometry for NAND which has 2048b pagesize and 112b OOB
size. This is for example Macronix MX30LF2G28AB chip.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-10-30 11:02:23 +01:00
Jeroen Hofstee
441529795c omap_gpmc: fix warnigs with W=1
- make omap_spl_dev_ready static
- make omap_reverse_list static, move to under CONFIG_NAND_OMAP_ELM

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@ti.com>
2014-10-25 07:02:02 -04:00
Jeroen Hofstee
00dcb07c54 cti_flash.c: use __weak when requested for flash_(read|write){8,16,32,64}
For various reasons (design, errata) boards may need to implement their
own versions of these accessors.  So in the case of
CONFIG_CFI_FLASH_USE_WEAK_ACCESSOR mark the functions as weak.  In the
normal case mark them as static to allow for better optimization.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[trini: Reword commit message]
Signed-off-by: Tom Rini <trini@ti.com>
2014-10-25 06:58:51 -04:00
Stefan Roese
3dc23f7852 arm: marvell: Move arch/kirkwood.h to arch/soc.h
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:20 -04:00
Simon Glass
b6c2956def dm: sf: sandbox: Convert SPI flash driver to driver model
Convert sandbox's spi flash emulation driver to use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:51 -06:00
Simon Glass
fbb099183e dm: Convert spi_flash_probe() and 'sf probe' to use driver model
We want the SPI flash probing feature to operate as a standard driver.
Add a driver for the basic probing feature used by most boards. This
will be activated by device_probe() as with any other driver.

The 'sf probe' command currently keeps track of the SPI slave that it
last used. This doesn't work with driver model, since some other driver
or system may have probed the device and have access to it too. On the
other hand, if we try to probe a device twice the second probe is a nop
with driver model.

Fix this by searching for the matching device, removing it, and then
probing it again. This should work as expected regardless of other device
activity.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:50 -06:00
Simon Glass
4c2dbefde5 dm: sf: Add a uclass for SPI flash
Add a driver model uclass for SPI flash which supports the common
operations (read, write, erase). Since we must keep support for the
non-dm interface, some modification of the spi_flash header is required.

CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:50 -06:00
Simon Glass
ae242cbfd0 spi: Use error return value in sf_ops
Adjust spi_flash_probe_slave() to return an error value instead of a
pointer so we get the correct error return.

Have the caller allocate memory for spi_flash to simplify error handling,
and also so that driver model can use its existing allocated memory.

Add a spi.h include in the sf_params file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:50 -06:00
Simon Glass
ff0960f9a0 sf: Tidy up public and private header files
Since spi_flash.h is supposed to be the public API for SPI flash, move
private things to sf_internal.h. Also tidy up a few comment nits.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:50 -06:00
Simon Glass
843c9e8796 dm: Add spi.h header to a few files
Some files are using SPI functions but not explitly including the SPI
header file. Fix this, since driver model needs it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:47 -06:00
Albert ARIBAUD
790af81543 Merge branch 'u-boot/master' into 'u-boot-arm/master' 2014-10-11 01:20:30 +02:00
Masahiro Yamada
ed3c980bee mtd: denali: support NAND_CMD_RNDOUT command
The function nand_flash_detect_ext_param_page() requires
NAND_CMD_RNDOUT command supported.  It is necessary to detect some
types of ONFi-compliant devices.  Without it, the error message
"unsupported command received 0x5" is shown.

Let's support this command on the Denali NAND controller driver.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Chin Liang See <clsee@altera.com>
2014-10-09 17:33:26 -05:00
Masahiro Yamada
05968e7cfd mtd: denali: fix NAND_CMD_PARAM command
NAND_CMD_PARAM (0xEC) command is not working on the Denali
NAND controller driver.

Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command
is followed by an address cycle, the target device goes busy.
(R/B# is deasserted)
Wait until the parameter data are ready.

In addition, unnecessary clear_interrupts() should be removed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Chin Liang See <clsee@altera.com>
2014-10-09 17:33:24 -05:00
Albert ARIBAUD
4b19b7448e Merge remote-tracking branch 'u-boot-imx/master'
The single file conflict below is actually trivial.

Conflicts:
	board/boundary/nitrogen6x/nitrogen6x.c
2014-10-08 21:20:49 +02:00
Tom Rini
dd0204e48d Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-10-07 07:38:39 -04:00
Baruch Siach
9169305599 cfi_flash: don't hide write/erase errors
Partially revert commit 0d01f66d23 (CFI: cfi_flash write fix for AMD
legacy).

flash_full_status_check() used to skip status register parsing when
flash_status_check() returns OK. This is wrong since flash_status_check()
must return OK for other status bits to be valid.

Cc: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2014-10-06 14:12:12 +02:00
Masahiro Yamada
845034e6b2 mtd: denali: add Denali NAND driver for SPL
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.

This driver requires two CONFIG macros:
 - CONFIG_SPL_NAND_DENALI
     Define to enable this driver.
 - CONFIG_SYS_NAND_BAD_BLOCK_POS
     Specify bad block mark position in the oob space. Typically 0.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
2014-10-05 14:10:09 +09:00
Masahiro Yamada
4b0abf9f3c mtd: denali: add Denali controller configs to Kconfig
Commit 3eb3e72a3f (nand/denali: Adding Denali NAND driver support)
introduced some new options, and some of them were documented by
commit f9860cf081 (nand/denali: Document CONFIG symbols).

This commit allows users to enable/disable them via Kconfig
with more detailed help docs.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
2014-10-05 14:10:09 +09:00
Tom Rini
be9f643ae6 Merge branch 'for-tom' of git://git.denx.de/u-boot-dm 2014-09-26 20:10:48 -04:00
Simon Glass
110bdee00f sandbox: Convert SPI flash emulation to use sf_params
At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.

This enables us to expand the number of chips that sandbox supports.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-26 15:00:36 -06:00
Tom Rini
2c2277f15c Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-09-26 09:57:52 -04:00
Chin Liang See
3eb3e72a3f nand/denali: Adding Denali NAND driver support
To add the Denali NAND driver support into U-Boot.
This driver is leveraged from Linux with commit ID
fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali
controller 64 variance, you need to declare macro
CONFIG_SYS_NAND_DENALI_64BIT.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-25 13:43:16 -05:00
Stefan Roese
be16aba5ce mtd: nand: Fix length bug in ioread16_rep() and iowrite16_rep()
The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific
and have been introduced with the Linux MTD v3.14 sync. While introducing
these functions, the length for the loop has been miscalculated. The ">> 1"
is already present in the caller. So lets remove it in the function.

Tested on omap3_ha.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-09-25 13:43:00 -05:00
Rostislav Lisovy
2f665945b3 mtd: nand: am335x: Fix 'bit-flip' errors in SPL
OMAP GPMC driver used with some NAND Flash devices
(e.g. Spansion S34ML08G1) causes that U-boot shows
hundreds of 'nand: bit-flip corrected' error messages.
Possible cause was discussed in the mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html

The issue was partially fixed with the cc81a5291910d7a.git
however this has to be done to fix the SPL.

The original author of the code is Belisko Marek
<marek.belisko@gmail.com>

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-25 13:43:00 -05:00
Prabhakar Kushwaha
5b8388a827 driver/mtd: Use generic timer API for FSL IFC, eLBC
Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks

Replace usec2ticks with get_timer() (generic timer API)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:17 -07:00
Masahiro Yamada
ed36323f6d kconfig: add blank Kconfig files
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-09-24 18:30:28 -04:00
Stefan Roese
31969b8993 sf: Add M25PX64 SPI NOR flash ID
Add ID for this Numonix / STMicro chip.

Tested on Marvell DB-78460-BP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:46:25 +05:30
Nikita Kiryanov
88e34e5ff7 spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.

Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.

Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:40:10 +05:30
Nikita Kiryanov
01d2aaf61b mtd: spi: add support for M25PE16 and M25PX16
Add support for M25PE16 and M25PX16

Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:25:16 +05:30
Simon Glass
bf1a86fca0 sf: Add an empty entry to the parameter list
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:30 -06:00
Stefano Babic
42817eb85d Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-22 15:51:01 +02:00
Boris BREZILLON
d357b94041 mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC
Disable subpage write when using PMECC to prevent buggy partial page write.

This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:22 +02:00
Wu, Josh
14b3b44eda mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc register
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:13 +02:00
maxin.john@enea.com
5da163d665 mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREAD
This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-09-16 12:23:59 -04:00
Khoronzhuk, Ivan
7206111e52 mtd: nand: davinci_nand: update write_page function for keystone RBL
After mtd was synced with Linux 3.14
(ff94bc40af)
the number of parameters for write_page function of nand_chip was
changed. The additional two var were needed for subpage write.
As keystone has no supbage write they are not needed. So correct
only function definition by upgrading it's parameter list.
That helps to get ritd of compilation warning.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-16 12:23:59 -04:00
Masahiro Yamada
3b61297024 kbuild: force to define __UBOOT__ in all the C sources
U-Boot has imported various source files from other projects,
mostly Linux.

Something like

  #ifdef __UBOOT__
    [ modification for U-Boot ]
  #else
    [ original code ]
  #endif

is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.

Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2014-09-16 12:23:56 -04:00
Stefan Agner
72d7beabf7 mtd: nand: add Freescale vf610_nfc driver
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
2014-09-16 13:25:18 +02:00
Rostislav Lisovy
cc81a52919 mtd: nand: omap_gpmc: Fix 'bit-flip' errors
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html

Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."

This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-04 13:06:00 -04:00
Rostislav Lisovy
5c3f7e0ead mtd: nand: omap_gpmc: Enable multiple NAND flash devices
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
fc12a1f589 mtd: nand: davinci_nand: correct keystone RBL layout definition
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-04 13:06:00 -04:00
Holger Brunck
292221e183 arm/kirkwood/nand: allow forced disabling for subpage writes
Make it configurable to disable subpage writes like the DaVinci NAND
driver already does.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Scott Wood <scottwood@freescale.com>
2014-08-30 07:46:41 -04:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
Heiko Schocher
4e67c57125 mtd,ubi,ubifs: sync with linux v3.15
snyc with linux v3.15:

commit 1860e379875dfe7271c649058aeddffe5afd9d0d
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Jun 8 11:19:54 2014 -0700

    Linux 3.15

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ddf7bcfa6c mtd, ubi, ubifs: update for the sync with linux v3.14
while playing with the new mtd/ubi/ubifs sync, found some
small updates for it:

- add del_mtd_partition() to include/linux/mtd/mtd
- mtd: add a debug_printf
- remove some not used functions

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ff94bc40af mtd, ubi, ubifs: resync with Linux-3.14
resync ubi subsystem with linux:

commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Mar 30 20:40:15 2014 -0700

    Linux 3.14

A nice side effect of this, is we introduce UBI Fastmap support
to U-Boot.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Joerg Krause <jkrause@posteo.de>
2014-08-25 19:25:55 -04:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Marek Vasut
a52a178f0b sf: sf_ops: Stop leaking memory
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Tom Rini
362f16b1e9 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-07-29 09:41:35 -04:00
Albert ARIBAUD
b1cdd8baa1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-28 12:26:21 +02:00
Khoronzhuk, Ivan
67ac6ffaee mtd: nand: davinci: add opportunity to write keystone U-boot image
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.

The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.

The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.

Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 15:21:06 -04:00
Heiko Schocher
562f8df18d spi: add config option to enable the WP pin function on st micron flashes
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128 thorugh
the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-07-23 12:26:45 +02:00
Prabhakar Kushwaha
591dd19230 driver/nand: Add support of 16K SRAM for IFC 2.0
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

Update the page offset calculation logic to support the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
04818bbdc3 driver/nand: Update SRAM initialize logic for IFC.
IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.

update SRAM initialize logic to reflect the same.

Also print error message in case of Page read error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
3bab3d8324 driver/nand:Define MAX_BANKS same as SoC defined for IFC
The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Jeroen Hofstee
c15df21fe7 mtd: cfi_flash: fix clang warning
clang warns this check is silly; it is since s is
a local variable.

u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
  array 's' not equal to a null pointer is always true
  else if ((s != NULL) && (strcmp(s, "yes") == 0)) {

cc: Stefan Roese <sr@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:22 -04:00
Albert ARIBAUD
e99f30e105 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-01 15:11:18 +02:00
Albert ARIBAUD
d6694aff56 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-06-30 23:00:34 +02:00
Khoronzhuk, Ivan
3e01ed00da mtd: nand: davinci: add header file for driver definitions
The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <trini@ti.com>
2014-06-19 17:53:58 -04:00
Tom Rini
28b62f0de3 Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-06-11 11:40:11 -04:00
Poddar, Sourav
1f436a6ddf sf: probe: Fix quad bit set path
Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-06-08 23:12:27 +05:30
Siva Durga Prasad Paladugu
0472808608 sf: params: Added support for Spansion S25FL512S_512K
Added support for Spansion chip "S25FL512S_512K".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-06-08 23:12:27 +05:30
pekon gupta
46840f66ca mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:10 -04:00
pekon gupta
b80a660338 mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL:    SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
        which is called before probing for devices, hence any ONFI parameter
        information is not available during GPMC initialization.

Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.

This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:06 -04:00
Brian Norris
27ce9e4290 mtd: nand: force NAND_CMD_READID onto 8-bit bus
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:03 -04:00
Brian Norris
b9ae609fdb mtd: nand: don't use read_buf for 8-bit ONFI transfers
Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author:     Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers

  Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
  devices, we need to avoid the upper I/O[16:9] bits. See the following
  commit for reference:

  commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
  Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  Date:   Thu Dec 5 22:22:04 2013 +0100

      mtd: nand: don't use {read,write}_buf for 8-bit transfers

  Now, I think that all barriers to probing ONFI on x16 devices are
  removed, so remove the check from nand_flash_detect_onfi().

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:01 -04:00
pekon gupta
3f990dc83b mtd: nand: omap: fix error-codes returned from omap-elm driver
This patch
 omap-elm.c: replaces -ve integer value returned during errorneous condition,
             with proper error-codes.
 omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
             omap-elm driver to upper layers

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:46:00 -04:00
pekon gupta
a09431da38 mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch
This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:57 -04:00
pekon gupta
9233279f8e mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info
This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemes

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:55 -04:00
pekon gupta
d21e77ff84 mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'
This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
 - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
 - remove nand_bch_priv.mode: <unused>

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:51 -04:00
pekon gupta
41bbe4dd49 mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16
ELM hardware engine support ECC error detection for multiple ECC strengths like
 +------+------------------------+
 |Type  | ECC syndrome length    |
 +------+------------------------+
 |BCH4  | 6.5 bytes = 13 nibbles |
 |BCH8  | 13 byte = 26 nibbles   |
 |BCH16 | 26 bytes = 52 nibbles  |
 +------+------------------------+

Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:48 -04:00
pekon gupta
b98c5755c0 mtd: nand: omap_elm: remove #include omap_gpmc.h
There is no dependency of omap_elm.c on omap_gpmc.h

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:47 -04:00
Tim Harvey
73210dccdb spl: nand: add support for mxs nand
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:07:25 +02:00
Belisko Marek
97eeae1a07 mtd: nand: omap_gpmc: Fix update of read_ecc in oob
We need to flip only one bit not assign.

Signed-off-by: Marek Belisko <marek.belisko@gmail.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-05-13 19:48:17 -04:00
Albert ARIBAUD
d2a3e91139 Merge branch 'u-boot/master'
Conflicts:
	drivers/net/Makefile

(trivial merge)
2014-05-09 11:50:14 +02:00
Prabhakar Kushwaha
1eaa742d85 driver: Add support of image load for MMC & SPI in SPL
Add support of loading image, binary for MMC and SPI during SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
e278ddcd7f driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.

During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.

Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
5abed9c546 driver/ifc: define nand_spl_load_image() for SPL
nand_spl_load_image() can also be used for non TPL framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Karicheri, Muralidharan
999d7d326d NAND: DaVinci: allow forced disable of subpage writes
This patch introduces a configurable mechanism to disable
subpage writes in the DaVinci NAND driver.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:38 -04:00
Tom Rini
fa1a73fa87 SPL:SPI: Add Falcon Mode support
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:37 -04:00
Tom Rini
db60580649 mtd: Build nand_util.o for CONFIG_ENV_IS_IN_NAND in SPL
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 14:39:54 -04:00
Tom Rini
6dd3b56689 mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL
This mainly converts the am335x_spl_bch driver to the "normal" format
which means a slight change to nand_info within the driver.

Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 14:39:54 -04:00
Masahiro Yamada
dd649f1d00 mtd: delete unused files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
2014-04-17 14:38:30 -04:00
Marek Vasut
bf64035a15 mtd: spi: Fix page size for S25FL032P,S25FL064P
The commit 6af8dc3ebc broke support for
S25FL032P and S25FL064P by carelessly removing the code handling special
page size for these two SPI NOR flashes and unifying the code under the
assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size.

Add special case handling for these two SPI NOR flashes.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:57 +05:30
Jagannadha Sutradharudu Teki
c6136aad91 sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-03-17 21:54:57 +05:30
Marek Vasut
cc56f13392 sf: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:56 +05:30
Marek Vasut
cfa90a636b sf: Add S25FL128S_256K IDs
Add IDs for this new chip.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:56 +05:30
Marek Vasut
c1f9325965 sf: Fix entries for S25FL256S_256K and S25FL512S_256K
Both of these chips have 256kB big sectors, thus the _256K suffix,
compared to their _64K counterparts, which have 64kB sectors. Also,
they have four times less sectors than their _64K counterparts.

Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:56 +05:30
Tom Rini
5495dae7aa Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-03-10 14:22:54 -04:00
Bo Shen
0b0b4f5981 mtd: nand: atmel: prepare for nand spl boot support
Prepare for nand spl boot support. It supports nand software ECC and
hardware PMECC.
This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 19:19:06 +01:00
Stefan Roese
345b77baca ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.

This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2014-03-07 10:59:06 -05:00
pekon gupta
2eda892f00 mtd: nand: omap: move omap_elm.h from arch/arm/include/asm to drivers/mtd/nand
omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-04 17:23:54 -06:00
pekon gupta
6aff050988 mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nand
omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-04 17:23:54 -06:00
pekon gupta
51d192c40d mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers into common omap_gpmc.h
Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related
defines and declarations scattered in SoC platform specific header files
like include/asm/arch-xx/cpu.h
However, GPMC hardware remains same across all platforms thus this patch merges
GPMC data scattered across different arch-xx specific header files into single
header file include/asm/arch/omap_gpmc.h

Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-04 17:23:54 -06:00
pekon gupta
6e562b1106 mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes
chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
	for ECC_BCH8 scheme using GPMC and ELM

This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
  known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
  omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-03 20:09:03 -06:00
pekon gupta
71a7f95600 mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes
chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.

All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.

This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges multiple chip->calculate API for different ECC schemes
  omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw()
				==> omap_calculate_ecc()
- removes omap_ecc_disable() and instead uses it as inline.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-03 20:09:03 -06:00
pekon gupta
f5f1f614bd mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes
chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)

Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip->ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() -> omap_enable_ecc_bch()

(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc()

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-03 20:09:03 -06:00
Prabhakar Kushwaha
1b4175d6fa driver/ifc:Change accessor function to take care of endianness
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So update acessor functions with common IFC acessor functions to take care
both type of endianness.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:51 -08:00
Po Liu
6609916efb powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.

	- For ifc, elbc, esdhc, espi, all need the SPL without
	section .resetvec.
	- Use a clear function name for nand spl boot.
	- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
	in spl/Makefile;

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:42:01 -08:00
Jeroen Hofstee
13fbde6e4f nand, gpmc: fix reading after switching ecc
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip->ecc.read_subpage which is not a valid
pointer. Therefore clear the flag when switching ecc so
reading in hw mode works again.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-01-17 08:04:32 -05:00
Siva Durga Prasad Paladugu
35a55fb57f sf: params: Removed flag SECT_4K for Micron N25Q128
Remove the flag SECT_4K for device N25Q128 as the 4K-byte
sub sector erase granularity is available only for top/bottom
8 sectors in some of the N25Q128 chips.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-12 21:40:23 +05:30
Jagannadha Sutradharudu Teki
b902e07cea sf: Add CONFIG_SF_DUAL_FLASH
This config will use for defining greater than single flash support.
currently - DUAL_STACKED and DUAL_PARALLEL.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-12 21:40:22 +05:30
Jagannadha Sutradharudu Teki
056fbc73d5 sf: Add dual memories support - DUAL_PARALLEL
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-12 21:40:22 +05:30
Jagannadha Sutradharudu Teki
f77f469117 sf: Add dual memories support - DUAL_STACKED
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-12 21:40:11 +05:30
Jagannadha Sutradharudu Teki
ab92224f45 sf: ops: Unify read_ops bank configuration
Unified the bar code from read_ops into a spi_flash_bar()

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-12 21:38:33 +05:30
Jagannadha Sutradharudu Teki
2ba863fae6 sf: Code cleanups
- comment typo's
- func args have a proper names

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-12 21:38:21 +05:30
Jagannadha Sutradharudu Teki
9f4322fd22 sf: Divide flash register ops from QEB code
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 16:51:41 +05:30
Jagannadha Sutradharudu Teki
5bb30f1a40 sf: probe: Enable macronix quad read/write cmds support
Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 16:51:39 +05:30
Jagannadha Sutradharudu Teki
067951223e sf: Add macronix set QEB support
This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 16:51:37 +05:30
Jagannadha Sutradharudu Teki
ff063ed480 sf: Discover read dummy_byte
Discovered the read dummy_byte based on the
configured read command.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 16:50:45 +05:30
Jagannadha Sutradharudu Teki
c4ba0d82d3 sf: Add QUAD_IO_FAST read support
This patch adds support QUAD_IO_FAST read command.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:13:27 +05:30
Jagannadha Sutradharudu Teki
33adfb5f9b sf: Separate the flash params table
Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:13:27 +05:30
Jagannadha Sutradharudu Teki
35ba667df4 sf: probe: Enable RD_FULL and WR_QPP
This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.

Remaining parts will be add in future patches.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:13:26 +05:30
Jagannadha Sutradharudu Teki
d08a1baf61 sf: Set quad enable bit support
This patch provides support to set the quad enable bit on flash.

quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.

Currently added set  quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:13:26 +05:30
Jagannadha Sutradharudu Teki
6cba6fdf96 sf: ops: Add configuration register writing support
This patch provides support to program a flash config register.

Configuration register contains the control bits used to configure
the different configurations and security features of a device.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:13:25 +05:30
Jagannadha Sutradharudu Teki
3163aaa63f sf: Add quad read/write commands support
This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read program

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:13:11 +05:30
Jagannadha Sutradharudu Teki
4e09cc1e2c sf: Add extended read commands support
Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.

This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 15:10:28 +05:30
Marek Vasut
9b56942f7d mtd: onenand: Fix unaligned access
Fix unaligned access in OneNAND core. The problem is that the ffchars[] array
is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed
to the memcpy_16() function. The memcpy_16() function will treat the buffer as
an array of "unsigned short", thus triggering unaligned access if the compiler
decided ffchars[] to be not aligned.

I managed to trigger the problem with regular ELDK 5.4 GCC compiler.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2013-12-31 09:59:16 +01:00
Tom Rini
1bbba03d0e Merge branch 'master' of git://git.denx.de/u-boot-spi 2013-12-19 14:22:12 -05:00
Poddar, Sourav
ac5cce38de driver: mtd: sf_ops: claim bus while doing memcpy
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-19 12:23:22 +05:30
Luka Perkov
57af475389 sf: probe: add support for MX25L2006E
Add support for Macronix MX25L2006E SPI flash.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-12-18 23:23:41 +05:30
Luka Perkov
28303f617a sf: probe: Hex values are in lower case
All other hex values in sf_probe.c are in lower case so we should
fix this one too.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-12-18 23:23:41 +05:30
Nikita Kiryanov
fcd0524574 mtd: nand: omap: fix ecc ops assignment when changing ecc
If we change to software ecc and then back to hardware ecc, the nand ecc ops
pointers are populated with incorrect function pointers. This is related to the
way nand_scan_tail() handles assigning functions to ecc ops:

If we are switching to software ecc/no ecc, it assigns default functions to the
ecc ops pointers unconditionally, but if we are switching to hardware ecc,
the default hardware ecc functions are assigned to ops pointers only if these
pointers are NULL (so that drivers could set their own functions). In the case
of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are
assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc,
the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite
them with hw ecc functions.
The result: sw ecc functions used to write hw ecc data.

Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that
ops which were not assigned by the driver will get the correct default values
from nand_scan_tail().

Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2013-12-17 17:47:47 -06:00
Nikita Kiryanov
eb237a15bd mtd: nand: omap: fix sw->hw->sw ecc switch
When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values
into the current nand chip's ecc.layout struct. This is done under the
assumption that the struct exists only to store values, so it is OK to overwrite
it, but there is at least one situation where this assumption is incorrect:

When switching to 1 bit hamming code sw ecc, the job of assigning layout data
is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a
pointer to an existing struct prefilled with the appropriate values. This struct
doubles as both data and layout definition, and therefore shouldn't be
overwritten, but on the next switch to hardware ecc, this is exactly what's
going to happen. The next time the user switches to software ecc, they're
going to get a messed up ecc layout.

Prevent this and possible similar bugs by explicitly using the
private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2013-12-17 17:46:53 -06:00
Tom Rini
3ef1eadb44 nand_util.c: Use '%zd' for length in nand_unlock debug print
length is size_t so needs to be '%zd' not '%d' to avoid warnings.

Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-17 17:44:36 -06:00
Nikita Kiryanov
2528460c38 mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.size
Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic
platform" (d016dc42ce) changed the way
software ECC is configured, both during boot, and during ecc switch, in a way
that is not backwards compatible with older systems:

Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring
for software ecc, relying on nand_scan_tail() to select a default for ecc.size
(256), while the new version of omap_gpmc.c assigns ecc.size = pagesize,
which is likely to not be 256.

Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert
to the original behavior.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Pekon Gupta <pekon@ti.com>
2013-12-17 17:41:25 -06:00
Stefan Roese
5d7a49b930 mtd: nand: omap_gpmc: cosmetic: Fix indentation
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: wrap some long lines]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-12-17 17:31:14 -06:00
pekon gupta
69cc97f8db mtd: nand: omap: fix ecc-layout for HAM1 ecc-scheme
As per OMAP3530 TRM referenced below [1]

For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
 - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
 - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device

Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
 *for x8 NAND Device*
 +--------+---------+---------+---------+---------+---------+---------+
 | xxxx   | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
 +--------+---------+---------+---------+---------+---------+---------+

 *for x16 NAND Device*
 +--------+--------+---------+---------+---------+---------+---------+---------+
 | xxxxx  | xxxxx  | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
 +--------+--------+---------+---------+---------+---------+---------+---------+

This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.

[1] OMAP3530: http://www.ti.com/product/omap3530
    TRM: http://www.ti.com/litv/pdf/spruf98x
		Chapter-25: Initialization Sub-topic: Memory Booting
		Section: 25.4.7.4 NAND
		Figure 25-19. ECC Locations in NAND Spare Areas

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Stefan Roese <sr@denx.de>
2013-12-17 17:28:41 -06:00
Masahiro Yamada
392ba5256a drivers/mtd: descend into sub directories only when it is necessary
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:18:44 -05:00
Tom Rini
4b210ad342 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	board/samsung/trats2/trats2.c
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-12-10 17:15:18 -05:00
Albert ARIBAUD
f15ea6e1d6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds
2013-12-10 22:23:59 +01:00
Tom Rini
65b7fe28a1 Merge branch 'spi' of git://git.denx.de/u-boot-x86 2013-12-10 09:36:23 -05:00
Mike Frysinger
ffdb20bea1 sandbox: spi: Add new SPI flash driver
This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write.  Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.

sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09 12:22:39 -07:00
Simon Glass
0efc02499f spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node
This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09 12:22:12 -07:00
Andreas Bießmann
ac45bb1646 at91: nand: switch atmel_nand to generic GPIO API
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-12-09 13:21:45 +01:00
Priyanka Jain
7aa6c455c3 powerpc: spiflash:Add corenet devices support in eSPI SPL
Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.

So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:34 -08:00
Tom Rini
77fdd6d1eb Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-12-02 08:38:28 -05:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
pekon gupta
3f719069c8 mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme
This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed
CONFIG_xx used for selecting NAND ecc-schemes.
This patch aims at solving following issues.

1) Currently ecc-scheme is tied to SoC platform, which prevents user to select
   other ecc-schemes also supported in hardware. like;
 - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite
   the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with
   software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW).
 - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware
   supports BCH16 ecc-scheme also.

2) Different platforms use different CONFIG_xx to select ecc-schemes, which
   adds confusion for user while migrating platforms.
 - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only
    8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW)
    whereas ELM hardware engine supports other ecc-schemes also like; BCH4,
    and BCH16 (in future).
 - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error
    correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW).
 - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library

Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency
on SoC platform and NAND driver. And user can select ecc-scheme independently
foreach board.
However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still
depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand)

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
pekon gupta
d016dc42ce mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+-----------------------------------+-----------------+-----------------+
|ECC Scheme                         | ECC Calculation | Error Detection |
+-----------------------------------+-----------------+-----------------+
|OMAP_ECC_BCH8_CODE_HW              |GPMC             |ELM H/W engine   |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC             |S/W BCH library  |
+-----------------------------------+-----------------+-----------------+

Current implementation limits the BCH8_CODE_HW only for AM33xx device family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.

This patch
- removes CONFIG_AM33xx
	Thus this driver can be reused by all devices having ELM h/w engine.
- adds omap_select_ecc_scheme()
	A common function to handle ecc-scheme related configurations. This
	can be used both during device-probe and via user-space u-boot commads
	to change ecc-scheme. During device probe ecc-scheme is selected based
	on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8
- enables CONFIG_BCH
	S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW
  	is enabled by CONFIG_BCH.
- enables CONFIG_SYS_NAND_ONFI_DETECTION
	for auto-detection of ONFI compliant NAND devices
- updates following README doc
	doc/README.nand
	board/ti/am335x/README
	doc/README.omap3

Signed-off-by: Pekon Gupta <pekon@ti.com>
[scottwood@freescale.com: fixed unused variable warning]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-11-21 13:33:41 -06:00
pekon gupta
beba5f04f2 mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms
ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include <asm/elm.h>
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
	and include in all board configs using AM33xx SoC platform.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c0dc3dec69 mtd: atmel_nand: use dev_xxx instead of printk
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c55cc573ea mtd: atmel_nand: don't print bit correction message in driver
Since for some MLC nand, bit errors happened too often. Just disable it
to avoid noise

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
16dddef605 mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flash
increase the delay to 75us to support the 8k bytes page nand flash

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Prabhakar Kushwaha
71220f80e7 mtd/ifc: Add support of 8K page size NAND flash
Current IFC driver supports till 4K page size NAND flash.
Add support of 8K NAND flash
  - Program Spare region size in csor_ext
  - Add nand_ecclayout for 4 bit & 8 bit ecc
  - Defines constants
  - Add support of 8K NAND boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Liu Po <po.liu@freescale.com>
2013-11-21 13:33:40 -06:00
Prabhakar Kushwaha
68ec9c85a9 mtd: move & update nand_ecclayout structure (plus board changes)
nand_ecclayout is present in mtd.h at Linux.
Move this structure to mtd.h to comply with Linux.

Also, increase the ecc placement locations to 640 to suport device having
writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone
up to 640 bytes and consequently the maximum ecc placement locations have
also gone up to 640.

Changes from Prabhabkar's version (squashed into one patch to preserve
bisectability):
 - Added _LARGE to MTD_MAX_*_ENTRIES

   This makes the names match current Linux source, and resolves
   a conflict between
   http://patchwork.ozlabs.org/patch/280488/
   and
   http://patchwork.ozlabs.org/patch/284513/

   The former was posted first and is closer to matching Linux, but
   unlike Linux it does not add _LARGE to the names.  The second adds
   _LARGE to one of the names, and depends on it in a subsequent patch
   (http://patchwork.ozlabs.org/patch/284512/).

 - Made max oobfree/eccpos configurable, and used this on tricorder,
   alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build
   for me without doing so, due to a size increase).

   On tricorder SPL, this saves 2576 bytes (and makes the SPL build
   again) versus the new default of 640 eccpos and 32 oobfree, and
   saves 336 bytes versus the old default of 128 eccpos and 8 oobfree.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Vipin Kumar <vipin.kumar@st.com>
[scottwood@freescale.com: changes as described above]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2013-11-21 13:32:43 -06:00
Prabhakar Kushwaha
ed5ac34a33 driver/mtd/ifc: Read Status while programming NAND flash
as per controller description,
  "While programming a NAND flash, status read should never skipped.
   Because it may happen that a new command is issued to the NAND Flash,
   even when the device has not yet finished processing the previous request.
   This may result in unpredictable behaviour."

IFC controller never polls for R/B signal after command send. It just return
control to software. This behaviour may not occur with NAND flash access.
because new commands are sent after polling R/B signal. But it may happen
in scenario where GPCM-ASIC and NAND flash device are working simultaneously.

Update the controller driver to take care of this requirement

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-11-13 18:43:39 -06:00
Bo Shen
7604a3f920 MTD: atmel_nand: support for software BCH ECC
Add possible to use software BCH ECC for atmel nand driver

Signed-off-by: Bo Shen <voice.shen@gmail.com>
2013-11-13 17:20:26 -06:00