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mtd: nand: omap: fix ecc-layout for HAM1 ecc-scheme
As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de>
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1 changed files with 6 additions and 2 deletions
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@ -798,8 +798,12 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
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nand->ecc.calculate = omap_calculate_ecc;
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/* define ecc-layout */
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ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
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for (i = 0; i < ecclayout->eccbytes; i++)
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ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
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for (i = 0; i < ecclayout->eccbytes; i++) {
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if (nand->options & NAND_BUSWIDTH_16)
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ecclayout->eccpos[i] = i + 2;
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else
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ecclayout->eccpos[i] = i + 1;
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}
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ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
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ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
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BADBLOCK_MARKER_LENGTH;
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