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mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme
This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed CONFIG_xx used for selecting NAND ecc-schemes. This patch aims at solving following issues. 1) Currently ecc-scheme is tied to SoC platform, which prevents user to select other ecc-schemes also supported in hardware. like; - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW). - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware supports BCH16 ecc-scheme also. 2) Different platforms use different CONFIG_xx to select ecc-schemes, which adds confusion for user while migrating platforms. - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only 8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW) whereas ELM hardware engine supports other ecc-schemes also like; BCH4, and BCH16 (in future). - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW). - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency on SoC platform and NAND driver. And user can select ecc-scheme independently foreach board. However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand) Signed-off-by: Pekon Gupta <pekon@ti.com>
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commit
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17 changed files with 43 additions and 15 deletions
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@ -208,6 +208,29 @@ Platform specific options
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detection. However ECC calculation on such plaforms would still be
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done by GPMC controller.
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CONFIG_NAND_OMAP_ECCSCHEME
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On OMAP platforms, this CONFIG specifies NAND ECC scheme.
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It can take following values:
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OMAP_ECC_HAM1_CODE_SW
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1-bit Hamming code using software lib.
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(for legacy devices only)
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OMAP_ECC_HAM1_CODE_HW
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1-bit Hamming code using GPMC hardware.
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(for legacy devices only)
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
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4-bit BCH code (unsupported)
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OMAP_ECC_BCH4_CODE_HW
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4-bit BCH code (unsupported)
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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8-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using software library.
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- requires CONFIG_BCH to enable software BCH library
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(For legacy device which do not have ELM h/w engine)
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OMAP_ECC_BCH8_CODE_HW
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8-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using ELM hardware engine.
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NOTE:
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=====
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@ -161,8 +161,7 @@ BCH8
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To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
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OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
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to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted
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syndrom generation to your board config.
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and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW.
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The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
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implementation for OMAP3 works for you so the u-boot version should also.
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When you require the SPL to read with BCH8 there are two more configs to
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@ -1004,18 +1004,13 @@ int board_nand_init(struct nand_chip *nand)
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nand->ecc.layout = &omap_ecclayout;
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/* select ECC scheme */
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#if defined(CONFIG_NAND_OMAP_ELM)
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err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW,
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#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
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err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
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CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
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#elif defined(CONFIG_NAND_OMAP_BCH8)
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err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
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#elif !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
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#else
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/* pagesize and oobsize are not required to configure sw ecc-scheme */
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err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
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0, 0);
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#else
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err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_HW,
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CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
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#endif
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if (err)
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return err;
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@ -240,7 +240,8 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif
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@ -264,6 +264,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@ -340,6 +340,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@ -334,6 +334,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@ -327,6 +327,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@ -353,7 +353,6 @@
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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@ -395,6 +394,7 @@
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56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@ -432,6 +432,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@ -107,6 +107,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@ -86,6 +86,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@ -362,6 +362,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif
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@ -325,6 +325,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@ -196,6 +196,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_ECCSTEPS 4
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
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@ -225,7 +225,6 @@
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_CONSOLE
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@ -138,7 +138,6 @@
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_NAND_OMAP_BCH8
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#define CONFIG_BCH
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_MAX_ECCPOS 56
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 13
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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