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04818bbdc3
IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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.. | ||
nand | ||
onenand | ||
spi | ||
ubi | ||
at45.c | ||
cfi_flash.c | ||
cfi_mtd.c | ||
dataflash.c | ||
ftsmc020.c | ||
jedec_flash.c | ||
Makefile | ||
mtdconcat.c | ||
mtdcore.c | ||
mtdpart.c | ||
mw_eeprom.c | ||
st_smi.c |