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mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes
chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by processing the data passed during Read/Write accesses. All H/W based ECC schemes use GPMC controller to calculate ECC syndrome. But each BCHx_ECC scheme has its own implemetation of post-processing and fetching ECC syndrome from GPMC controller. This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way: - merges multiple chip->calculate API for different ECC schemes omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw() ==> omap_calculate_ecc() - removes omap_ecc_disable() and instead uses it as inline. Signed-off-by: Pekon Gupta <pekon@ti.com>
This commit is contained in:
pekon gupta
Scott Wood
parent
f5f1f614bd
commit
71a7f95600
1 changed files with 63 additions and 163 deletions
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@ -21,7 +21,10 @@
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#define SECTOR_BYTES 512
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#define ECCCLEAR (0x1 << 8)
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#define ECCRESULTREG1 (0x1 << 0)
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#ifdef CONFIG_BCH
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static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
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0x97, 0x79, 0xe5, 0x24, 0xb5};
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#endif
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static uint8_t cs;
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static __maybe_unused struct nand_ecclayout omap_ecclayout;
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@ -142,42 +145,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
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return 0;
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}
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/*
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* omap_calculate_ecc - Generate non-inverted ECC bytes.
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*
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* Using noninverted ECC can be considered ugly since writing a blank
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* page ie. padding will clear the ECC bytes. This is no problem as
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* long nobody is trying to write data on the seemingly unused page.
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* Reading an erased page will produce an ECC mismatch between
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* generated and read ECC bytes that has to be dealt with separately.
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* E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
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* is used, the result of read will be 0x0 while the ECC offsets of the
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* spare area will be 0xFF which will result in an ECC mismatch.
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
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const uint8_t *dat, uint8_t *ecc_code)
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{
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u_int32_t val;
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/* Start Reading from HW ECC1_Result = 0x200 */
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val = readl(&gpmc_cfg->ecc1_result);
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ecc_code[0] = val & 0xFF;
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ecc_code[1] = (val >> 16) & 0xFF;
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ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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writel(0x000, &gpmc_cfg->ecc_config);
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return 0;
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}
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/*
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* Generic BCH interface
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*/
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@ -194,12 +161,7 @@ struct nand_bch_priv {
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#define ECC_BCH8 1
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#define ECC_BCH16 2
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/* GPMC ecc engine settings */
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#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
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#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
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/* BCH nibbles for diff bch levels */
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#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
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#define ECC_BCH4_NIBBLES 13
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#define ECC_BCH8_NIBBLES 26
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#define ECC_BCH16_NIBBLES 52
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@ -211,7 +173,6 @@ struct nand_bch_priv {
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* When some users with other BCH strength will exists this have to change!
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*/
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static __maybe_unused struct nand_bch_priv bch_priv = {
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.mode = NAND_ECC_HW_BCH,
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.type = ECC_BCH8,
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.nibbles = ECC_BCH8_NIBBLES,
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.control = NULL
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@ -280,57 +241,76 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
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}
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/*
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* omap_ecc_disable - Disable H/W ECC calculation
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*
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* @mtd: MTD device structure
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* omap_calculate_ecc - Read ECC result
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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* Using noninverted ECC can be considered ugly since writing a blank
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* page ie. padding will clear the ECC bytes. This is no problem as
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* long nobody is trying to write data on the seemingly unused page.
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* Reading an erased page will produce an ECC mismatch between
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* generated and read ECC bytes that has to be dealt with separately.
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* E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
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* is used, the result of read will be 0x0 while the ECC offsets of the
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* spare area will be 0xFF which will result in an ECC mismatch.
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*/
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static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
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{
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writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
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}
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/*
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* BCH support using ELM module
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*/
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#ifdef CONFIG_NAND_OMAP_ELM
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/*
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* omap_read_bch8_result - Read BCH result for BCH8 level
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*
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* @mtd: MTD device structure
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* @big_endian: When set read register 3 first
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* @ecc_code: Read syndrome from BCH result registers
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*/
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static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
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static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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uint32_t *ptr;
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint32_t *ptr, val = 0;
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int8_t i = 0, j;
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if (big_endian) {
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switch (bch->ecc_scheme) {
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case OMAP_ECC_HAM1_CODE_HW:
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val = readl(&gpmc_cfg->ecc1_result);
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ecc_code[0] = val & 0xFF;
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ecc_code[1] = (val >> 16) & 0xFF;
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ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
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break;
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#ifdef CONFIG_BCH
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case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
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#endif
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case OMAP_ECC_BCH8_CODE_HW:
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ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
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ecc_code[i++] = readl(ptr) & 0xFF;
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val = readl(ptr);
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ecc_code[i++] = (val >> 0) & 0xFF;
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ptr--;
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for (j = 0; j < 3; j++) {
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ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
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ecc_code[i++] = readl(ptr) & 0xFF;
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val = readl(ptr);
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ecc_code[i++] = (val >> 24) & 0xFF;
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ecc_code[i++] = (val >> 16) & 0xFF;
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ecc_code[i++] = (val >> 8) & 0xFF;
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ecc_code[i++] = (val >> 0) & 0xFF;
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ptr--;
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}
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} else {
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ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
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for (j = 0; j < 3; j++) {
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ecc_code[i++] = readl(ptr) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
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ptr++;
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}
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ecc_code[i++] = readl(ptr) & 0xFF;
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ecc_code[i++] = 0; /* 14th byte is always zero */
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break;
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default:
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return -EINVAL;
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}
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/* ECC scheme specific syndrome customizations */
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switch (bch->ecc_scheme) {
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case OMAP_ECC_HAM1_CODE_HW:
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break;
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#ifdef CONFIG_BCH
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case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
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for (i = 0; i < chip->ecc.bytes; i++)
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*(ecc_code + i) = *(ecc_code + i) ^
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bch8_polynomial[i];
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break;
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#endif
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case OMAP_ECC_BCH8_CODE_HW:
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ecc_code[chip->ecc.bytes - 1] = 0x00;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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#ifdef CONFIG_NAND_OMAP_ELM
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/*
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* omap_rotate_ecc_bch - Rotate the syndrome bytes
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*
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@ -366,35 +346,6 @@ static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
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syndrome[i] = calc_ecc[j];
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}
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/*
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* omap_calculate_ecc_bch - Read BCH ECC result
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*
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t big_endian = 1;
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int8_t ret = 0;
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if (bch->type == ECC_BCH8)
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omap_read_bch8_result(mtd, big_endian, ecc_code);
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else /* BCH4 and BCH16 currently not supported */
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ret = -1;
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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omap_ecc_disable(mtd);
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return ret;
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}
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/*
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* omap_fix_errors_bch - Correct bch error in the data
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*
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@ -551,57 +502,6 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
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* OMAP3 BCH8 support (with BCH library)
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*/
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#ifdef CONFIG_BCH
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/*
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* omap_calculate_ecc_bch_sw - Read BCH ECC result
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*
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* @mtd: MTD device structure
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* @dat: The pointer to data on which ecc is computed (unused here)
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* @ecc: The ECC output buffer
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*/
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static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc)
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{
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int ret = 0;
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size_t i;
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unsigned long nsectors, val1, val2, val3, val4;
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nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
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for (i = 0; i < nsectors; i++) {
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/* Read hw-computed remainder */
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val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
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val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
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val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
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val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
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/*
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* Add constant polynomial to remainder, in order to get an ecc
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* sequence of 0xFFs for a buffer filled with 0xFFs.
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*/
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*ecc++ = 0xef ^ (val4 & 0xFF);
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*ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
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*ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
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*ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
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*ecc++ = 0xed ^ (val3 & 0xFF);
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*ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
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*ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
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*ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
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*ecc++ = 0x97 ^ (val2 & 0xFF);
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*ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
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*ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
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*ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
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*ecc++ = 0xb5 ^ (val1 & 0xFF);
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}
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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omap_ecc_disable(mtd);
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return ret;
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}
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/**
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* omap_correct_data_bch_sw - Decode received data and correct errors
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* @mtd: MTD device structure
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@ -752,7 +652,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
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nand->ecc.bytes = 13;
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nand->ecc.hwctl = omap_enable_hwecc;
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nand->ecc.correct = omap_correct_data_bch_sw;
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nand->ecc.calculate = omap_calculate_ecc_bch_sw;
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nand->ecc.calculate = omap_calculate_ecc;
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/* define ecc-layout */
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ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
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ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
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@ -794,7 +694,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
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nand->ecc.bytes = 14;
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nand->ecc.hwctl = omap_enable_hwecc;
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nand->ecc.correct = omap_correct_data_bch;
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nand->ecc.calculate = omap_calculate_ecc_bch;
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nand->ecc.calculate = omap_calculate_ecc;
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nand->ecc.read_page = omap_read_page_bch;
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/* define ecc-layout */
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ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
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