Commit graph

19185 commits

Author SHA1 Message Date
Michael Walle
d3b745f7d0 mmc: fsl_esdhc: add pulse width detection workaround
HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
workaroung for the pulse width detection. Apply this workaround in
u-boot, too.

This will make HS400 mode work reliably on the LS1028A SoC.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-06 18:36:04 +08:00
Michael Walle
bd7b8505f2 mmc: fsl_esdhc: add workaround for erratum A-011334
LS1028A SoCs are restricted in what divider values are allowed for HS400
mode. This is basically a port from the corresponding linux driver.

Signed-off-by: Michael Walle <michael@walle.cc>
2021-04-06 18:35:55 +08:00
Neil Armstrong
6f3cd174a3 net: designware: remove amlogic compatibles
These compatibles are now handled by the dwmac_meson8b glue driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-06 11:10:29 +02:00
Neil Armstrong
798424e857 net: designware: add Amlogic Meson8b & later glue driver
This adds a proper glue driver for the Designware DWMAC ethernet MAC IP
found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs.

This is aimed to replace the static ethernet link setup found on the board
init code for the Amlogic SoC based boards.

Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d
with external 10/100/1000 RGMII PHY) to cover the most extreme setups.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-06 11:10:29 +02:00
Neil Armstrong
8120ce17bf net: add Amlogic Meson G12A MDIO MUX driver
The Amlogic G12A & compatible SoCs embeds a mux to either communicate with
the external PHY or the internal 10/100 PHY.

This adds support for this mux as a MDIO MUX device.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-06 11:10:29 +02:00
Neil Armstrong
5160b4567c net: designware: add DM_MDIO support
Add support for DM_MDIO to connect to PHY and expose a MDIO device for the
internal MDIO bus in order to dynamically connect to MDIO PHYs with DT
with eventual MDIO muxes in between.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-06 11:10:29 +02:00
Neil Armstrong
6c7bc9fec0 net: add MMIO Register MDIO MUX driver
Add support for MMIO register MDIO muxes based on the Linux mdio-mux-mmioreg driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-06 11:10:29 +02:00
Pali Rohár
830d29ac37 watchdog: Allow to use CONFIG_WDT without starting watchdog
In some cases it is useful to compile support for U-Boot command 'wdt'
without starting HW watchdog in early U-Boot phase. For example when the
user want to start the watchdog only on demand by some boot script.

This change adds a new compile option WATCHDOG_AUTOSTART to control whether
U-Boot should automatically start the watchdog during init phase or not.

This option is enabled by default as it was the default behavior prior
introducing this new change. When compiling U-Boot users can decide to turn
this option off.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06 10:47:32 +02:00
Pali Rohár
25e20e347e watchdog: Show error message when initr_watchdog() cannot start watchdog
Function wdt_start() may fail. So in initr_watchdog() function check return
value of wdt_start() call and print error message when watchdog starting
failed.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06 10:47:32 +02:00
Pali Rohár
9c44ff1c5f watchdog: Set/unset GD_FLG_WDT_READY flag in wdt_start()/wdt_stop()
Watchdog is ready after successful call of ops->start() callback in
wdt_start() function. And is stopped after successful call of ops->stop()
callback in wdt_stop function.

So move setting of GD_FLG_WDT_READY flag from initr_watchdog() function to
wdt_start() and ensure that GD_FLG_WDT_READY flag is unset in wdt_stop()
function.

This change ensures that GD_FLG_WDT_READY flag is set only when watchdog is
running. And ensures that flag is also also when watchdog was started not
only by initr_watchdog() call (e.g. by U-Boot 'wdt' command).

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06 10:47:32 +02:00
Jagannadha Sutradharudu Teki
53879b1738 cfi_flash: Fix detection of 8-bit bus flash devices via address shift
We had a problem detecting 8/16bit flash devices connected only via
8bits to the SoC for quite a while. Commit 239cb9d9
[mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support] finally
fixed this 8-bit bus support. But also broke some other boards using
this cfi driver. So this patch had to be reverted.

I spotted a different, simpler approach for this 8-bit bus support
on the barebox mailing list posted by
Oleksij Rempel <bug-track@fisher-privat.net>:

http://www.spinics.net/lists/u-boot-v2/msg14687.html

Here the commit text:

"
Many cfi chips support 16 and 8 bit modes. Most important
difference is use of so called "Q15/A-1" pin. In 16bit mode this
pin is used for data IO. In 8bit mode, it is an address input
which add one more least significant bit (LSB). In this case
we should shift all adresses by one:
For example 0xaa << 1 = 0x154
"

This patch now is a port of this barebox patch to U-Boot.

Along with the change w.r.t from barebox,
Some flash chips can support multiple bus widths, override the
interface width and limit it to the port width.

Tested on 16-bit Spansion flash on sequoia.
Tested 8-bit flashes like 256M29EW, 512M29EW.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-04-06 08:55:53 +02:00
Simon Glass
bddac45d04 pinctrl: Return -ENOSYS when system call is not available
Update the code to use -ENOSYS, which is the correct error code for an
unimplemented system call in U-Boot.

Also we should not check for a missing operations array as this is not
permitted. For now this can be covered by an assert().

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-04-06 16:33:19 +12:00
Simon Glass
d6332d59d2 simple-pm-bus: Use -ENOSYS for checking missing system call
We don't need to check -ENOTSUPP since this is not used for this purpose
in U-Boot. Update the code accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-06 16:33:19 +12:00
Simon Glass
3bc11b983d clk: Return -ENOSYS when system call is not available
Update clk_composite_set_parent() to use -ENOSYS, which is the correct
error code for U-Boot. Also rearrange the code so that the error condition
is clearly indicated and the function runs to the end in the normal case,
since this is the common style in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-06 16:33:19 +12:00
Simon Glass
9042bf6fe4 clk: Update drivers to use -EINVAL
At present some drivers use -ENOSUPP to indicate that an unknown or
unsupported clock is used. Most use -EINVAL, indicating an invalid value,
so convert everything to that.

Signed-off-by: Simon Glass <sjg@chromium.org>

Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06 16:33:19 +12:00
Simon Glass
6379a94cac usb: Return -ENOSYS when system call is not available
Update usb_gadget_release() to use -ENOSYS, which is the correct error
code for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-04-06 16:33:19 +12:00
Simon Glass
aa4ad8bbad dm: core: Use -ENOSPC in acpi_get_path()
Update this function to use -ENOSPC which is more commly used when a buffer
runs out of space.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-04-06 16:33:19 +12:00
Tom Rini
db8b46120a Xilinx changes for v2021.07
net:
 - Fix gem PCS support
 
 spi:
 - Small trivial fixes
 
 zynq:
 - Enable time/timer commands
 - Update bitmain platform
 - Several DT changes
 
 zynqmp:
 - Update clock driver
 - mini config alignments
 - Add/update psu_init for zcu208/zcu216/zc1275
 - Several DT changes
 - Enable efi debug command (also for Versal)
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Merge tag 'xilinx-for-v2021.07' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.07

net:
- Fix gem PCS support

spi:
- Small trivial fixes

zynq:
- Enable time/timer commands
- Update bitmain platform
- Several DT changes

zynqmp:
- Update clock driver
- mini config alignments
- Add/update psu_init for zcu208/zcu216/zc1275
- Several DT changes
- Enable efi debug command (also for Versal)
2021-03-31 09:47:30 -04:00
Tom Rini
7d23eb9260 First set of u-boot-atmel features for 2021.07 cycle
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Merge tag 'u-boot-atmel-2021.07-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for 2021.07 cycle:
This small feature set includes the implementation of the slew rate for
the PIO4 pin controller device, and a fix for arm926ejs-based
microprocessors that avoids a crash.
2021-03-30 11:24:09 -04:00
T Karthik Reddy
d999a7b7b6 spi: xilinx_spi: Trivial fixes in axi qspi driver
Use __func__ instead for function name in debug.
Use Linux style u32 instead of uint32_t.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30 12:03:24 +02:00
T Karthik Reddy
dd4c642757 clk: zynqmp: Fix clk dump values
With "clk dump" command, few clocks are showing up incorrect values
and some clocks are displayed as "unknown".

Add missing clocks to zynqmp clock driver to display proper
clocks rates.

Implement a simple way to get clock source, instead of calling
functions. Change existing functions to this simple mechanism.

Fix gem clock name "gem_rx" to "gem_tx" which was incorrect.
Change dbf_fpd & dbf_lpd clk names to dbg_fpd & dbg_lpd.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
2021-03-30 12:03:24 +02:00
Robert Hancock
e8a212ac77 net: gem: Fix setting PCS auto-negotiation state
The code was trying to disable PCS auto-negotiation when a fixed-link node
is present and enable it otherwise. However, the PCS registers were being
written before the PCSSEL bit was set in the network configuration
register, and it appears that in this state, PCS register writes are
ignored. The result is that the intended change only took effect on the
second network operation that was performed, since at that time PCSSEL is
already enabled.

Fix the order of register writes so that PCS registers are only written to
after the PCS is enabled.

Fixes: 26e62cc971 ("net: gem: Disable PCS autonegotiation in case of fixed-link")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30 09:18:47 +02:00
Tom Rini
1057b1be75 Prepare v2021.04-rc5
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Merge tag 'v2021.04-rc5' into next

Prepare v2021.04-rc5
2021-03-29 18:00:21 -04:00
T Karthik Reddy
346df7d4fa spi: spi-uclass: Add support to manually relocate spi memory ops
Add spi memory operations to relocate manually when
CONFIG_NEEDS_MANUAL_RELOC is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-03-27 16:26:48 +13:00
Simon Glass
529d5f96cf cpu: Rename SPL_CPU_SUPPORT to SPL_CPU
The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.

Tidy up the TODO that prompted this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
b3b60f5912 sf: Support querying write-protect
This feature was dropped from U-Boot some time ago:

   f12f96cfaf (sf: Drop spl_flash_get_sw_write_prot")

However, we do need a way to see if a flash device is write-protected,
since if it is, it may not be possible to write to do (i.e. failing to
write is expected).

I am not sure of the correct layer to implement this, so this patch is a
stab at it. If spi-flash makes sense then I will add to the 'sf' also.

Re the points mentioned in the removal commit:

    1) This kind of requirement can be achieved using existing
       flash operations and flash locking API calls instead of
       making a separate flash API.

Which uclass is this?

    2) Technically there is no real hardware user for this API to
       use in the source tree.

I do want coral (at least) to support this.

    3) Having a flash operations API for simple register read bits
       also make difficult to extend the flash operations.

This new patch only mentions write-protect being on or off, rather than
the actual mechanism.

    4) Instead of touching generic code, it is possible to have
       this functionality inside spinor operations in the form of
       flash hooks or fixups for associated flash chips.

That sounds to me like what drivers are for. But we still need some sort
of API for it to be accessible.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
1758551ec9 sandbox: Provide a way to bind fixed/removeable devices
At present when a file is bound to a host device it is always marked as
removeable. Arguably the device is removeable, since it can be unbound at
will. However while it is bound, it is not considered removable by the
user. Also it is useful to be able to model both fixed and removeable
devices for code that distinguishes them.

Add a -r flag to the 'host bind' command and plumb it through to provide
this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
a5bc9abcee sandbox: cros_ec: Only write EC state when the EC is probed
This can crash if the EC has not yet been probed. Add a check to prevent
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
539db6ab09 sandbox: Only call timer_timebase_fallback() if present
This function only exists if CPU is enabled. Update the code to take
account of this, so that it does not have to be enabled on all sandbox
builds.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-03-27 15:04:31 +13:00
Simon Glass
19987c9834 x86: video: Allow coreboot video to be used on any x86 board
When booting from coreboot we need this driver for the video to work.
Update the driver to be usable on any board.

The driver disables itself if it sees that is not booted from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
bcac36185b video: Fix video on coreboot with the copy buffer
The copy buffer, if enabled, prevents booting from coreboot correctly,
since no memory is allocated for it. Allow it to fall back to disabled
in this situation. This ensures that a console is displayed, even if
it is slow.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
e35b6497f4 x86: Make coreboot sysinfo available to any x86 board
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or
from coreboot. In the latter case we want to provide access to the coreboot
sysinfo tables. Move the definitions into a file available to any x86
board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
326aae2589 mmc: pci_mmc: Set up the card detect
The driver currently reads the card-detect but does not register it with
the MMC stack. Update this so that card-detect works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
42ee0cd216 tegra: i2c: Drop LOG_DEBUG
We should not enable debugging by default. Drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:36 +13:00
Simon Glass
7d252d0279 x86: Probe device if needed in intel_gpio_xlate()
The Intel GPIO binding allows GPIOs to be globally numbered, so that it
does not matter which GPIO bank is specified in the device tree. This is
convenient and avoid confusion since the banks do not have the same number
of GPIOs and the numbering is not sequential.

The GPIO uclass ensures that the device mentioned in the devicetree
binding is probed. It is fine for the driver to update gpio_desc to point
to a different driver, but this may not have been probed. If it has not
been, then it cannot be claimed since there is no uclass data.

We could handle this in the GPIO uclass but so far it is an unusual
situation so it is probably not worth the extra code. Handle this case in
the GPIO driver by probing the selected device if necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:36 +13:00
Simon Glass
72d98ee091 x86: p2sb: Drop LOG_DEBUG
We should not enable debugging by default. Drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:36 +13:00
Heinrich Schuchardt
b09c74f66d mtd: spi_flash_free()
dfu_free_entities() invoking dfu_free_entity_sf() has let to segementation
faults due to double freeing the same device.

spi_flash_free() is not relevant for the driver model but exists only for
compatibility with old drivers.

We must not remove any device here:

* The device may still be referenced.
* We don't want to have to probe again.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-27 13:59:36 +13:00
Tom Rini
9c7335e4e6 dtoc support for of-platdata-inst
driver model support for of-platdata-inst
 support of-platdata-inst on x86 / coral
 binman support for exapanded entries
 binman convert docs to reST
 ti-sysc fix for duplicate uclass driver
 patman minor improvements
 pylibfdt build only if needed
 correct obscure CI error with OF_PLATDATA_INST
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Merge tag 'dm-pull-26mar21-take2' of git://git.denx.de/u-boot-dm into next

dtoc support for of-platdata-inst
driver model support for of-platdata-inst
support of-platdata-inst on x86 / coral
binman support for exapanded entries
binman convert docs to reST
ti-sysc fix for duplicate uclass driver
patman minor improvements
pylibfdt build only if needed
correct obscure CI error with OF_PLATDATA_INST
2021-03-26 12:15:26 -04:00
Simon Glass
cfb9c9b77c dm: core: Use separate priv/plat data region
Make use of the new priv/plat data region if enabled. This is implemented
as a simple offset from the position set up by dtoc to the new position.

So long as all access goes through dm_priv_to_rw() this is safe.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
baf0371883 dm: core: Allow storing priv/plat data separately
At present the device priv/data data allocated by dtoc is stored in the
data section along with other variables. On some platforms it is better
to allocate space for it separately, e.g. if SPL is running from read-only
memory.

Create a new space with the same size as that allocated by dtoc, ready for
use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
6f644efdd8 dm: core: Move flags to device-runtime info
When of-platdata-inst is active, use the flags in the new udevice_rt
table, dropping them from the main struct udevice. This ensures that the
latter is not updated at runtime.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
ab933d8026 dm: core: Create a struct for device runtime info
At present when driver model needs to change a device it simply updates
the struct udevice structure. But with of-platdata-inst most of the fields
are not modified at runtime. In fact, typically only the flags need to
change.

For systems running SPL from read-only memory it is convenient to separate
out the runtime information, so that the devices don't need to be copied
before being used.

Create a new udevice_rt table, similar to the existing driver_rt. For now
it just holds the flags, although they are not used in this patch.

Add a new Kconfig for the driver_rt data, since this is not needed when
of-platdata-inst is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
3a825d3fa7 Revert "sandbox: Disable I2C emulators in SPL"
With recent changes this can be supported again. Add it back.

This reverts commit d85f2c4f29.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
728d04cc72 sandbox: i2c: Support i2c emulation with of-platdata
At present the i2c emulators require access to the devicetree, which is
not possible (by design) with of-platdata.

Add a way for drivers to record the of-platdata index of their emulator,
so that we can still find the emulator.

This allows i2c emulation to work with of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
cc469b7086 dm: Rename device_get_by_driver_info_idx()
This function finds a device by its driver_info index. With
of-platdata-inst we do not use driver_info, but instead instantiate
udevice records at build-time.

However the semantics of using the function are the same in each case:
the caller provides an index and gets back a device.

So rename the function to device_get_by_ofplat_idx(), so that it can be
used for both situations. The caller does not really need to worry about
the details.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
e62ad9c867 sandbox: i2c: Move platdata structs to header files
At present the structs used by these drivers are declared in the C files
and so are not accessible to dtoc. Move them to header files, as required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
168227a199 dm: core: Drop uclass_find_device_by_phandle() with of-platdata
At present this function is included in the build but with of-platdata it
only services to produce a confusing link error complaining about a call
to dev_read_u32_default().

Drop it so that any call to uclass_find_device_by_phandle() is flagged as
an error, making it easier to see what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
6ba46a0f21 dm: core: Drop device_get_by_driver_info()
This function is now only used in a test. Drop it. Also drop
DM_DRVINFO_GET() which was the only purpose for having the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
8813986dfd clk: sandbox: Create a special fixed-rate driver
Create a version of this driver for sandbox so that it can use the
of-platdata struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
4ddc91b32f clk: fixed-rate: Export driver parts for OF_PLATDATA_INST
We need to allow SoCs to create their own drivers for this so that they
can use their own of-platdata structs. To minimise code duplication,
export the driver operations and the ofdata_to_plat() setup function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
cc7ffd3adc clk: sandbox: Move priv/plat data to a header file
At present the structs used by this driver are not accessible outside it,
so cannot be used with OF_PLATDATA_INST. Move them to a header file to
fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Heinrich Schuchardt
57cba225fa dfu: dfu_sf: avoid double free of SPI device
Multiple DFU entities may share the same SPI device. We must make sure that
the SPI device is only freed once.

When using the driver model it is not necessary to free the SPI device.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
2021-03-25 20:15:30 +01:00
Maxim Kochetkov
cad6ffa34d mtd: rawnand: fsl_ifc: fix FSL NAND driver to read all ONFI parameter pages
Linux commit a75bbe71a27 ("mtd: rawnand: fsl_ifc: fix FSL NAND driver to
 read all ONFI parameter pages")

Per ONFI specification (Rev. 4.0), if the CRC of the first parameter page
read is not valid, the host should read redundant parameter page copies.
Fix FSL NAND driver to read the two redundant copies which are mandatory
in the specification.

Signed-off-by: Jane Wan <Jane.Wan@nokia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-23 18:06:07 +05:30
Hou Zhiqiang
ae5cbc43b3 pci: layerscape: Change to allocate zeroed memery for struct ls_pcie
As on some incipient Layerscape platforms (LS1043A series) there isn't
separate PF control register block, these registers reside in the LUT
register block, so when the driver detected there isn't 'ctrl', it will
assign the 'lut' address to the ls_pcie->ctrl.

The current code allocate memory for the struct ls_pcie with random
contents, this can result in skipping to assign the ls_pcie->ctrl with
the 'lut' address, then further crash with the incorrect address.

Fixes: 118e58e26e ("pci: layerscape: Split the EP and RC driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-23 18:06:07 +05:30
Chris Packham
f65774e1f6 rtc: ds1307: Add ds1339 compatible
As far as u-boot is concerned the ds1339 is compatible with the other
devices supported by the ds1307 driver. The Linux driver does expose
some additional functionality but as far as u-boot is concerned just
adding the compatible string is enough.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-23 18:06:07 +05:30
Simon Glass
91bcfdf0b6 dm: core: Skip adding uclasses with OF_PLATDATA_INST
There is no need to ever add new uclasses since these are set up at build
time. Update the code to return an error if this is attempted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:28 +13:00
Simon Glass
967a7d483a dm: core: Set up driver model for OF_PLATDATA_INST
With this we don't need to scan and bind drivers, not even the root
device. We just need to locate the root device that was set up at build
time, then set our root in global_data to point to it.

Update the code to handle this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:28 +13:00
Simon Glass
3fa9f553c0 dm: core: Adjust uclass setup with of-platdata
When OF_PLATDATA_INST is enabled we don't need to create the uclass list.
Instead we just need to point to the existing list. Update the code
accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:28 +13:00
Simon Glass
1ef3af3b27 dm: core: Allow dropping run-time binding of devices
With OF_PLATDATA_INST devices are bound at build time. We should not need
binding of devices at runtime in most cases. However it is inflexible to
absolutely prohibit it, so add an option to control this.

Update the driver model core so that it does not bind devices. Update
device_bind() to return an error if called.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:28 +13:00
Dario Binacchi
929e9940b0 bus: ti-sysc: change in a normal driver
The module defines a duplicate uclass driver for UCLASS_SIMPLE_BUS, but
it is not allowed. This breaks of-platdata and makes the result
non-deterministic.

The driver does not need to be an uclass driver, so lets remove it. I
had turned it into an uclass driver because I thought wrongly it had to
call the dm_scan_fdt_dev routine to work properly, but some tests on the
board have shown otherwise.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Simon Glass
d392d32fd8 dtoc: Generate device instances
Add support for generating a file containing udevice instances. This
avoids the need to create these at run time.

Update a test uclass to include a 'per_device_plat_auto' member, to
increase test coverage.

Add another tab to the driver_info output so it lines up nicely like the
device-instance output.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Simon Glass
ea74c95103 dtoc: Generate uclass devices
Add support for generating a file containing uclass instances. This avoids
the need to create these at run time.

Update a test uclass to include a 'priv_auto' member, to increase test
coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Simon Glass
c4085d733b sandbox: i2c: Rename driver names to work with of-platdata
Some of these do not follow the rules. Make sure the driver name matches
the compatible string in all cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Simon Glass
074197aadf dtoc: Assign a sequence number to each node
Now that we have the alias information we can assign a sequence number
to each device in the uclass. Store this in the node associated with each
device.

This requires renaming the sandbox test drivers to have the right name.
Note that test coverage is broken with this patch, but fixed in the next
one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Heinrich Schuchardt
c803838fa8 dm: error handling dev_get_dma_range()
goto after return has not effect. Calling of_node_put() in case of some
errors and not for others is inconsistent.

Fixes: 51bdb50904 ("dm: Introduce xxx_get_dma_range()")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:26 +13:00
Bin Meng
511dcc3b90 mmc: pci: Fix Kconfig dependency
The PCI MMC driver depends on the generic MMC SDHCI driver,
otherwise it does not compile.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-22 19:23:26 +13:00
Weijie Gao
0b9f1ae586 serial: mtk: rewrite the setbrg function
Currently the setbrg logic of serial-mtk is messy, and should be rewritten.
Also an option is added to make it possible to use highspeed-3 mode for all
bauds.

The new logic is:
1. If baud clock > 12MHz
   a) If baud <= 115200, highspeed-0 mode will be used (ns16550 compatible)
   b) If baud <= 576000, highspeed-2 mode will be used
   c) any bauds > 576000, highspeed-3 mode will be used
2. If baud clock <= 12MHz
   Forced highspeed-3 mode
   a) If baud <= 115200, calculates the divisor using DIV_ROUND_CLOSEST
   b) any bauds > 115200, the same as 1. c)

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Weijie Gao
a449cdb881 pinctrl: mt7629: add jtag function and pin group
The EPHY LEDs of mt7629 can be used as JTAG. This patch adds the jtag pin
group to the pinctrl driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Weijie Gao
70a2b4220e pinctrl: mediatek: do not probe gpio driver if not enabled
The mtk pinctrl driver is a combination driver with support for both
pinctrl and gpio. When this driver is used in SPL, gpio support may not be
enabled, and this will result in a compilation error.

To fix this, macros are added to make sure gpio related code will only be
compiled when gpio support is enabled.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Sam Shih
e254d2c0a4 pinctrl: mediatek: add get_pin_muxing ops for mediatek pinctrl
This patch add get_pin_muxing support for mediatek pinctrl drivers

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2021-03-20 16:24:27 -04:00
Sam Shih
4fc5d4cedb pinctrl: mediatek: fix wrong assignment in mtk_get_pin_name
This is a bug fix for mtk pinctrl common part. Appearently pins should be
used instead of grps in mtk_get_pin_name().

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2021-03-20 16:24:27 -04:00
Andre Przywara
4c49879689 nvme: Elaborate on cache maintenance operation in get/set_features
At the moment the nvme_get_features() and nvme_set_features() functions
carry a (somewhat misleading) comment about missing cache maintenance.

As it turns out, nvme_get_features() has no caller at all in the tree,
and nvme_set_features' only user doesn't use a DMA buffer.

Mention that in the comment, and leave some breadcrumbs for the future,
should those functions attract more users.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-19 10:36:55 -04:00
Andre Przywara
d0c04926cd nvme: Always invalidate whole cqes[] array
At the moment nvme_read_completion_status() tries to invalidate a single
member of the cqes[] array, which is shady as just a single entry is
not cache line aligned.
The structure is dictated by hardware, and with 16 bytes is smaller than
any cache line we usually deal with. Also multiple entries need to be
consecutive in memory, so we can't pad them to cover a whole cache line.

As a consequence we can only always invalidate all of them - U-Boot just
uses two of them anyway. This is fine, as they are only ever read by the
CPU (apart from the initial zeroing), so they can't become dirty.

Make this obvious by always invalidating the whole array, regardless of
the entry number we are about to read.
Also blow up the allocation size to cover whole cache lines, to avoid
other heap allocations to sneak in.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
2021-03-19 10:36:53 -04:00
Dario Binacchi
ccc58b4d32 bus: ti-sysc: change in a normal driver
The module defines a duplicate uclass driver for UCLASS_SIMPLE_BUS, but
it is not allowed. This breaks of-platdata and makes the result
non-deterministic.

The driver does not need to be an uclass driver, so lets remove it. I
had turned it into an uclass driver because I thought wrongly it had to
call the dm_scan_fdt_dev routine to work properly, but some tests on the
board have shown otherwise.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-19 10:35:20 -04:00
Frank Wunderlich
93cac85d78 ahci: mediatek: fix undefined reference of dev_err
building with MTK_AHCI enabled results in implicit declaration and
undefined reference of dev_err followed by a segfault of gcc

drivers/ata/mtk_ahci.c: In function 'mtk_ahci_parse_property':
drivers/ata/mtk_ahci.c:65:4: warning:
implicit declaration of function 'dev_err'
drivers/ata/mtk_ahci.c:65: undefined reference to `dev_err'
in function `mtk_ahci_probe':
drivers/ata/mtk_ahci.c:92: undefined reference to `dev_err'
Segmentation fault

fix this by adding the dm/device_compat.h to includes

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2021-03-19 10:35:19 -04:00
Daniel Golle
30e76b755b mmc: mtk-sd: don't ignore max-frequency from device tree
commit e58e68d9 ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value")
wrongly assumed that plat->cfg.f_max is always unset at the time
mscd_drv_probe() is run. This is not true in case max-frequency being
defined in device tree, as it is then already set by mmc_of_parse()
in msdc_of_to_plat().
Only set plat->cfg.f_max to the default maximum value in case it is
not already set to a sane value.

Fixes: e58e68d93e ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value")
Cc: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2021-03-17 12:27:58 -04:00
Lad Prabhakar
220f308a5c pinctrl: renesas: Add support for R8A774C0
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals.

This patch hooks R8A774C0 SoC with the pfc driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Lad Prabhakar
4ece226e80 pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11
Sync the R8A77990 SoC PFC tables with Linux 5.11 , commit f40ddce88593.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Tom Rini
22fc991daf Prepare v2021.04-rc4
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Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4
2021-03-15 12:15:38 -04:00
Tom Rini
e8a10a02bd - Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
 - Remove the nand MTD configuration for NOR boot in stm32mp1 board
 - STM32programmer update
 - Bsec: manage clock when present in device tree
 - stm32mp15: move bootdelay configuration in defconfig
 - Update for stm32 dsi and dw_mipi_dsi
 - STM32 MCU's cleanup
 - Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
 - Update stm32mp1 doc
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Merge tag 'u-boot-stm32-20210312' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
2021-03-15 08:43:19 -04:00
Jorge Ramirez-Ortiz
5a8783c80c drivers: tee: sandbox: SCP03 control emulator
Adds support for a working SCP03 emulation. Input parameters are
validated however the commands (enable, provision) executed by the TEE
are assumed to always succeed.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-14 11:50:13 -04:00
Simon Glass
e7c920a228 tpm: Correct warning on 32-bit build
Fix the warning:

drivers/tpm/tpm2_tis_sandbox.c: In function ‘sandbox_tpm2_xfer’:
drivers/tpm/tpm2_tis_sandbox.c:288:48: warning: format ‘%ld’ expects
	argument of type ‘long int’, but argument 2 has type ‘size_t’
	{aka ‘unsigned int’} [-Wformat=]
   printf("TPM2: Unmatching length, received: %ld, expected: %d\n",
                                              ~~^
                                              %d
          send_size, length);
          ~~~~~~~~~

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-13 13:14:52 -05:00
Simon Glass
20740e4fbc dm: core: Fix allocation of empty of-platdata
With of-platdata we always have a dtv struct that holds the platform data
provided by the driver_info record. However, this struct can be empty if
there are no actual devicetree properties provided.

The upshot of empty platform data is that it will end up as a zero-size
member in the BSS section, which is fine. But if the driver specifies
plat_auto then it expects the correct amount of space to be allocated.

At present this does not happen, since device_bind() assumes that the
platform-data size will always be >0. As a result we end up not
allocating the space and just use the BSS region, overwriting whatever
other contents are present.

Fix this by removing the condition that platform data be non-empty, always
allocating space if requested.

This fixes a strange bug that has been lurking since of-platdata was
implemented. It has likely never been noticed since devices normally have
at least some devicetree properties, BSS is seldom used on SPL, the dtv
structs are normally at the end of bss and the overwriting only happens
if a driver changes its platform data.

It was discovered using sandbox_spl, which exercises more features than
a normal board might, and the critical global_data variable 'gd' happened
to be at the end of BSS.

Fixes: 9fa2819009 ("dm: core: Expand platdata for of-platdata devices")
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:29 -05:00
Pali Rohár
15942805b7 arm: mvebu: a38x: Remove dead code ARMADA_39X
Config option ARMADA_39X is never set so remove all dead code hidden under
ifdef CONFIG_ARMADA_39X blocks.

Also remove useless checks for CONFIG_ARMADA_38X define as this macro is
always defined for a38x code path.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-12 07:44:21 +01:00
Pali Rohár
2fa30d0484 arm: a37xx: pci: Implement workaround for the readback value of VEND_ID
Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions
document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243):

    The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it
    should read 11ABh.

    The firmware can write the correct value, 11ABh, through VEND_ID
    (RD0076044h [15:0]).

Implement this workaround in U-Boot PCIe controller driver aardvark for
both PCI vendor id and PCI subsystem vendor id.

This change affects PCI vendor id of PCIe root bridge emulated by Linux
kernel. With this change Linux kernel reports correct vendor id 11AB.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-12 07:44:21 +01:00
Marek Behún
74f4929c2c ddr: marvell: axp: fix array types have different bounds warning
The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have
different bounds declared in header files where these variables are also
defined from the ones declared in source files.

This causes the compiler to complain (when building with LTO):
  ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match
                               original declaration
			       [-Wlto-type-mismatch]
  ddr3_patterns_64bit.h:911:5: note: array types have different bounds
  ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously
                                     declared here

ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match
                           original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:167:4: note: array types have different bounds
ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared
                             here

ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match
                           original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:196:4: note: array types have different bounds
ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared
                             here

CI managed to trigger this as an error when compiling with LTO for AXP.

Fix this by using values from the header files, which seem to be the
correct ones.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-03-12 07:44:21 +01:00
Marek Behún
e5b3e87dfa ddr: marvell: axp: align signature of mv_xor_mem_init() with a38x
In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common
XOR definitions, regardless whether we compile for axp or a38x.

But the declaration of this function has a different signature in axp's
xor.h from the one used in a38x' implementation - one parameter is u64
instead of u32. This can result in wrong argument's being passed to that
function on a38x with no one the wiser.

I discovered this when building U-Boot for Turris Omnia with LTO. The
compiler complains about the different signatures being thrown into the
same linking process:

  axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match
                           original declaration [-Wlto-type-mismatch]
   67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size,
      |     ^
  a38x/xor.c:165:5: note: type mismatch in parameter 3
  165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long
      |     ^
  a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match
                          type ‘u32’

Fix this by changing the type of the block_size argument in the axp's
implementation and header file to the one used in a38x (and upstream
mv-ddr-marvell).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-12 07:44:21 +01:00
Pali Rohár
107c3391b9 ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the
commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot").

This patch was created by following steps:

1. Replace all a38x files in U-Boot tree by files from upstream github
   Marvell mv-ddr-marvell repository.

2. Run following command to omit portions not relevant for a38x and ddr3:

    files=drivers/ddr/marvell/a38x/*
    sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files
    unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \
        -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
        -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
        -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files

3. Manually omit SPDX-License-Identifier changes from this patch as
   upstream license in  upstream github repository contains long license
   texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x ddr3 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch is removal of dead code and some fixes with
include files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-12 07:42:37 +01:00
Sujeet Baranwal
a5fc099081 ddr: marvell: a38x: Add more space for additional info from SPD
commit 258be123226f8f5cd516b7813fe201fb7d7416e9 upstream.

At this moment, only page 0 of SPD is being read but to support
smbios, we need to read page 1 also which has more info. In order
to do that, we need to allocate more space.

Signed-off-by: Sujeet Baranwal <sujeet.baranwal@cavium.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Sujeet Kumar Baranwal <Sujeet.Baranwal@cavium.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
2021-03-12 07:42:37 +01:00
Yannick Fertre
c45f82bb2e video: dw_mipi_dsi: update log of dphy_enable
The DSI phy can be turned on from the DSI digital interface in
the dphy_enable() function or from a dedicated DSI phy "wrapper"
in phy_ops->init() function. If the STM32MP1 case, the wrapper
is used then the dphy_enable() "warning" traces are not relevant.

This patch moves these "warning" traces to "debug" traces so
they are still available for DSI phy based on the digital
interface in debug logging mode, but not there in normal mode
for both cases.
Note: The related Linux kernel driver uses a "debug"
message too.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:55:44 +01:00
Yannick Fertre
612f769227 video: dw_mipi_dsi: missing device to log debug
Missing udevice to struct dw_mipi_dsi to log trace.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:55:44 +01:00
Patrick Delaunay
a6d047c0a8 video: stm32: remove all child of DSI bridge when its probe failed
Remove the child device of the STM32 DSI bridge when the driver probe
failed to stop futher probe request on panels used with STMicroelectronics
board (orisetech_otm8009a.c or raydium-rm68200.c driver).

This patch avoid the trace "cannot get reset GPIO" when
STM32MP157 device tree is used on stm32MP151 SOC without DSI support.

In this hw_version value is 0, as DSI bridge is absent and the panel
ofdata_to_platdata is called for each try of panel probe,
the gpio reset pin is requested but after dsi father probe failed).

For the next request, the PANEL ofdata_to_platdata failed as the gpio
is already used.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:55:09 +01:00
Patrick Delaunay
0689dc5323 scmi: cosmetic: reorder include files
Reorder include files in expected order.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:03:19 +01:00
Patrick Delaunay
9f5e4aa66e scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:03:19 +01:00
Patrick Delaunay
1b9ad5198a scmi: Include device_compat.h
Include the file needed for log function prototype, this patch solves the
compilation issue for undefined reference to `dev_err'.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:03:19 +01:00
Etienne Carriere
08db5d5c71 clk: stm32mp1: gets root clocks from fdt
This change makes stm32mp1 clock driver to get the root clocks
reference from the device node in the FDT rather than fetching
straight these clocks by their name. Driver now stores the
clock reference and use it to know if a root clock is present,
get its rate or gets its related udevice reference.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-03-11 17:03:19 +01:00
Patrice Chotard
de6f70a632 mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write()
In case of big area read/write on spi nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and
spinand_mtd_write() to ensure that watchdog is reset.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-11 17:00:41 +01:00
Patrice Chotard
3f6cfdaa23 mtd: nand: Add WATCHDOG_RESET() in nanddev_mtd_erase()
In case of big area erased on nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in nanddev_mtd_erase() to ensure that
watchdog is reset.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-11 16:59:16 +01:00
Patrice Chotard
e48ec51b43 spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo()
In case of reading large area and memory-map mode is misconfigured
(memory-map size declared lower than the real size of the memory chip)
watchdog can be triggered.

Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it.

Issue reproduced with stm32mp157c-ev1 board and memory map size set to
1, with following command:
sf read 0xC0000000 0 0x4000000

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-11 16:59:16 +01:00
Patrice Chotard
5988575a90 mtd: spi-nor: Add WATCHDOG_RESET() in spi_nor_core callbacks
In case of big area write/erase on spi nor, watchdog timeout may occurs.
Issue reproduced on stm32mp157c-ev1 with following commands:

sf write 0xC0000000 0 0x3000000
or
sf erase 0 0x1000000

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-11 16:36:32 +01:00
Chunfeng Yun
044d7003a7 usb: mtu3: flush cache for next GPD
When flush cache of the current GPD and resume QMU, the controller
will try to access the next GPD after processing the current one,
if not flush the next GPD, the controller may get wrong GPD status.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-03-10 11:48:09 +01:00
Simon Glass
049c4dc677 x86: Move INTEL_ACPIGEN to arch/x86
This option is better placed in the x86 code since it is not generic
enough to be in the core code. Move it.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-09 09:42:12 +08:00
Tom Rini
472c5484bc - button: adc: fix treshold typo
- configs: meson64: add fdtoverlay_addr_r
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Merge tag 'u-boot-amlogic-20210308' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- button: adc: fix treshold typo
- configs: meson64: add fdtoverlay_addr_r
2021-03-08 07:41:50 -05:00
Neil Armstrong
efe1f06496 button: adc: fix treshold typo
Fix the treshold typo in code by threshold.

Fixes: c0165c85c3 ("button: add a simple Analog to Digital Converter device based button driver")
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
2021-03-08 10:32:34 +01:00
Siew Chin Lim
9a5bbdfd1a arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-08 10:59:10 +08:00
Bin Meng
5f1a08b6ab dm: sysreset: Add a Kconfig option for the 'reset' command
sysreset uclass driver provides an implementation of 'reset'
command using the sysreset_ APIs unconditionally. It also
supports the 'poweroff' command using the sysreset_ APIs,
but under a Kconfig option CONFIG_SYSRESET_CMD_POWEROFF.

Let's do the same for the 'reset' command, by introducing a
new Kconfig option CONFIG_SYSRESET_CMD_RESET, and set it to
on by default, to allow a board that don't have a sysreset
reset driver yet, but have a sysreset poweroff driver to
compile without any issue.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:43 +05:30
Bin Meng
271a87b4ec gpio: mpc8xxx: Support controller register physical address beyond 32-bit
dev_read_addr_size_index() returns fdt_addr_t which might be a
64-bit physical address. This might be true for some 85xx SoCs
whose CCSBAR is mapped beyond 4 GiB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:43 +05:30
Bin Meng
5474ef886c virtio: Fix VirtIO BLK driver dependency
The VirtIO BLK driver depends on the blk uclass driver.
Add the dependency in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:43 +05:30
Bin Meng
8461ee5115 pci: mpc85xx: Support 64-bit bus and cpu address
At present the driver only supports 32-bit bus and cpu address.
The controller's outbound registers/fields for extended address
are not programmed. Let's program them to support 64-bit bus and
cpu address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:43 +05:30
Bin Meng
03ff970a1b pci: mpc85xx: Support controller register physical address beyond 32-bit
devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit
physical address. Use map_physmem() to return the virtual address
that can be used by a 32-bit machine.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:43 +05:30
Bin Meng
5a40f5c09d pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAW
For the QEMU ppce500 machine, LAW registers are not implemented
hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not
available. We should wrap all LAW registers programming in the
mpc85xx PCI driver with CONFIG_FSL_LAW.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:43 +05:30
Bin Meng
7365a03804 pci: fsl_pci_init: Dynamically allocate the PCI regions
Commit e002474158 ("pci: pci-uclass: Dynamically allocate the PCI regions")
changes 'struct pci_controller'.regions from pre-allocated array of
regions to dynamically allocated, which unfortunately broken lots of
boards that still use the non-DM PCI driver.

This patch changes the non-DM fsl_pci_init driver to dynamically
allocate the regions, just like what's done in the pci uclass driver.

Fixes: e002474158 ("pci: pci-uclass: Dynamically allocate the PCI regions")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:42 +05:30
Tom Rini
668866aa24 - convert sunxi_display to DM_VIDEO
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Merge tag 'next-2021-03-04' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into next

 - convert sunxi_display to DM_VIDEO
2021-03-04 14:36:40 -05:00
Bin Meng
384b62c073 serial: ns16550: Handle zero <clock-frequency> value
A working device tree node of ns16550 should never be populated
with value zero for the <clock-frequency> property. Unfortunately
this is the case for the QEMU ppce500 target.

Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the
last resort to handle such case.

This commit should be reverted when:

- The following QEMU patch [1] is merged, and
- U-Boot CI has upgraded its QEMU version that contains the fix

[1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Bin Meng
09bd08401a serial: ns16550: Correct the base address type
Currently ns16550_serial_assign_base() treats the argument 'base'
with type `ulong`. This is incorrect because the base address was
obtained from device tree with type `fdt_addr_t` that can represent
a physical address larger than 32-bit in a 32-bit system.

Fixes: 9e6ce62190 ("serial: ns16550: Fix ordering of getting base address")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Heinrich Schuchardt
297b8b3ebf sandbox: host bind must close file descriptor
Each invocation of the 'host bind' command with a file name argument opens
a file descriptor. The next invocation of the 'host bind' command destroys
the block device but the file descriptor remains open. The same holds true
for the 'unbind blk' command.

Close the file descriptor when unbinding the host block device.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Simon Glass
15421b71bc dm: core: Add DM_DEVICE_REMOVE condition to all exit paths
At present device_bind() does some unnecessary work if a device fails to
bind in SPL. Add the missing conditions.

Also fix a style nit in the same function while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Simon Glass
24fd7e383d dm: core: Fix allocation of empty of-platdata
With of-platdata we always have a dtv struct that holds the platform data
provided by the driver_info record. However, this struct can be empty if
there are no actual devicetree properties provided.

The upshot of empty platform data is that it will end up as a zero-size
member in the BSS section, which is fine. But if the driver specifies
plat_auto then it expects the correct amount of space to be allocated.

At present this does not happen, since device_bind() assumes that the
platform-data size will always be >0. As a result we end up not
allocating the space and just use the BSS region, overwriting whatever
other contents are present.

Fix this by removing the condition that platform data be non-empty, always
allocating space if requested.

This fixes a strange bug that has been lurking since of-platdata was
implemented. It has likely never been noticed since devices normally have
at least some devicetree properties, BSS is seldom used on SPL, the dtv
structs are normally at the end of bss and the overwriting only happens
if a driver changes its platform data.

It was discovered using sandbox_spl, which exercises more features than
a normal board might, and the critical global_data variable 'gd' happened
to be at the end of BSS.

Fixes: 9fa2819009 ("dm: core: Expand platdata for of-platdata devices")
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Simon Glass
8a45b22057 gpio: Add a way to read 3-way strapping pins
Using the internal vs. external pull resistors it is possible to get
27 different combinations from 3 strapping pins. Add an implementation
of this.

This involves updating the sandbox GPIO driver to model external and
(weaker) internal pull resistors. The get_value() method now takes account
of what is driving a pin:

   sandbox: GPIOD_EXT_DRIVEN - in which case GPIO_EXT_HIGH provides the
          value
   outside source - in which case GPIO_EXT_PULL_UP/DOWN indicates the
          external state and we work the final state using those flags and
          the internal GPIOD_PULL_UP/DOWN flags

Of course the outside source does not really exist in sandbox. We are just
modelling it for test purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 15:40:47 -05:00
Simon Glass
be04f1ab42 gpio: Define the log category in the uclass
This uses log_debug(), etc. but does not define the category. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 15:40:11 -05:00
Simon Glass
d638a18357 gpio: sandbox: Track whether a GPIO is driven
Add a new flag to keep track of whether sandbox is driving the pin, or
whether it is expecting an input signal. If it is driving, then the value
of the pin is the value being driven (0 or 1). If not driving, then we
consider the value 0, since we don't currently handle things like pull-ups
yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:40:11 -05:00
Simon Glass
edab114775 gpio: x86: Drop the deprecated methods in intel_gpio
We don't need to implement direction_input() and direction_output()
anymore. Drop them and use update_flags() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 15:40:11 -05:00
Simon Glass
3d64774716 gpio: Use an 'ops' variable everywhere
Update this driver to use the common method of putting the driver
operations in an 'ops' variable install of calling gpio_get_ops()
repeatedly. Make it const since operations do not change.

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:40:11 -05:00
Simon Glass
ca1e1f57be gpio: Replace direction_input() and direction_output()
The new update_flags() method is more flexible since it allows the
driver to see the full flags all at once. Use that in preference to these
two functions. Add comments to that effect.

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:40:11 -05:00
Simon Glass
7e0a96d559 dm: gpio: Add a way to update flags
It is convenient to be able to adjust some of the flags for a GPIO while
leaving others alone. Add a function for this.

Update dm_gpio_set_dir_flags() to make use of this.

Also update dm_gpio_set_value() to use this also, since this allows the
open-drain / open-source features to be implemented directly in the
driver, rather than using the uclass workaround.

Update the sandbox tests accordingly. This involves a lot of changes to
dm_test_gpio_opendrain_opensource() since we no-longer have the direciion
being reported differently depending on the open drain/open source flags.

Also update the STM32 drivers to let the uclass handle the active low/high
logic.

Drop the GPIOD_FLAGS_OUTPUT() macro which is no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:40:10 -05:00
Simon Glass
e87e86f31c gpio: sandbox: Make sandbox_gpio_set_flags() set all flags
Allow this function to see all flags, including the internal sandbox ones.
This allows the tests to fully control the behaviour of the driver.

To make this work, move the setting of GPIOD_EXT_HIGH -to where the flags
are updated via driver model, rather than the sandbox 'back door'.

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:38:58 -05:00
Simon Glass
0242aecb4c gpio: sandbox: Fully separate pin value from output value
At present we have the concept of a pin's external value. This is what
is used when getting the value of a pin. But we still set the
GPIOD_IS_OUT_ACTIVE flag when changing the value. This is not actually
correct, since if the pin changes from output to input, the external
value need not change. Adjust the logic for this difference.

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:38:58 -05:00
Simon Glass
1f212afc4c gpio: sandbox: Use a separate flag for the value
At present with the sandbox GPIO driver it is not possible to change the
value of GPIOD_IS_OUT_ACTIVE unless the GPIO is an output. This makes it
hard to test changing the flags since we need to be aware of the internal
workings of the driver.

The feature is designed to aid testing.

Split this feature out into a separate sandbox-specific flag, so that the
flags can change unimpeded. This will make it easier to allow updating the
flags in a future patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 15:38:58 -05:00
Simon Glass
a03a0aa7e8 gpio: sandbox: Rename GPIO dir_flags to flags
Adjust the terminology in this driver to reflect that fact that all flags
are handled, not just direction flags.

Create a new access function to get the full GPIO state, not just the
direction flags. Drop the static invalid_dir_flags since we can rely on a
segfault if something is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 15:38:58 -05:00
Simon Glass
c0c1e62c6e gpio: Rename dm_gpio_get_dir_flags() to dm_gpio_get_flags()
This function can be used to get any flags, not just direction flags.
Rename it to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-03-03 14:51:06 -05:00
Simon Glass
9648789e26 dm: gpio: Rename get_dir_flags() method to get_flags()
It is more useful to be able to read all the flags, not just the direction
ones. In fact this is what the STM32 driver does. Update the method name
to reflect this.

Tweak the docs a little and use 'flagsp' as the return argument, as is
common in driver model, to indicate it returns a value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-03-03 14:51:06 -05:00
Simon Glass
13979fc446 dm: gpio: Rename set_dir_flags() method to update_flags()
The current method is a misnomer since it is also used (e.g. by stm32) to
update pull settings and open source/open drain.

Rename it and expand the documentation to cover a few more details.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 14:51:06 -05:00
Simon Glass
4fe406729c gpio: Disable functions not used with of-platdata
These functions use devicetree and cannot work with of-platdata, which has
no runtime devicetree.

If they are used, the current linker error is confusing, since it talks
about missing functions in the bowels of driver model.

Avoid compiling these functions at all with of-platdata, so that a
straightforward link error points to the problem.

Series-changes; 3
- Fix 'wprl' typo

Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-03 14:51:06 -05:00
Tom Rini
52ba373b78 i.MX for 2021.04
----------------
 
 - new boards:
 	- i.MX8MN Beacon EmbeddedWorks (2GB)
 	- Gateworks Venice imx8mm
 - convert to DM:
 	- imx53-qsb, mx53loco, mx51evk, mx23-evk
 - Fixes :
 	- Network : FEC ethernet quirks
 	- DH dh-imx6
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
 -----BEGIN PGP SIGNATURE-----
 
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Merge tag 'u-boot-imx-20210303' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2021.04
----------------

- new boards:
	- i.MX8MN Beacon EmbeddedWorks (2GB)
	- Gateworks Venice imx8mm
- convert to DM:
	- imx53-qsb, mx53loco, mx51evk, mx23-evk
- Fixes :
	- Network : FEC ethernet quirks
	- DH dh-imx6

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
2021-03-03 10:10:34 -05:00
Jagan Teki
5d235324ae video: sunxi_display: Convert to DM_VIDEO
DM_VIDEO migration deadline is already expired, but around
80 Allwinner boards are still using video in a legacy way:

===================== WARNING ======================
This board does not use CONFIG_DM_VIDEO Please update
the board to use CONFIG_DM_VIDEO before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================

Convert the legacy video driver over to the DM_VIDEO framework. This is
a minimal conversion: it doesn't use the DT for finding its resources,
nor does it use DM clocks or DM devices for the outputs (LCD, HDMI, CVBS).

Tested in Bananapi M1+ Plus 1920x1200 HDMI out. (Jagan)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[Andre: rebase and smaller fixes]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 10:03:15 +01:00
Heinrich Schuchardt
795d605cab usb: USB keyboard requires DM_KEYBOARD
If CONFIG_DM_USB=y, the USB keyboard only works if CONFIG_DM_KEYBOARD=y.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-03 04:12:46 +01:00
Pali Rohár
7f98575b7b usb: gadget: Use dbg_ep0() macro instead of serial_printf()
All debug messages from ep0.c except a few are printed by dbg_ep0() macro.
So for remaining few exceptions use also dbg_ep0() instead of serial_printf().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
f2e81c1d38 usb: musb: Ensure that we set musb dynamic FIFO buffer for every endpoint
If we do not set FIFO buffer address and size for some endpoint which is in
use then default programmed address 0x0 would be used which is in conflict
with address of FIFO buffer for endpoint 0. Moreover address of FIFO buffer
for endpoint 0 cannot be programmed, it is fixed to 0x0. Sharing address
space between more endpoints cause data loss and unexpected errors.

This patch is fixing transmission of characters over usbtty serial console
and allows using of usbtty for debugging purposes on Nokia N900.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
f1e8d2072c usb: musb: Fix handling interrupts for EP0 and SET ADDRESS commmand
Interrupt for EP0 is indicated in intrtx register via first bit. This bit
is set for both RX and TX despite register has only TX in its name. First
bit in intrrx register is reserved, not used and never set.

So remove calling musb_peri_ep0() function at every iteration of udc_irq()
and musb_peri_rx() and call it only from musb_peri_tx() when correct
interrupt bit in initrtx it set.

Address from SET ADDRESS command must be set to faddr register only after
acknowledging SERV_RXPKTRDY followed by received EP0 interrupt. So prior
calling musb_peri_ep0_set_address() check for EP0 interrupt instead of
(incorrect) MUSB_INTR_SOF interrupt.

This patch fixes issue that host (computer) cannot register U-Boot USB
device and is failing with errors:

    usb 1-1: new full-speed USB device number 86 using xhci_hcd
    usb 1-1: Device not responding to setup address.
    usb 1-1: Device not responding to setup address.
    usb 1-1: device not accepting address 86, error -71

U-Boot was writing address to faddr register too early and did not wait for
correct interrupt after which should update address.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
ff77bb301e usb: musb: Fix receiving of bigger buffers
If musb_peri_rx_ep() was called to process received HW buffer but U-Boot
cannot read it yet (e.g. because U-Boot SW buffer is full) then interrupt
was marked as processed also when HW buffer stayed unprocessed.

U-Boot tried to process this buffer again when it received interrupt again,
but it can receive it only when sender (host) sends a new data. As sender
(host) is not going to send a new data until U-Boot process current data
this issue caused a deadlock in case sender (host) is emitting data faster
than U-Boot can process it.

Reading musb intrrx register automatically clears this register and marks
interrupt as processed. So to prevent marking interrupt in U-Boot as
processed, adds a new variable pending_intrrx which would contain
unprocessed bits of intrrx register.

For a second step, every time when musb_peri_rx_ep() is called and there
are waiting data to be processed (signaled by MUSB_RXCSR_RXPKTRDY) either
acknowledge sender (via musb_peri_rx_ack()) that whole HW buffer was
processed or set corresponding bit in pending_intrrx that HW buffer was not
fully processed yet and next iteration is required after U-Boot allocates
space for reading HW buffer.

This patch fixes receiving large usb buffers, e.g. file transfer via Kermit
protocol implemented by 'loadb' U-Boot command over usbtty serial console.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
ea7125c4c6 usb: musb: Fix transmission of bigger buffers
If udc_endpoint_write() was called with bigger payload which does not fit
into one USB packet it is needed to transmit payload in more USB packets.
First packet is transmitted by udc_endpoint_write() call itself and other
packets are put into waiting queue.

Implement function musb_peri_tx() which checks if endpoints are ready for
transmit and continue transmission of waiting queue.

This patch fixes sending big output from printenv command over usbtty
serial console.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>>
2021-03-03 04:12:46 +01:00
Pali Rohár
7d7ae28c8b usb: musb: Read value of PERI_RXCSR to 16bit variable
PERI_RXCSR is 16bit register so store its value into 16bit local variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
10bc132510 usb: musb: Fix configuring FIFO for endpoints
This patch fixes configuring FIFOs for one-directional endpoints which have
only one queue (either RX or TX, but noth both).

Size of FIFO buffer is 2^(idx+3) bytes and starting address is 2^(addr+3).
Moreover first 64 bytes are reserved for EP0.

Without this patch if FIFO size specified by caller was zero then idx was
incorrectly calculated (expr. ffs(0)-1) and size overflowed in fifosz
register. This register uses has only 4 bits for FIFO size. Moreover
specifying zero buffer size is not possible (with idx=0 is minimal buffer
size 8 bytes).

So even for one-directional endpoints we need to correctly specify both
(RX and TX) FIFO buffer sizes and its addresses.

This patch is fixing calculation of start address and buffer size to
minimal value and ensures that it would not overlap with buffer reserved
for EP0.

This issue caused loose of packets on USB bus in both directions and
basically usbtty was unusable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
a6f5e1b9cd usb: musb: Always clear the data toggle bit when configuring ep
Without this patch clearing was done only when U-Boot was compiled with
MUSB Host Controller. But clearing of data toggle bit is needed also for
MUSB Device Controller otherwise Device Controller does not work correctly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:45 +01:00
Pali Rohár
7f840c1b26 serial: usbtty: Send urb data in correct order
Function next_urb() selects the last urb data buffer from linked list to
which next data from usbtty's puts function should be appended.

But to check if TX data still exists it is needed to look at the first urb
data buffer from linked list. So check for endpoint->tx_urb (first from the
linked list) instead of current_urb (the last from the linked list).

Successful call to udc_endpoint_write() may invalidate active urb and
allocate new urb in queue which invalidates pointer returned by next_urb()
function.

So call next_urb() prior putting data into urb buffer and call it every
time after using udc_endpoint_write() function to prevent sending data from
usbtty's puts function in incorrect order.

This patch fixes issue that usbtty code does not transmit data when they
are waiting in the tx queue.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:45 +01:00
Pali Rohár
d3fb8fee7d serial: usbtty: Fix puts function
This function has incorrect implementation of prepending CR prior LF.
Without this patch it prepended CR prior whole string which is going to be
written and let LF without leading CR. Fix this issue by inserting CR at
correct place to make output on usbtty serial console more readable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:45 +01:00
Simon Glass
d5cb6687c5 tpm: Use logging in the uclass
Update this to use log_debug() instead of the old debug().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-03-02 15:53:37 -05:00
Simon Glass
13ad993fc7 tpm: Don't include cr50 in TPL/SPL
At present the security chip is not used in these U-Boot phases. Update
the Makefile to exclude it.

Fix a few logging statements while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-03-02 15:53:37 -05:00
Harald Seiler
35b65dd8ef reset: Remove addr parameter from reset_cpu()
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.

Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).

To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.

This transformation was done with the following coccinelle patch:

    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()

    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-02 14:03:02 -05:00
Matthias Brugger
3ac05239b4 rng: iproc_rng200: Enable support for RPi4 armv7
On the RPi4 armv7 build we have the situationt that we use physical
addresses of 64 bit, while the virtual addresses are 32 bit.
Remap the base address in this scenario via map_physmem().

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-03-02 13:53:48 +01:00
Bharat Gooty
76cffd5795 drivers: mmc: iproc_sdhci: enable HS200 mode
Add tuning functionality which is needed for HS200 mode.
For HS200, program the correct needed 1.8 voltage

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-03-02 13:53:37 +01:00
Claudiu Beznea
8bad34a709 pinctrl: at91-pio4: add support for slew-rate
SAMA7G5 supports slew rate configuration. Adapt the driver for this.
For switching frequencies lower than 50MHz the slew rate needs to
be enabled. Since most of the pins on SAMA7G5 fall into this category
enabled the slew rate by default.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-03-02 09:28:33 +02:00
Haibo Chen
0ba116a319 mmc: fsl_esdhc_imx: fix the DTOCV to 0xE
On imx6Q/imx6DL, we find if config the DTOCV to 0~3, it will impact
cmd6 behavior, after cmd6 get transfer complete interrupt, the data0
line will keep low over 5 seconds. This should be a IC bug on imx6Q/DL.
For other platforms, do not has this issue.

To fix this issue, fix the DTOCV to 0xE, the max setting, this also align
with Linux configuration.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
c3e6f99e73 mmc: fsl_esdhc_imx: Add a compatible for i.MX51
Add a compatible for i.MX51 so that i.MX51 can use this driver
via driver model.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-01 10:21:36 +01:00
Tim Harvey
deb78ff34e thermal: imx_tmu: enable monitoring and default alert/critical
Set default critical/alert temperature and enabling monoitoring.

Without calling imx_tmu_enable_msite() monitoring will not be enabled
and read_temperature will return 0. Additionally without setting alert
temperature will cause imx_tmu_get_temp() to spin indefiniately thinking
the system needs to cool.

This resolves the board spinning endlessly when enabling IMX_TMU in the
SPL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-03-01 10:21:36 +01:00
Tom Rini
08cca188c1 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- fastboot updates / fixes
2021-02-26 15:11:08 -05:00
Tom Rini
b839fc9d47 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- new GigaDevice flash ids
- fixes for imx, nxp_spi drivers
2021-02-26 12:41:19 -05:00
Patrice Chotard
0a7e5e5f10 usb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and usb_gadget_register_driver()
Since commit 8745b9ebcc ("usb: gadget: add super speed support")
ums was no more functional on platform which use dwc2_udc_otg driver.

This was due to a too restrictive test which checked that the gadget
driver speed was either FS or HS.

So all gadget driver with max speed set to speed higher than
HS (SS in case of composite gadget driver in our case) are not
allowed, which is wrong.

Update the speed test in usb_gadget_register_driver() and in
dwc2_gadget_start() to allow all gadget driver speed equal or higher
than FS.

Tested on stm32mp157c-ev1 board.

Fixes: c791c8431c ("usb: dwc2: convert driver to DM_USB_GADGET")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-26 15:30:55 +01:00
Heiko Schocher
bc820d5bcc fastboot: add UUU command UCmd and ACmd support
add support for the UUU commands ACmd and UCmd.

Enable them through the Kconfig option
CONFIG_FASTBOOT_UUU_SUPPORT

base was commit in NXP kernel
9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support")

and ported it to current mainline. Tested this patch
on imx6ul based board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-26 15:30:55 +01:00
Sean Anderson
de1728ce4c fastboot: Allow u-boot-style partitions
This adds support for partitions of the form "dev.hwpart:part" and
"dev#partname". This allows one to flash to eMMC boot partitions without
having to use CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT. It also allows one to
flash to an entire device without needing CONFIG_FASTBOOT_MMC_USER_NAME.
Lastly, one can also flash MMC devices other than
CONFIG_FASTBOOT_FLASH_MMC_DEV.

Because devices can be specified explicitly, CONFIG_FASTBOOT_FLASH_MMC_DEV
is used only when necessary for existing functionality. For those cases,
fastboot_mmc_get_dev has been added as a helper function. This allows

There should be no conflicts with the existing system, but just in case, I
have ordered detection of these names after all existing names.

The fastboot_mmc_part test has been updated for these new names.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
ae5e6b4e8f fastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_name
This makes the next commit more readable by doing the move now.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
f3cf964f2d fastboot: Remove mmcpart argument from raw_part_get_info_by_name
The only thing mmcpart was used for was to pass to blk_dselect_hwpart.
This calls blk_dselect_hwpart directly from raw_part_get_info_by_name. The
error handling is dropped, but it is reintroduced in the next commit
(albeit less specificly).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
3f6fb77175 mmc: sandbox: Add support for writing
This adds support writing to the sandbox mmc backed by an in-memory
buffer. The unit test has been updated to test reading, writing, and
erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF
then that can be easily changed.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Tom Rini
99bebbd5b2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- turris_mox: Enhancements, mostlly defconfig changes (Pali)
- pci-aardvark: Set Max Payload Size and Max Read Request Size
                to 512 bytes (Pali)
- pci_mvebu: Minor cleanup and refactoring (Marek)
- Upgrade A38x DDR3 training to version 14.0.0 (Marek)
2021-02-26 07:55:16 -05:00
Tom Rini
d9bc92f554 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2021-02-26 07:54:27 -05:00
Reto Schneider
783a15b351 mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.

As the overlaps are huge, variable names have been generalized
accordingly.

Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.

New hardware features are not supported, namely:
 - Power on reset
 - Unique ID
 - Double transfer rate (DTR)
 - Parameter page
 - Random data quad IO

The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.

The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.

Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 16:01:37 +05:30
Hauke Mehrtens
12926f46fd mtd: nand: spi: Only one dummy byte in QUADIO
The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG

Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 16:01:29 +05:30
Adam Ford
90d76f812b spi: nxp_fspi: Fix error reporting
On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set.  When checking for errors, it only
checks that it is not NULL.  Since positive numbers are not errors,
only check for negative numbers when handling errors.

Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:09:38 +05:30
Marek Behún
2f0c18b158 ddr: marvell: a38x: fix comment in conditional macro
The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
b1b17f8967 ddr: marvell: a38x: bump version to 14.0.0
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
heaterC
420e106ef1 ddr: marvell: a38x: enum mv_ddr_twin_die: change order
commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.

@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.

Signed-off-by: heaterC <airyguy@gmx.de>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
a267943fd9 ddr: marvell: a38x: import code change from upstream
commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
2ab7bbf71e ddr: marvell: a38x: fix memory cs size function
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
b85c6fb065 ddr: marvell: a38x: import header change from upstream
commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
44aeb28c9b ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit
commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.

WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
32e7a6baef ddr: marvell: a38x: add support for twin-die combined memory device
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
    all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
52dd9b96fc ddr: marvell: a38x: add 16Gbit memory devices support
commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Baruch Siach
369e532691 ddr: marvell: a38x: allow board specific ODT configuration
commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
6e0532401b ddr: marvell: a38x: import header change from upstream
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
9c4e06af0b ddr: marvell: a38x: fix memory size calculation using 32bit bus width
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.

- function mv_ddr_spd_die_capacity_user_get() has a bug,
  since it insert a user memory enum to it,
  instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
  at mv_ddr_mem_sz_per_cs_get() function

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
6373a92d42 ddr: marvell: a38x: fix 32bit
commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
4d676739b9 ddr: marvell: a38x: import header change from upstream
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Alex Leibovich
1dbd0bd599 ddr: marvell: a38x: add ddr 32bit ECC support
commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Alex Leibovich
5d88723ca4 ddr: marvell: a38x: add ddr32 support
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
ab7dda724f ddr: marvell: a38x: import header change from upstream
commit a165037ec26f301be75e1fabc263643683e85255 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
69f084f5c6 ddr: marvell: a38x: fix write leveling suplementary algo
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
5ddfd3f441 pci: pci_mvebu: set local dev to number 1
Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.

Let's do it also in U-Boot.

With this commit the pci command in U-Boot prints something like:
  => pci
  Scanning PCI devices on bus 0
  BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  _____________________________________________________________
  00.00.00   0x168c     0x003c     Network controller      0x80

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
10eb2cc344 pci: pci_mvebu: refactor validation of addresses for config access
Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.

We can simplify the code by putting the validation into separate
function.

Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
  (by default this register is set to 0) there is a
  "Marvell Memory controller", which isn't useful in root complex
  mode,
* on all other slots the real PCIe card connected to the PCIe slot.

We can simplify the code even more by simply allowing access only to
the real PCIe card.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
26f7a76ef9 pci: pci_mvebu: debug rd/wr config as other drivers do
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
241d763618 pci: pci_mvebu: cosmetic fix
Write bdf address in a same way in mvebu_pcie_read/write_config.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
201958af10 pci: pci_mvebu: use dev_seq instead of static variable
PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Pali Rohár
cba6edd68b arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.

This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.

Linux has this code too.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Su Baocheng
de76ae36f6 mtd: spi-nor-ids: Add support of flash protection to w25q128
The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents
various models. From Winbond's website, I could only find 3 types of
them:

    W25Q128JV-IQ/JQ
    datasheet:https://www.winbond.com/resource-files/
w25q128jv%20revg%2004082019%20plus.pdf

    W25Q128FV (SPI Mode)
    datasheet: https://www.winbond.com/resource-files/
w25q128fv%20rev.m%2005132016%20kms.pdf

    W25Q128BV
    datesheet: https://www.winbond.com/resource-files/
w25q128bv_revh_100313_wo_automotive.pdf

According to the datasheets, all of these 3 types support BP(0,1,2) and
TB bits in the status register (SR), so it could reuse the flash
protection logic for ST Micro.

So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
flags to the w25q128 entry of spi_nor_ids table.

Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[jagan: remove comments in spi-nor-ids.c]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 13:35:25 +05:30
Alper Nebi Yasak
eb69d797d3 mtd: spi-nor-ids: Add Gigadevice GD25LQ64C
Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on
rk3399-gru-kevin:

    => sf probe
    SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB
    => sf erase 0x600000 0x200000
    SF: 2097152 bytes @ 0x600000 Erased: OK
    => sf test 0x700000 0x1000
    SPI flash test:
    0 erase: 52 ticks, 76 KiB/s 0.608 Mbps
    1 check: 5 ticks, 800 KiB/s 6.400 Mbps
    2 write: 14 ticks, 285 KiB/s 2.280 Mbps
    3 read: 3 ticks, 1333 KiB/s 10.664 Mbps
    Test passed
    0 erase: 52 ticks, 76 KiB/s 0.608 Mbps
    1 check: 5 ticks, 800 KiB/s 6.400 Mbps
    2 write: 14 ticks, 285 KiB/s 2.280 Mbps
    3 read: 3 ticks, 1333 KiB/s 10.664 Mbps

The values are the same as in Linux, except adjusted for the U-Boot
definition of INFO().

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 13:27:42 +05:30
Marek Vasut
c1d264e84e spi: imx: Implement set_speed
The set_speed() callback should configure the bus speed, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-26 13:25:21 +05:30
Heinrich Schuchardt
df88a0e5cd net: cortina_ni: buffer overrun
When copying to a u32 field we should use sizeof(u32) and not
sizeof(*u32) in memcpy.

On 64bit systems like cortina_presidio-asic-emmc_defconfig using
sizeof(*u32) leads to a buffer overrun.

Fixes: febe13b438 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
2021-02-24 16:51:49 -05:00
Heinrich Schuchardt
6b0431dc21 mtd: rawnand: cortina_nand: missing initialization
ca_do_bch_correction() takes a random value from the stack and starts
counting bitflips from this value. Initialize the counter.

This passed unnoticed as the value is finally ignored in the call
hierarchy.

Fixes: 161df94b3c ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-02-24 16:51:49 -05:00
Heinrich Schuchardt
f0bbcdef1b dm: ddr: socfpga: don't assign values that are not used
The values of left_edge[0] and right_edge[0] are overwritten before they
are used. Remove the superfluous assignments.

Fixes: 285b3cb939 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-24 16:51:49 -05:00
Peter Robinson
391a16b710 rng: iProc rng200: Rename ..._platdata variables to just ..._plat
In 8a8d24bd Simon dropped data from all the various _platdata calls
but it seems this wasn't caught for the RNG200 driver from when it
was posted to merged. This fixes that issue.

Fixes: 537f0018 (rng: Add iProc RNG200 driver)
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2021-02-24 16:51:49 -05:00
Vincent Stehlé
25d34b936c virtio: fix off by one device id comparison
VIRTIO_ID_MAX_NUM is the largest device ID plus 1. Therefore a device id
cannot be greater or equal to VIRTIO_ID_MAX_NUM. Fix the comparison
accordingly.

Fixes: 8fb49b4c7a ("dm: Add a new uclass driver for VirtIO transport devices")
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2021-02-24 16:51:48 -05:00