mmc: fsl_esdhc: add pulse width detection workaround

HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
workaroung for the pulse width detection. Apply this workaround in
u-boot, too.

This will make HS400 mode work reliably on the LS1028A SoC.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Michael Walle 2021-03-17 15:01:37 +01:00 committed by Peng Fan
parent bd7b8505f2
commit d3b745f7d0
4 changed files with 12 additions and 1 deletions

View file

@ -48,6 +48,7 @@ config ARCH_LS1028A
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A050382
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select RESV_RAM if GIC_V3_ITS
imply PANIC_HANG

View file

@ -816,3 +816,6 @@ config SYS_FSL_ERRATUM_ESDHC_A001
config SYS_FSL_ERRATUM_A011334
bool
config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
bool

View file

@ -71,7 +71,8 @@ struct fsl_esdhc {
uint sdtimingctl; /* SD timing control register */
char reserved8[20]; /* reserved */
uint dllcfg0; /* DLL config 0 register */
char reserved9[12]; /* reserved */
uint dllcfg1; /* DLL config 1 register */
char reserved9[8]; /* reserved */
uint dllstat0; /* DLL status 0 register */
char reserved10[664];/* reserved */
uint esdhcctl; /* eSDHC control register */
@ -767,6 +768,9 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
/* Set timout to the maximum value */
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
esdhc_clrbits32(&regs->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
return 0;
}

View file

@ -190,6 +190,9 @@
#define DLL_RESET 0x40000000
#define DLL_FREQ_SEL 0x08000000
/* DLL config 1 register */
#define DLL_PD_PULSE_STRETCH_SEL 0x80000000
/* DLL status 0 register */
#define DLL_STS_SLV_LOCK 0x08000000