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mmc: fsl_esdhc: add pulse width detection workaround
HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a workaroung for the pulse width detection. Apply this workaround in u-boot, too. This will make HS400 mode work reliably on the LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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4 changed files with 12 additions and 1 deletions
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@ -48,6 +48,7 @@ config ARCH_LS1028A
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A050382
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select SYS_FSL_ERRATUM_A011334
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select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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select RESV_RAM if GIC_V3_ITS
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imply PANIC_HANG
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@ -816,3 +816,6 @@ config SYS_FSL_ERRATUM_ESDHC_A001
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config SYS_FSL_ERRATUM_A011334
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bool
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config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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bool
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@ -71,7 +71,8 @@ struct fsl_esdhc {
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uint sdtimingctl; /* SD timing control register */
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char reserved8[20]; /* reserved */
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uint dllcfg0; /* DLL config 0 register */
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char reserved9[12]; /* reserved */
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uint dllcfg1; /* DLL config 1 register */
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char reserved9[8]; /* reserved */
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uint dllstat0; /* DLL status 0 register */
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char reserved10[664];/* reserved */
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uint esdhcctl; /* eSDHC control register */
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@ -767,6 +768,9 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
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/* Set timout to the maximum value */
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esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
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if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
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esdhc_clrbits32(®s->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
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return 0;
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}
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@ -190,6 +190,9 @@
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#define DLL_RESET 0x40000000
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#define DLL_FREQ_SEL 0x08000000
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/* DLL config 1 register */
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#define DLL_PD_PULSE_STRETCH_SEL 0x80000000
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/* DLL status 0 register */
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#define DLL_STS_SLV_LOCK 0x08000000
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