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ddr: marvell: a38x: add ddr 32bit ECC support

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commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
This commit is contained in:
Alex Leibovich 2021-02-19 17:11:12 +01:00 committed by Stefan Roese
parent 5d88723ca4
commit 1dbd0bd599
3 changed files with 11 additions and 1 deletions
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5
drivers/ddr/marvell/a38x/mv_ddr_spd.c
View file

@ -217,6 +217,11 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_
return ret_val;
}
void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity)
{
spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity;
}
unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
{
unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;

1
drivers/ddr/marvell/a38x/mv_ddr_spd.h
View file

@ -277,6 +277,7 @@ union mv_ddr_spd_data {
int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]);
enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data);
enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data);
void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity);
unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);

6
drivers/ddr/marvell/a38x/mv_ddr_topology.c
View file

@ -74,6 +74,10 @@ int mv_ddr_topology_map_update(void)
/* update device width in topology map */
iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
/* overwrite SPD configuration, with what the user set */
if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size);
/* update die capacity in topology map */
iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
@ -144,7 +148,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) {
if (tm->bus_act_mask == BUS_MASK_32BIT)
if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);