Commit graph

3037 commits

Author SHA1 Message Date
Hans de Goede
c74384c680 sunxi: Print soc-id from sram controller for sun8i boards
As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-31 14:26:52 +02:00
Hans de Goede
5f8afd704c sunxi: Add conditional magic sram poke for A33
I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-31 14:26:52 +02:00
Tom Rini
0badc648dc Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-03-29 12:58:45 -04:00
Saksham Jain
4a97a0c91d armv8: fsl-lsch3: Disable SMMU during secure boot
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.

For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:22 -07:00
Qianyu Gong
258b8c93ec armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPI
The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-28 17:35:38 -07:00
Vasily Khoruzhick
9cfc059853 pxa: add support for D- and I- caches
Tested with OHCI and pxafb drivers - no issues found

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2016-03-27 09:13:00 -04:00
Vasily Khoruzhick
9ddde3e6ce pxa: start.S: enable SRAM clock
SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2016-03-27 09:12:59 -04:00
Alexander Graf
d990f5c834 arm: Add support for HYP mode and LPAE page tables
We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:17 -04:00
Nishanth Menon
c755e67516 ARM: OMAP5/DRA7: Expose do_set_iodelay
do_set_iodelay can now be used from board files based on needs of the
platforms variation they have.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:15 -04:00
Nishanth Menon
ceb7d77d6f ARM: OMAP5/DRA7: Split iodelay functionality into sub steps
Since many platforms may need different pad configuration required
depending on variation of the platform with minor deltas, it is
easier to maintain a sub step based approach to allow for pin mux
and iodelay configuration which may depend on the platform variations
and need to be done in IO isolation.

While we retain the older __recalibrate_iodelay function which provides
a ready sequencing, __recalibrate_iodelay_start and
__recalibrate_iodelay_end may be alternatively used now and the callers
will be responsible for the correct sequencing of operations.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:15 -04:00
Nishanth Menon
9c90f5135e ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0
Based on data from EMIF configuration tool 1.1.1.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:14 -04:00
Nishanth Menon
3d042e468a ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0
Based on data from EMIF configuration tool 1.1.1. Expected update for
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has
been incorporated as well.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:13 -04:00
Ravi Babu
d851ad3a66 ARM: DRA72x: Add support for detection of SR2.0
Add support for detection of SR2.0 version of DRA72x family of
processors.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:12 -04:00
Peng Fan
7abeec2234 imx: mx7d: move MX7D to Kconfig entry
If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
 will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX7D" to boards using i.MX7 Dual.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-26 14:16:12 +01:00
Peng Fan
9131c18cfa imx: mx6sx: move MX6SX to Kconfig entry
If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-26 14:16:12 +01:00
Stefan Roese
a7f480d92d arm: mx6: Add CCV xPress board support
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:

- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB

This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-26 14:16:12 +01:00
Fabio Estevam
47173483a3 warp7: Add initial support
Add the basic support for Warp7 board.

For more information about this reference design, please visit:

https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-26 14:16:12 +01:00
Leonid Iziumtsev
f7440928e6 mx27: 16-bit wide watchdog registers
Make the watchdog registers 16-bit wide, as they are according to TRM.

Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-25 14:03:28 +01:00
Marek Vasut
b10d93ee9e arm: imx6: Switch DDR3 calibration to wait_for_bit()
Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-03-25 14:01:29 +01:00
Peng Fan
d78e7f2794 imx: print ARM clock for clocks command
Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=> clocks
PLL_SYS         792 MHz
PLL_BUS         528 MHz
PLL_OTG         480 MHz
PLL_NET          50 MHz

ARM          396000 kHz
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-25 13:57:19 +01:00
Peng Fan
7082d87916 imx: mx6ul configure the PMIC_STBY_REQ pin as open drain
Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-25 13:56:55 +01:00
Peng Fan
e4dc3fc068 imx: mx6ul: skip setting ahb rate
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-25 13:56:40 +01:00
Ye Li
b777789ebd imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2016-03-25 13:55:54 +01:00
vishnupatekar
e449e840c5 sunxi: A83T: fix 32bit overflow warning
In mctl_channel_init, (0x50<<26) which overflows 32bit.
It was supposed to be 0x50<<16,corrected now.

Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-23 22:04:13 +01:00
Hans de Goede
fc8991c61c sunxi: Fix gmac not working due to cpu_eth_init no longer being called
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.

This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().

The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.

Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
2016-03-23 22:04:13 +01:00
Hans de Goede
60fa63012f sunxi: Add support for USB vbus pin for USB3
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
1da598208d sunxi: Fix clock_twi_onoff for sun9i
Fix a copy and paste error which caused us to use the uart rather then
the twi reset bits in clock_twi_onoff for sun9i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
a93b0fe3fd sunxi: Fix clock_twi_onoff for sun8i-a83
clock_sun8i_a83.c did not contain a clock_twi_onoff implementation
at all, this is fixed by moving the clock_sun6i.c implementation,
which is correct for the a83 too, to a shared location.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
730d2f3a41 sunxi: Fix clock_twi_onoff for sun6i
The clock_sun6i.c implementation was not deasserting the reset for
the regular i2c controllers, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
583fede8ee sunxi: A23: Fix some revisions needing a different magic sram poke
I've had this one a23 tablet which would not boot and I've finally
figured out what the problem is by looking at the released boot0 code,
it seems the magic sram controller poke which we need to do in s_init()
depends on the revision of the a23.

Specifically this change is needed to get the A23 SoC I have with the
following serial to boot: "E6071AB 26Y7".

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Simon Glass
c1352119fd arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled
Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:09 -04:00
Yangbo Lu
e477f4bdd4 armv8/fsl-lsch2: fix sdhc clock frequency value
The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:14 -07:00
Pratiyush Srivastava
b2b877306c armv8: fsl-layerscape: Updating entries in Serdes Table
The serdes protocol entries in  Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
2d97fbb4c4 armv8: ls2080a: remove obsolete stream ID partitioning support
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
Prabhakar Kushwaha
2b690b9837 armv8: lsch3: Enable WUO config for RNI-20 node
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Alexander Graf
c05016ab0b arm64: Fix layerscape mmu setup
With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.

On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.

Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Stefano Babic
312a6c016a Merge branch 'next' 2016-03-20 22:04:29 +01:00
Tom Rini
f8a4826383 spl: arm: Make sure to include all of the u_boot_list entries
Starting with 96e5b03 we use a linker list for partition table
information.  However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well.  While doing this, it's
best to simply include all linker lists to future proof ourselves.

Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16 15:27:55 -04:00
Tom Rini
f5af0827f2 arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX
On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size.  Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16 15:03:48 -04:00
Alexander Graf
4c2cc7c4e9 arm64: Allow exceptions to return
Our current arm64 exception handlers all panic and never return to the
exception triggering code.

But if any handler wanted to continue execution after fixups, it would
need help from the exception handling code to restore all registers.

This patch implements that help. With this code, exception handlers on
aarch64 can successfully return to the place the exception happened (or
somewhere else if they modify elr).

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 21:30:10 -04:00
Alexander Graf
50149ea37a efi_loader: Add runtime services
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.

This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.

We could maybe in the future map U-boot environment variables to EFI variables
here.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-03-15 18:03:10 -04:00
Alexander Graf
19503c3117 arm64: Only allow dcache disabled in SPL builds
Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:11 -04:00
Alexander Graf
7985cdf74b arm64: Remove non-full-va map code
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:10 -04:00
Alexander Graf
96519f31cb zymqmp: Replace home grown mmu code with generic table approach
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:03 -04:00
Alexander Graf
d473f0c621 thunderx: Move mmu table into board file
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:02 -04:00
Alexander Graf
5e2ec773bb arm64: Make full va map code more dynamic
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:01 -04:00
Alexander Graf
9bb367a590 arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:00 -04:00
Alexander Graf
0691484ac1 thunderx: Calculate TCR dynamically
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:12:59 -04:00
Paul Kocialkowski
69847dd8f0 omap4: Check warm reset for reboot mode validity
Since the SAR registers are filled with garbage on cold reset, this checks for a
warm reset to assert the validity of reboot mode.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:54 -04:00
Paul Kocialkowski
faec3f9841 omap4: Reboot mode support
Reboot mode is written to SAR memory before reboot in the form of a string.

This mechanism is supported on OMAP4 by various TI kernels.

It is up to each board to make use of this mechanism or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:53 -04:00
Paul Kocialkowski
6e495a453f omap4: Properly enable USB PHY clocks
This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:50 -04:00
Paul Kocialkowski
5e56b0a80e omap-common: clocks-common: Setup USB DPLL when MUSB is in use
On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY
to work properly. The internal PHY is used by default with the MUSB USB OTG
controller.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:49 -04:00
Paul Kocialkowski
ae51b5709e Amazon Kindle Fire (first generation) codename kc1 support
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.

It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:48 -04:00
Paul Kocialkowski
14689ad79e omap4: Move i2c clocks enable to enable_basic_clocks
I2C is often enabled withing the U-Boot SPL, thus those clocks are required to
be enabled early (especially when the bootrom doesn't enable them for us).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:47 -04:00
Paul Kocialkowski
437086b1da omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespace
This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin
enable_basic_uboot_clocks. Also, a doubled whitespace is removed.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:46 -04:00
Paul Kocialkowski
3832e54673 omap-common: Remove deprecated arch_cpu_init code
save_omap_boot_params is called from spl_board_init in the SPL context. Thus,
there is no reason to duplicate that call on arch_cpu_init.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:46 -04:00
Paul Kocialkowski
3ef56e61c8 omap-common: Rename set_muxconf_regs_essential to set_muxconf_regs
There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:06 -04:00
Paul Kocialkowski
ed5ddebe96 omap4: Export jedec sdram timings
Individual boards might provide their own emif_get_device_timings function and
use the jedec timings in their own way, hence those have to be exported.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:32 -04:00
Paul Kocialkowski
96703acd0a omap4: Export elpidia sdram timings
Individual boards might provide their own emif_get_device_timings function and
use the elpidia timings in their own way, hence those have to be exported.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:31 -04:00
Paul Kocialkowski
7cb998ba85 omap4: Export elpidia sdram device details
Individual boards might provide their own emif_get_device_details function and
use elpidia device details in their own way, hence those have to be exported.

This also wraps existing definitions with the proper ifdef logic.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:30 -04:00
Paul Kocialkowski
90ca5dfec4 omap3: Use a define for reboot reason offset
This introduces a define for the offset to the reboot reason, rather than
hardcoding it.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 15:10:48 -04:00
Paul Kocialkowski
c5412b084b omap3: String-based reboot mode handling
This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 15:10:47 -04:00
Tom Rini
4d339a9e8a Merge branch 'master' of git://git.denx.de/u-boot-video 2016-03-15 08:01:17 -04:00
Masahiro Yamada
0ea6cc1253 arm64: define _image_binary_end to fix SPL_OF_CONTROL
To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be
defined in the linker script.

 LD      spl/u-boot-spl
lib/built-in.o: In function `fdtdec_setup':
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

Note:
CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:52 -04:00
Lokesh Vutla
a7638833b3 ARM: DRA7: Move emif settings to board specific files
The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.

Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-14 19:18:50 -04:00
Lokesh Vutla
25afe55de5 ARM: DRA7: Enable EEPROM support
Enable EEPROM support for DRA74-evm.

Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-14 19:18:50 -04:00
Adam Ford
2f6ed3b89a ARM: Various: Future-proof serial platdata
A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.

Tested on the Logic PD Torpedo + Wireless.

I only changed a handful of devices that used the same syntax as the Logic
board.  Appologies if I missed one or stepped on toes.  Thanks to Derald Woods
and Alexander Graf.

Signed-off-by: Adam Ford <aford173@gmail.com>

V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c

V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c

V4: Fix subject heading

V3: Remove  reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.

V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-14 19:18:48 -04:00
Lokesh Vutla
e850ed82bc ARM: OMAP4+: Allow arch specfic code to use early DM
Early system initialization is being done before initf_dm is being called
in U-Boot. Then system will fail to boot if any of the DM enabled driver
is being called in this system initialization code. So, rearrange the
code a bit so that DM enabled drivers can be called during early system
initialization.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:48 -04:00
Lokesh Vutla
29c20ba235 ARM: DRA7: emif: Enable interleaving for higher address space
Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Lokesh Vutla
e3ce3aa103 ARM: DRA7: emif: Check for enable bits before updating leveling output
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Lokesh Vutla
4571c519b4 ARM: DRA7: emif: Fix DDR init sequence during warm reset
Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:46 -04:00
Lokesh Vutla
de09547478 ARM: DRA7: emif: Fix updating of refresh ctrl shadow
On DRA7, refresh ctrl shadow should be updated with
the final value.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:46 -04:00
Kipisz, Steven
212f96f6bd board: ti: AM57xx: Add detection logic for AM57xx-evm
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).

The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.

Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.

NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.

This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:35 -04:00
Kipisz, Steven
d88d6c8ccf ARM: OMAP4/5: Add generic board detection hook
Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override from board files that may desire to do
so.

NOTE: All TI EVMs are capable of detecting board information based on
early clocks that are configured. However, in case of additional needs
this can be achieved within the override logic from within the board
file.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:34 -04:00
Kipisz, Steven
93e6253d11 ARM: OMAP4/5: Centralize early clock initialization
Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.

By splitting up prcm_init and centralizing this clock initialization,
we setup the code for follow on patches that can do board specific
initialization such as board detection which will depend on these
basic clocks.

As part of this change, since the early clock initialization
is centralized, we no longer need to expose the console clock
initialization.

NOTE: we change the sequence slightly by initializing console clocks
timer after the io settings are complete, but this is not expected
to have any functioanlity impact since we setup the basic IO drive
strength initialization as part of do_io_settings.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:32 -04:00
Peng Fan
00b1d2d317 imx: mx6: hdmi: handle overflow condition
If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-14 22:53:45 +01:00
Fabio Estevam
e25a0656ba mx7: Distinguish between dual and solo versions
Read the number of cores in the fuses to distinguish between
the dual and solo versions.

Tested on a mx7d sabresd and on a mx7solo warp7.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-09 12:50:39 +01:00
Akshay Bhat
f9162b15c1 arm: imx: Add support for GE Bx50v3 boards
Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-09 12:45:42 +01:00
Alexander Graf
22d90d560a omap3: Use raw SPL by default for mmc1
Now that we fall back to the FS code path when we don't find u-boot
at the raw sector offset, there is no good reason to not default to
raw boot.

With this patch, I can successfully boot u-boot from a raw sector
offset on beagle-xm.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-08 15:01:46 -05:00
Paul Kocialkowski
23a004a63f sniper: Various minor cleanups, missing Kconfig configs and reorganisation
This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-29 14:49:37 -05:00
Yuichiro Goto
ba10b852fe ARM: start.S: fix typo
Fix typo in comment about position of 'A' bit in several start.S.

Signed-off-by: Yuichiro Goto <goto.yuichiro@espark.co.jp>
2016-02-29 14:49:35 -05:00
Tom Rini
e1417c7b66 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-02-24 18:44:15 -05:00
Alison Wang
a08b1921b4 armv7: ls102xa: Move smmu and stream id initialization into the common soc code
The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:15 -08:00
Qianyu Gong
0e52b6fea1 armv8/fsl-layerscape: fdt: add fixup for Fman ucode
Add fdt fixup to insert Fman firmware into the device tree.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:14 -08:00
Mingkai Hu
bbc8e053ba armv8/ls1043a: Implement workaround for erratum A009660
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:56 -08:00
Jelle van der Waa
dc44fd8ae4 sunxi: H3: Add support for the host usb-phys
Add support for phy 1-3.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-02-23 20:59:10 +01:00
Tom Rini
595af9db24 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-02-21 07:56:16 -05:00
Peng Fan
35c4ce5e20 imx: mx7d: isolate resources to domain 0 for A7 core
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.

So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.

This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
83703a1ccf imx: mx7: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
0623d375cf imx: mx6: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
677656bdb5 imx: mx7d: clock support for RDC
If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Soeren Moch
1a43dc11a3 imx: mx6: Implement mmc_get_env_part
commit 216d286c7e [imx: mx6: implement
mmc_get_env_dev] introduced selection of the environment device according
to the boot device when booting from SD/MMC.

Extend this functionality for also selecting the device partition.

Signed-off-by: Soeren Moch <smoch@web.de>
2016-02-21 11:31:44 +01:00
David Müller (ELSOFT AG)
26275dae82 arm: build some file(s) as ARM mode only
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15 12:04:46 -05:00
Adam Ford
2cd1ff8403 OMAP3_LOGIC: Setup defconfig to enable SPL and NAND booting
The defconfig patch will enable the the SPL and NAND settings.
The update to Kconfig will allow the SPL to configured in and
built.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-08 10:10:39 -05:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Peng Fan
216d286c7e imx: mx6: implement mmc_get_env_dev
Implement mmc_get_env_dev, devno can be got from smbr1 of SRC.
Introduce a weak function board_mmc_get_env_dev, different
boards can implement it according to different sdhc controllers
that used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-04 10:13:49 +01:00
Peng Fan
62d8cce9f3 imx: mx7dsabresd: move mmc_get_env_devno to soc code
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-04 10:13:45 +01:00
Ye Li
23e2da27d3 imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation
The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-02 21:25:50 +01:00
Ye Li
9655ebdd50 imx: mx6sx: Fix issue in LCDIF clock enablement
Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always
enter the -EINVAL return.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-02 21:25:05 +01:00
Ye Li
cf94a3427a imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:04:21 +01:00
Ye Li
d4d1dd6749 mx6: soc: Add ENET2 mac address support
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:03:59 +01:00
Marek Vasut
d339f16911 arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-02 20:58:46 +01:00
Tom Rini
008e61f512 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-02-02 06:51:05 -05:00
Ashish kumar
2ea3a448cc armv8: ls2080a: Implement workaround for core errata 829520, 833471
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.

833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01 13:58:22 -08:00
Wang Dongsheng
c5e954eccd ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.

Use readelf -t -r u-boot show us:
.__secure_start		addr: 601408e4
.__secure_end		addr: 60141460

60141140  00000017 R_ARM_RELATIVE
46	_secure_monitor:
47	#ifdef CONFIG_ARMV7_PSCI
48      ldr     r5, =_psci_vectors

60141194  00000017 R_ARM_RELATIVE
6014119c  00000017 R_ARM_RELATIVE
601411a4  00000017 R_ARM_RELATIVE
601411ac  00000017 R_ARM_RELATIVE
64	_psci_table:
66	.word	psci_cpu_suspend
...
72	.word	psci_migrate

60141344  00000017 R_ARM_RELATIVE
6014145c  00000017 R_ARM_RELATIVE
202	ldr     r5, =psci_text_end

Solutions:
1. Change absolute address to RelAdr.
   Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.

2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
   If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-31 16:32:56 +01:00
Marek Vasut
11aa6a32eb arm: cache: Implement cache range check for v7
Add code to aid tracking down cache alignment issues.
In case DEBUG is defined in the cache.c, this code will
check alignment of each attempt to flush/invalidate data
cache and print a warning if the alignment is incorrect.
If DEBUG is not defined, this code is optimized out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
2016-01-31 16:32:56 +01:00
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Bin Meng
afe6462da9 arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()
eth_get_dev_by_index() is an API which is not available in driver
model. Use eth_get_dev_by_name() instead, which can also simplifly
the code logic a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:23:22 -06:00
Tom Rini
cd85bec36d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-01-27 15:05:36 -05:00
Gong Qianyu
166ef1e90c armv8/ls1043aqds: add QSPI support in SD boot
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:28:55 -08:00
Aneesh Bansal
d041288586 secure_boot: enable chain of trust for ARM platforms
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:49 -08:00
Michal Simek
be6f6af1d6 ARM64: zynqmp: Add initial support for the first silicon
Add basic configuration for the first silicon.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
0785dfd8a7 ARM64: zynqmp: Use the same U-Boot version with/without ATF
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Vishnu Patekar
f3ad64c88c sunxi: Add support for LPDDR3 for A83T
Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T.
Mostly the timing parameters are different from DDR3.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Vishnu Patekar
f5fd8caf7f sunxi: Groundwork to support new dram type for A83T
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.

This adds groundwork to support for new DRAM type for A83T.

Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Vishnu Patekar
627b380f62 sunxi: Redundant code cleanup from a83t dram init
This removes the redundant lines of code from mctl_sys_init.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
9683945179 sunxi: Support PSCI ops on Allwinner H3
H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
ed80584f30 sunxi: Support H3 CCU security switches
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.

Configure them to enable non-secure access.

For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
5823664fb8 sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3
Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.

Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.

This patch supports the new settings, and sets them to allow non-secure
access.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:04 +01:00
Pratiyush Mohan Srivastava
191e3c0527 armv8: Enable all 8 DPMAC ports in LS2080A Personality
LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:17 -08:00
Tang Yuantian
1ef7ac70e2 arm: ls1021a: Adjust sata register default values
Updated the default sata register values to enhance the
performance and stability.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Prabhakar Kushwaha
6f14e257c4 armv8: fsl-lsch3: fixup SYSCLK frequency in device tree
SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.

So Fixup Linux device tree from boot-loader.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Peng Fan
d9699de85c imx: mx7: default enable MDIO open drain
The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:15:14 +01:00
Peng Fan
9ba18ff8ef imx: mx6ul/sx: fix mmdc_ch0 clk calculation
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.

Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:13:21 +01:00
Tom Rini
6905f4d3c7 Merge git://git.denx.de/u-boot-dm 2016-01-21 11:49:49 -05:00
Jelle van der Waa
9d0826879e sunxi: Add support for the I2C controller which is part of the PRCM
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-01-21 07:30:01 +01:00
Mugunthan V N
28a6c01187 arm: omap-common: do not build timer when CONFIG_TIMER defined
To prepare timer driver to DM/DT conversion do not build the
exiting timer driver when CONFIG_TIMER is defined. But since
omap's SPL doesn't support DM yet so built timer driver only for
SPL build when CONFIG_TIMER is defined.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-20 19:06:21 -07:00
Vikas Manocha
0a61ee880c stm32: move stm32 specific code to mach-stm32
This patch moves stm32 sources at one place, with this armv7m now contains
only generic stuff.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-01-20 10:19:41 -05:00
Ladislav Michl
bfb7cc3340 armv7: Add missing newline after OMAP die ID
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Enric Balletbo Serra <enric.balletbo@collabora.com>
2016-01-20 10:19:38 -05:00
Sergey Temerkhanov
a5b9fa30ce armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure
This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)

The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
2016-01-19 22:25:36 +00:00
Sergey Temerkhanov
94f7ff36e5 armv8: New MMU setup code allowing to use 48+ bits PA/VA
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
2016-01-19 22:25:36 +00:00
Vladimir Zapolskiy
1222305b55 arm: lpc32xx: switch SPL builds to driver model
For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.

Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.

The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-13 21:05:22 -05:00
Vladimir Zapolskiy
d25ba89e8b arm: lpc32xx: switch serial console to driver model
On NXP LPC32xx platform for non-SPL builds the change adds
standard (NS16550) and high-speed UARTs to driver model.
Due to specific of DM NS16550 device description UART clock can not be
got in runtime and by default it is set to 13MHz, if board PERIPH_CLK
is different, this should be specified in board configuration file.

For SPL builds HSUARTs are disabled and non-DM NS16550 driver is
compiled, if needed.

The change also updates default configs of devkit3250 and work_92105
boards to reflect updates in platform files.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-13 21:05:22 -05:00
Tom Rini
90345c92a8 am33xx/am43xx: Add platform data for GPIOs
On these platforms we have many cases of boards that enable device model
and GPIO support but do not enable OF_CONTROL and pass in a device tree
with the binary.  We need to bring in the platform data here as well.

Tested on Beaglebone Black.

Reported-by: Robert Nelson <robertcnelson@gmail.com>
Reported-by: Francisco Aguerre <franciscoaguerre@gmail.com>
Reported-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-08 10:15:45 -05:00
Tom Rini
f1993ca066 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-01-03 10:32:24 -05:00
Michael Heimpold
fe21eaf92d ARM: mxs: allow boards to select DC-DC switching clock source
For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.

For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.

Example:
void mxs_power_setup_dcdc_clocksource(void)
{
    mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-01-03 15:56:36 +01:00
Peng Fan
839479dda6 imx: ddr: drop duplicated debug info
Drop duplicated debug info for tcl.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-03 15:19:58 +01:00
Mingkai Hu
0d6faf2bd0 armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Tom Rini
e6e3faa5c2 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-12-14 20:27:23 -05:00
Tang Yuantian
989c5f0a8f armv8: Add sata support on Layerscape ARMv8 board
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
Aneesh Bansal
70f959c3c4 armv8: Make SEC read/write as snoopable for LS1043
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:34 +08:00
Aneesh Bansal
b644d3e932 armv8: define usec2ticks function
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:34 +08:00
York Sun
c04921414c armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
York Sun
c107c0c05c armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
Yao Yuan
000f4e7686 move erratum a008336 and a008514 to soc specific file
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Yao Yuan
6c4a1eba3f armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Yao Yuan
0b8bc6314e armv7: ls102xa: cci-400: Enable snoop and DVM message requests.
Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:56:53 +08:00
Tom Rini
312db9f75f armv7: omap-common: Rework SPL board_mmc_init()
Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional.  For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC).  A further rework and consolidation of the
functions should be done at a later date.

Tested on Beaglebone Black (SD and eMMC boot).

Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-14 13:42:54 -05:00
Yao Yuan
762b353546 arm: ls102xa: enable all the snoop signal for masters.
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Yao Yuan
7ba0261810 arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00