Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.
Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[scottwood@freescale.com: fix fsl_ifc_sram_init prototype]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Document parameters used for specifying the NAND image to be loaded.
Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory. The word "simple" is
there for a reason. :-)
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: updated for makefile changes earlier in patchset
Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
nand_ecc.c:82:5: warning: symbol 'nand_calculate_ecc' was not declared. Should it be static?
nand_ecc.c:155:5: warning: symbol 'nand_correct_data' was not declared. Should it be static?
nand_base.c:2854:1: error: directive in argument list
nand_base.c:2856:1: error: directive in argument list
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
cfi_flash.c:756:43: warning: Using plain integer as NULL pointer
cfi_flash.c:1150:52: warning: cast to non-scalar
cfi_flash.c:1433:46: warning: cast truncates bits from constant value (890089 becomes 89)
cfi_flash.c:1490:61: warning: cast truncates bits from constant value (1f001f becomes 1f)
cfi_flash.c:1508:61: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1738:63: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1857:6: warning: symbol '__flash_cmd_reset' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
Add the missing bits to the Tegra NAND driver to make ONFI detection work
properly.
Also add it to the Tegra default config, as it seems to be a reasonable thing
to have it available on all boards that use any kind of NAND.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.
All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Due to grown code sizes the TQM85xx boards don't build any more with
some older tool chains (like ELDK 4.2). As these boards have long
reached EOL it seems a waste of effort trying to fix them. The vendor
has agreed to drop support for them, too. So let's get rid of them.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Use the same IP revisions as in Linux in order to make the comparison more
clear.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Merge mxc_setup_config1() into board_nand_init() in order to ease the addition
of i.MX5 support in the following patches.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
mxc_nand_read_page_raw_syndrome() should reenable ECC upon exit. This fixes ECC
errors left uncorrected after a call to this function.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use _mxc_nand_enable_hwecc() instead of duplicating its code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patches fixes the TODO to use same register definitions in mtd mxc_nand and
nand_spl fsl nfc drivers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <computersforpeace@gmail.com>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND_CMD_ constants for lock/unlock should be in the header
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[scottwood@freescale.com: updated docs and added comment about invert bit]
Signed-off-by: Scott Wood <scottwood@freescale.com>
With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
This is commit 637957551c0ac80de8dfc7650d320c5a98c2c0c0 from Linux
Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
[scottwood@freescale.com: picked from Linux into U-Boot]
Reported-by: Rafael Beims <rafael.beims@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Using common spi flash operation function to replace private operation
funtion
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
With Simon Glass's include/nand.h alignment changes, some mxs builds
were generating errors. Fix is to ensure asm/cache.h is included before
linux/mtd/nand.h. Moving common.h to top of include list does that.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Check for ctrlc() in operations that take time and loop over the flash
addresses.
In netconsole, tstc() is expensive. Only check once in a while to not
slow down the operation significantly.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added an optional check in the CFI driver to evaluate if the sector is
already blank before issuing an erase command. Improves erase time by
over a factor of 10 if already blank.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.
To use PMECC in this driver, the user needs to set the PMECC correction
capability, the sector size and ROM lookup table offsets in board config file.
This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference
is in this version it uses registers structure access hardware instead of using macros.
It is tested in 9x5 serial boards.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[rebase]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch
1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support.
2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix empty newline at EOF error and move return value check into ifdef]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Orjan Friberg wrote at [1]:
"For the beagleboard, ecc.size is not explicitly set when doing 'nandecc
sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's
set to 256 bytes.
When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when
changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly
the format has changed."
No patch has been submitted and the issue was still present. This patch
adds the mentioned solution. Tested on a tam3517 board.
[1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html
cc: Orjan Friberg <of@flatfrog.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: Add support for S25FL256S
sf: winbond: fix page_size
sf: stmicro: add support for N25Q128A
sf: stmicro: add support N25Q128 parts
sf: stmicro: support JEDEC standard two-byte signature
sf: winbond: add W25Q32
cmd_spi: remove superfluous semicolon
Signed-off-by: Wolfgang Denk <wd@denx.de>
Commit a4ed3b6 "sf: inline data constants" modified winbond.c's page_size
from 256 to 4096. This prevents either/both of "sf write" writing the
correct data, or "sf read" from reading the correct data back.
This allows U-Boot running on Compulab Tegra to upgrade itself.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 54652991
Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips
fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads
to problems for smaller versions of this chip e.g. the 32Mbit version
with deviceid 0x16 on mgcoge. So move the code for this work around to
an own function and check previously manufacturer id and device id to
not break other flashes which don't need this work around.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Philippe De Muyter <phdm@macqel.be>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Erasing flash sectors protected with persistent protection bit (PPB)
mechanism on Spansion flash chips doesn't work. Add sector protection
status checking and sector lock and unlock commands to fix this.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Adds support for Numonyx's N25Q128 SPI flash. These devices
are used on (among others) Avnet Spartan-6 LX9 micro-evaluation
boards. Tested with "sf" commands and CONFIG_ENV_IS_IN_SPI_FLASH.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
There are more than the M25Pxx serial flashs that can be
used with the stmicro driver, for example: the M25PXxx or
N25Qxx serie. All these chips have burned in the original
stmicro manufacture id 0x20 together with a standard
two-byte signature.
In preperation to support all these chips the stmicro driver
have to decode the full two-byte signature.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
SMDK EVT1 has a different Winbond part, added its part details
to the SPI flash table.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Note: because 4-byte addressing is not supported yet,
at the moment only the first 16MiB of the device are available.
Signed-off-by: Jérôme Carretero <cJ@zougloub.eu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The only two drivers to write the status register do it in the same
way, so unify the implementations. This also makes the block unlock
logic the same.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The local sst enable/disable write funcs don't really add anything
over the common API, so just inline the common calls directly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Analysis of the flash drivers shows that they all use 0x20 if the erase
size is 4KiB, or 0xd8 if it's larger. So with this info in hand, we can
unify all the erase functionality in one place.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
I imagine much of these constants are due to copy & pasting previous
drivers rather than an actual reflection of the hardware layout. At
any rate, inline the info that we don't care about externally as it
shrinks things nicely.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
In an effort to unify the spi flash drivers further, drop all the
unused and/or duplicate command defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Needed for redundant environment for example.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
There are two problems in the current timeout loop implementation:
1. In case initial test failing, there will always be a delay of 1 ms
2. The delay duration is not tunable
The new implementation addresses both these limitations.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
If the flash size was smaller than 1MB then flash_print_info()
was erroneously reporting 0 MB.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
THis patch introduces a new methodology for flash probing
in which flash_devices[] table, looked-up thru the dev_id, is
used to locate the flash geometry and information.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since the smi erase code is very generic and works for any kind
of flash, there is no need to test for ST_M25Pxx_ID flash types
like m25p40 flashes).
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
smi_read_sr fails sometimes because of TFF not getting set within assumed time.
This condition may arise because of, for example, smi memory being in a erase
mode.
This fix is to enable reading the status register until timeout.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SMI driver read status fails because the control register could not be
overwritten. Instead, the read status should be tried until timeout.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit does the following:
- Reports error if SNOR flash is not found on the board
- Changes smi_read_sr to return error using which a retry mechanism is
implemented for reading flash status
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Curently the code makes wrong assumption that the Transfer finished flag shall
be set within the stipulated time. However, there may occur a scenario in which
the TFF flag is not set. Return error in that case.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SMI is the serial memory interface controller provided by ST.
Earlier, a driver exists in the u-boot source code for the SMI IP. However, it
was specific to spear platforms. This commit converts the same driver to a more
generic driver. As a result, the driver files are renamed to st_smi.c and
st_smi.h and moved into drivers/mtd folder for reusability by other platforms
using smi controller peripheral.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Flexible static memory controller is a peripheral provided by ST,
which controls the access to NAND chips along with many other
memory device chips eg NOR, SRAM.
This patch adds the driver support for FSMC controller interfacing
with NAND memory.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
* 'master' of git://git.denx.de/u-boot-nand-flash:
NAND: Remove ONFI detection message to from bootup log
driver/mtd:IFC: Fix possible memory leak
driver/mtd: IFC NAND: Add support of ONFI NAND flash
mtd, nand: move some printfs to debug output.
nand_util: correct YAFFS image write function
powerpc/85xx: fix NAND boot linker scripts for -fpic
nand: extend .raw accesses to work on multiple pages
Without this patch, boot shows this messages upon NAND detection:
NAND: ONFI flash detected
ONFI param page 0 valid
ONFI flash detected
ONFI param page 0 valid
128 MiB
With this patch, its back to the U-Boot "standard":
NAND: 128 MiB
Tested on x600 (SPEAr600).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Scott Wood <scott@tyr.buserror.net>
if priv->bank >= MAX_BANK, priv should be freed before returning ENODEV.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scott@tyr.buserror.net>
current U-Boot shows on startup (for example on the enbw_cmc
board) the following printfs from the nand subsystem:
Flash: 2 MiB
NAND: Bad block table found at page 65472, version 0x01
Bad block table found at page 65408, version 0x01
nand_read_bbt: Bad block at 0x000002980000
nand_read_bbt: Bad block at 0x000003240000
128 MiB
MMC: davinci: 0
remove them to debug output, so it shows with this patch:
Flash: 2 MiB
NAND: 128 MiB
MMC: davinci: 0
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scott@tyr.buserror.net>
In function nand_write_skip_bad(),for YAFFS filesystem part,
write_oob() will return 0 when success, so when rval equals 0,
it should continue to write the next page, and no break.
Signed-off-by: Wentao, Liu <wentao.liu@intel.com>
Acked-by: Lei Wen <leiwen@marvell.com>
Signed-off-by: Scott Wood <scott@tyr.buserror.net>
Fix gcc 4.6 build warnings:
onenand_base.c: In function 'onenand_probe':
onenand_base.c:2577:6: warning: variable 'maf_id' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
* 'master' of git://git.denx.de/u-boot-arm:
ARM926EJS: Fix cache.c to comply with checkpatch.pl
ARM926EJS: Make asm routines volatile in cache ops
MX35: mx35pdk: wrong board revision
ARM1136: MX35: Make asm routines volatile in cache ops
ARM: add u-boot.imx as target for i.MX SOCs
M28: Pull out CONFIG_APBH_DMA so it's always enabled
DMA: Split the APBH DMA init into block and channel init
imx: Return gpio_set_value in gpio_direction_output
imx: Use GPIO_TO_PORT macro in the gpio driver instead of (gpio >> 5)
imx: Add GPIO_TO_PORT macro in the mxc_gpio driver
imx: Remove unneeded/repititive definitions from imx headers
i.MX28: Allow coexistence of PIO and DMA mode for SD/MMC
MX31: mx31pdk: drop enable_caches from board file
i.MX28: Fix initial stack pointer position
mx35: mx35pdk: fix when cache functions are linked
mx35: flea3: fix when cache functions are linked
ARM: 926ejs: use debug() for misaligned addresses
ARM1136: add cache flush and invalidate operations
mx6qsabrelite: Fix the serial console port
mx6qsabrelite: Add boot switch setting information into the README
i.MX6: mx6qsabrelite: add cache commands if cache is enabled
i.MX6: implement enable_caches()
i.MX6: define CACHELINE_SIZE
MX53: DDR: Fix ZQHWCTRL field TZQ_CS
mx28evk: Add a README file
mx28: Split the README into a common part and a m28 specific part
tricorder: Load kernel from ubifs
tricorder: Add UBIFS
cm-t35: fix Ethernet reset timing
hawkboard: Add CONFIG_SPL_LIBGENERIC_SUPPORT
BeagleBoard: Remove userbutton command and use gpio command instead
OMAP: Move omap1510inn to Unmaintained / Orphaned
This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.
The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.
The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.
NOTE: This patch depends on:
http://patchwork.ozlabs.org/patch/150957/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Fix:
spr_smi.c: In function 'smi_write':
spr_smi.c:325:15: warning: variable 'WM' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Vipin Kumar <vipin.kumar@st.com>
This replacement causes 4KB page size devices to work properly with u-boot.
The old ONENAND_IS_MLC() behavior has been preserved by explicit
setting of ONENAND_HAS_4KB_PAGE for those devices.
This change makes the onenand_base.c file more resembling the respective
kernel sources.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
Test HW:
- Samsung S5PC110 GONI
- Samsung S5PC210 Universal
Separate callback for probing OneNAND memory chip.
If no special function is defined, default implementation will be used.
This approach gives more flexibility for OneNAND device probing.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
The following warnings are reported for boards using SOFT ECC.
omap_gpmc.c:33:30: warning: 'hw_nand_oob' defined but not used
omap_gpmc.c:78:13: warning: 'omap_hwecc_init' defined but not used
omap_gpmc.c:116:12: warning: 'omap_correct_data' defined but not used
omap_gpmc.c:182:12: warning: 'omap_calculate_ecc' defined but not used
omap_gpmc.c:208:13: warning: 'omap_enable_hwecc' defined but not used
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Without the fix, flash_write_cfibuffer will terminate the erased
status check once an all-0xFF word has been found instead of
continuing the erased status check utill the first non-0xFF word.
Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Freescale IFC NAND Machine calculates ECC on 512byte sector and same is used in
fsl_ifc_run_command() during ECC status verification. Also this sector is passed
to is_blank() for blank checking. It is wrong at first place because
is_blank()'s implementation checks for Page size and OOB area size.
is_blank() should be called per page for main and OOB area verification.
Variables name are redefined to avoid confusion between buffer and ecc sector.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
1) OOB area should be updated irrespective of NAND page size. Earlier it was
updated only for 512byte NAND page.
2) During OOB update fbcr should be equal to OOB size.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
commit 2a8e0fc8b3 ("nand: Merge changes
from Linux nand driver") accidentally reverted commit
13f0fd94e3 ("NAND: Scan bad blocks
lazily.").
Reinstate the change, as amended by commit
ff49ea8977 ("NAND: Mark the BBT as scanned
prior to calling scan_bbt.").
Signed-off-by: Scott Wood <scottwood@freescale.com>
This reverts commit 4fee6c2f29.
It breaks boards that currently rely on soft-ecc, as pointed out here:
http://patchwork.ozlabs.org/patch/140872/
The reverted patch should be resubmitted with documentation, and with the
CONFIG_MTD_ECC_SOFT selected from every board that needs it. We could
start by looking at what NAND driver the board selects, and whether
that driver ever asks for soft ECC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
* 'sf' of git://git.denx.de/u-boot-blackfin:
README: Add description of SPI Flash (SF) command configuration
sf command: allow default bus and chip selects
sf: eeprom_m95xxx: set a sane default timeout
sf: eeprom_m95xxx: fix up style
Every board currently defines this to the same value, so just default
to that to avoid having to make everyone do the same thing.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current implementation of cfi_flash uses udelay to reset watchdog.
If several blocks are blank (0xff filled) the watchdog timed out.
The reason is, udelay is never called, if flash device is ready to fast.
e.g.
mw.w $(copy_addr) FFFF 10000;cp.b $(copy_addr) 10880000 20000
-> watchdog timed out
mw.w $(copy_addr) 0000 10000;cp.b $(copy_addr) 10880000 20000
-> watchdog not timed out
This patch adds an extra watchdog reset in front of flash ready check.
Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This driver doesn't yet make use of the added flexibility (not that that
should stop anyone from converting...), but it will with the in-progress
hack to support 4k-page NAND.
Signed-off-by: Scott Wood <scottwood@freescale.com>
This allows a driver to run code between nand_scan_ident() and
nand_scan_tail(), among other things. See the additions to
doc/README.nand for details.
To allow a gradual transition, Boards that don't set
CONFIG_SYS_NAND_SELF_INIT will still be initialized the old way, but
new drivers should not require this, and existing drivers should be
converted when convenient.
Signed-off-by: Scott Wood <scottwood@freescale.com>
- fix NAND_CMD_READID command for ONFI detect.
- add NAND_CMD_PARAM command to read the ONFI parameter page.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The software ECC algorithm is not necessary when hardware ECC
is available and can be left out for a smaller image size.
Enable with CONFIG_MTD_ECC_SOFT.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
[backport from linux commit 02f8c6aee8df3cdc935e9bdd4f2d020306035dbe]
This is part of the synchronization with the nand driver to the
Linux 3.0 state.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
[backport from linux commit 02f8c6aee8df3cdc935e9bdd4f2d020306035dbe]
This patch synchronizes the nand driver with the Linux 3.0 state.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
[backport from linux commit 02f8c6aee8df3cdc935e9bdd4f2d020306035dbe]
This patch synchronizes the nand driver with the Linux 3.0 state.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: minor fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Bring up to date with corresponding file from linux.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
[backport from linux commit 02f8c6aee8df3cdc935e9bdd4f2d020306035dbe]
This patch merges the additional NAND flash types from the 3.0 Linux
kernel.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
[backport from linux commit 02f8c6aee8df3cdc935e9bdd4f2d020306035dbe]
This patch merges the BCH ECC algorithm from the 3.0 Linux kernel.
This enables U-Boot to support modern NAND flash chips that
require more than 1-bit of ECC in software.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing
the fixed address in RAM.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Ilya Yanok <yanok@emcraft.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Simon Schwarz <simonschwarzcor@googlemail.com>
CC: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Fix:
nand_spl_load.c: In function 'nand_boot':
nand_spl_load.c:31:6: warning: variable 'ret' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fix warnings for both cases:
definded CONFIG_SYS_NAND_HW_ECC_OOBFIRST:
nand_spl_simple.c: In function 'nand_read_page':
nand_spl_simple.c:156:6: warning: variable 'stat' set but not used
[-Wunused-but-set-variable]
not definded CONFIG_SYS_NAND_HW_ECC_OOBFIRST:
nand_spl_simple.c: In function 'nand_read_page':
nand_spl_simple.c:196:6: warning: variable 'stat' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use software ECC for the SPL build if support for software ECC in SPL is
enabled.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Scott Wood <scottwood@freescale.com>
This patch adds support for software ECC to the nand_spl_simple driver.
To enable this one have to define CONFIG_SPL_NAND_SOFTECC.
Tested on OMAP3.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Scott Wood <scottwood@freescale.com>
s3c64xx.c implemented its own nand_read_byte, nand_write_buf and
nand_read_buf functions. This provoked a regression when these functions
were made public by patch 55f429bb39614a16b1bacc9a8bea9ac01a60bfc8.
This deletes these duplicated functions from s3c64xx.c and adds the generic
implementations in nand_base.c to the spl Makefile. It also adds
-ffcuntion-sections and -gc-sections to the compilation flags of the SPL to
avoid errors originating from unused functions in nand_base.c.
Description of the regression:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/108873
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Cc: scottwood@freescale.com
Cc: s-paulraj@ti.com
Cc: albert.u.boot@aribaud.net
Functions often used in SPL are now part of linux/mtd/nand.h.
Static modifiers are removed from these functions in
drivers/mtd/nand/nand_base.c.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Cc: scottwood@freescale.com
Cc: s-paulraj@ti.com
Cc: albert.u.boot@aribaud.net
Acked-by: Scott Wood <scottwood@freescale.com>
We want to show the length, so multiplying by sector size makes no sense.
This is a hold over from the erase code before the big refactor.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Change my old email address which is no longer valid.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
samsung.c: In function 's3c_onenand_check_lock_status':
samsung.c:486:6: warning: variable 'tmp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
dataflash.c: In function 'AT91F_DataflashInit':
dataflash.c:42:6: warning: variable 'last_part' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
onenand_base.c: In function ‘onenand_do_lock_cmd’:
onenand_base.c:1946:6: warning: variable ‘wp_status_mask’ set but not used
[-Wunused-but-set-variable]
onenand_base.c: In function ‘onenand_check_maf’:
onenand_base.c:2229:8: warning: variable ‘name’ set but not used
[-Wunused-but-set-variable]
onenand_base.c: In function ‘flexonenand_get_boundary’:
onenand_base.c:2258:6: warning: variable ‘ret’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
This introduces small OneNAND loader, fitting into 1kB of space (smallest
possible OneNAND RAM size). Some devices equipped with such crappy chips will
use this.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
V2: Introduce spl_onenand_load_image() to load data from OneNAND in SPL
V3: Cleanup, align with nand_spl. Skip whole blocks.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
similiar to commit dc7cd8e59b, only
adapted for the new spl framework.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The debugX() macro was always used with debug level 1. There is no point to use
it here instead of debug().
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
jedec_flash.c: In function 'fill_info':
jedec_flash.c:393: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'ulong'
jedec_flash.c:393: warning: format '%x' expects type 'unsigned int', but
argument 3 has type 'ulong'
jedec_flash.c:402: warning: format '%d' expects type 'int', but argument 2 has
type 'ulong'
jedec_flash.c:402: warning: format '%d' expects type 'int', but argument 3 has
type 'ulong'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
cfi_flash.c: In function 'flash_protect_default':
cfi_flash.c:2152: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'ulong'
cfi_flash.c:2152: warning: format '%08x' expects type 'unsigned int', but
argument 3 has type 'long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
Jz4740 NAND flash controller can support:
* MLC NAND as well as SLC NAND
* all 8-bit/16-bit NAND flash devices
* HAMMING and RS hardware ECC
* automatic boot up from NAND flash devices
nand_ecclayout is set up for 2GiB NAND chip mounted in Qi LB60.
We'll bring up boot-from-NAND support in nand_spl/ in the future.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
This fixes that u-boot gets stuck when a bitflip was detected
during "ubi part <ubi_device>". If a bitflip was detected UBI tries
to copy the PEB to a different place. This needs that the eba table
are initialized, but this was done after the wear levelling worker
detects the bitflip. So changes the initialisation of these two
tasks in u-boot.
This is a u-boot specific patch and not needed in the linux layer,
because due to commit 1b1f9a9d00
UBI: Ensure that "background thread" operations are really executed
we schedule these tasks in place and not as in linux after the inital
task which schedule this new task is finished.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fix:
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:226:19: warning: variable 'mtd_list' set but not used [-Wunused-but-set-variable]
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:225:6: warning: unused variable 'devices_found'
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:226:19: warning: variable 'mtd_list' set but not used [-Wunused-but-set-variable]
[-Wunused-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
* 'master' of git://git.denx.de/u-boot-nand-flash:
PPC: Fix socrates NAND problem
PPC: Fix fsl_upm.c by renaming nand handling functions
NAND: Make page, erase, oob size available via cmd_nand
mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poi
NAND: Add -y option to nand scrub command
NAND: Add nand read.raw and write.raw commands
NAND: Really ignore bad blocks when scrubbing
spl, nand: add 4bit HW ecc oob first nand_read_page function
mxc_nand: fix a problem writing more than 32MB
mxc_nand: fixed some typos (cosmetic)
nand: increase chip_delay in mv kirkwood nand driver
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p3060: Add SoC related support for P3060 platform
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
powerpc/85xx: Refactor some defines out of corenet_ds.h
fm-eth: Add ability for board code to disable a port
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
powerpc/mpc85xxcds: Fix PCI speed
powerpc/mpc8548cds: Fix booting message
powerpc/p4080: Add support for secure boot flow
powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
powerpc/p2041rdb: remove watch dog related codes
powerpc/p2041rdb: updated description of cpld command
powerpc/p2041rdb: add more ddr frequencies support
powerpc/p2041rdb: set sysclk according to status of physical switch SW1
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
powerpc/mpc8xxx: Add DDR2 to unified DDR driver
powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
powerpc/85xx: Enable CMD_REGINFO on corenet boards
powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
powerpc/85xx: Fix USB protocol definitions for P1020RDB
powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
powerpc/mpc8xxx: Move DDR RCW overriding to common code
powerpc/mpc8xxx: Extend CWL table
powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
powerpc/85xx: Cleanup extern in corenet_ds board code
powerpc/p2041rdb: Add ethernet support on P2041RDB board
powerpc/85xx: Add networking support to P1023RDS
powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
powerpc/85xx: Add FMan ethernet support to P4080DS
powerpc/85xx: Add support for FMan ethernet in Independent mode
powerpc/mpc8548cds: Cleanup mpc8548cds.c
powerpc/mp: add support for discontiguous cores
powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
fdt: Add new fdt_create_phandle helper
fdt: Rename fdt_create_phandle to fdt_set_phandle
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
nand: Freescale Integrated Flash Controller NAND support
powerpc/85xx: Add basic support for P1010RDB
powerpc/85xx: Add support for new P102x/P2020 RDB style boards
powerpc/85xx: relocate CCSR before creating the initial RAM area
powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
This avoids colision with nand subsystem's functions.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The eLBC NAND driver currently follows up each program/write operation with a
read-back of the page, in order to [ostensibly] fill in ECC data for the
caller. However, the page address used for this read is always -1, so the read
will never work correctly. Remove this useless (and potentially problematic)
block of code.
v2: fix broken mailer
Signed-off-by: mhench <mhench@elutions.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: use chip instead of redundant priv_nand]
Signed-off-by: Scott Wood <scottwood@freescale.com>
When writing 0x4000 to the unlockend_blkaddr register, large writes to
a 2k page NAND sometimes fail. The current kernel driver writes 0xFFFF
to this register for V2 of the nand controller.
However on an i.MX31 this also fixes writes larger than 32MB.
The datasheet is very unspecific, but (0x4000=16384)*2000
roughly fits the limits we're encountering with NAND writes.
This problem might be NAND chip specific.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay.
The Data Transfer from Cell to Register is >= 35us. Other Vendors
and older chips normally use >= 25us. To have enough margin 40us
is selected.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
vmt.c: In function ‘ubi_free_volume’:
vmt.c:681:6: warning: variable ‘err’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
nand_bbt.c: In function ‘search_bbt’:
nand_bbt.c:465:6: warning: variable ‘bits’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Add NAND support (including spl) on IFC, such as is found on the p1010.
Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should
work, as it does not use OOB for anything but ECC.
When hardware ECC is not enabled in CSOR, software ECC is now used.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
On some systems, we get a warning when %lu is used with size_t's, so
use the correct format string.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Add support of MX25L4005 and MX25L8005 according to the datasheet
http://www.mct.net/download/macronix/mx25l8005.pdf
This patch has been tested with MX25L4005 and MX25L8005
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Newer SST flashes have dropped the Auto Address Increment (AAI) word
programming (WP) modes in favor of the standard page programming mode
that most flashes now support. So add a flags field to the different
flashes to support both modes with new and old styles.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Every spi flash uses the same write disable command, so unify this in
the common code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Fixed commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Now that the common spi_flash structure tracks all the info that these
drivers need, kill off their local state indirection and use just what
the common code provides.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Once we add a new page_size field for write lengths, we can unify the
write methods for most of the spi flash drivers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds support for 16 bit NAND devices attached to the
NDFC on ppc4xx processors. Two config entries were added:
CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a
16 bit device is attached.
CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus
Controller configuration register.
Also, a new ndfc_read_byte() function was added which does not
first convert the data to little endian.
The NAND SPL was also modified to do 16bit bad block testing
when a 16 bit chip is being used.
Signed-off-by: Alex Waterman <awaterman@dawning.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add a flag to nand_read_skip_bad() such that if true, any trailing
pages in an eraseblock whose contents are entirely 0xff will be
dropped.
The implementation is via a new drop_ffs() function which is
based on the function of the same name from the ubiformat
utility by Artem Bityutskiy.
This is as-per the reccomendations of the UBI FAQ [1]
[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Artem Bityutskiy <dedekind1@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an
operation which is mutually exclusive with the 'usual' way of writing.
Add a check that client code does not specify WITH_YAFFS_OOB along with any
other flags and add a comment indicating that the WITH_YAFFS_OOB flag should
not be mixed with other flags.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
In a future commit the behaviour of nand_write_skip_bad()
will be further extended.
Convert the only flag currently passed to the nand_write_
skip_bad() function to a bitfield of only one allocated
member. This should avoid an explosion of int's at the
end of the parameter list or the ambiguous calls like
nand_write_skip_bad(info, offset, len, buf, 0, 1, 1);
nand_write_skip_bad(info, offset, len, buf, 0, 1, 0);
Instead there will be:
nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB |
WITH_OTHER);
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Replace an incorrect 'read' with 'write' in a comment.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For newer STM parts where CFI >= 1.1, there is a byte in the extended
structure that declares the flash layout type (just like the AMD parts),
so key off of that to find out when we need to reverse the geometry.
This can be seen with M29W640 parts where U-Boot does:
Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED
Erase timeout: 8192 ms, write timeout: 1 ms
Buffer write timeout: 1 ms, buffer size: 16 bytes
Sector Start Addresses:
20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO
2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO
...
But Linux does:
physmap platform flash device: 00800000 at 20000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank.
Manufacturer ID 0x000020 Chip ID 0x0022ed
physmap-flash.0: Swapping erase regions for top-boot CFI table.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The status polling can take a while, so make sure we kick the
watchdog after each successful poll.
Signed-off-by: Patrick Sestier <psestier@mircom.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.
This change will let other SoC which also use ftsmc020
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
I ran into a problem where the reset was failing except when I enabled
debugging support. After talking with Garret Swalling at Spansion I
was told that the GL-N series of devices require a 500ns wait for the
reset to complete. The below patch adds a 1us delay after all reset
commands.
-Aaron Williams
Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The M29W800DT parts also report their geometry with the sector layout
reversed. So add that ID to the flash_fixup_stm function.
Otherwise, we get:
bfin> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 1 MB in 19 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22D7
Erase timeout: 8192 ms, write timeout: 1 ms
Sector Start Addresses:
20000000 20004000 20006000 20008000 20010000
20020000 20030000 20040000 20050000 20060000
20070000 20080000 20090000 200A0000 200B0000
200C0000 200D0000 200E0000 200F0000
Reported-by: Jianxi Fu <fujianxi@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch sync with Brian's patch on Linux in nand_flash_detect_onfi()
commit b7b1a29d94c17e4341856381bccb4d17495bea60
Author: Brian Norris <computersforpeace@gmail.com>
Date: Sun Dec 12 00:23:33 2010 -0800
mtd: nand: rearrange ONFI revision checking, add ONFI 2.3
In checking for the ONFI revision, the first conditional (for checking
"unsupported" ONFI) seems unnecessary. All ONFI revisions should be
backwards-compatible; even if this is not the case on some newer ONFI
revision, it should simply fail the second version-checking if-else block
(i.e., the bit-fields for 1.0, 2.0, etc. would not be set to 1). Thus, we
move our "unsupported" condition after having checked each bit field.
Also, it's simple enough to add a condition for ONFI revision 2.3. Note
that this does *NOT* mean we handle all new features of ONFI versions
above 1.0.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
This patch sync with David's patch on Linux in nand_flash_detect_onfi()
commit 4ccb3b4497ce01fab4933704fe21581e30fda1a5
Author: David Woodhouse <David.Woodhouse@intel.com>
Date: Fri Dec 3 16:36:34 2010 +0000
mtd: nand: Fix integer overflow in ONFI detection of chips >= 4GiB
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Commit 6ee1416e81 (mtd, cfi: introduce
void flash_protect_default(void)) introduced a bug which resulted in
boards that define CONFIG_SYS_FLASH_AUTOPROTECT_LIST not compiling with
the the following errors and warning:
ptyser@petert u-boot $ make -s xpedite520x
Configuring for xpedite520x board...
cfi_flash.c: In function 'flash_protect_default':
cfi_flash.c:2118: error: 'i' undeclared (first use in this function)
cfi_flash.c:2118: error: (Each undeclared identifier is reported only once
cfi_flash.c:2118: error: for each function it appears in.)
cfi_flash.c:2118: error: 'apl' undeclared (first use in this function)
cfi_flash.c:2118: error: invalid application of 'sizeof' to incomplete type 'struct apl_s'
cfi_flash.c: In function 'flash_init':
cfi_flash.c:2137: warning: unused variable 'apl'
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Reported-by: Kumar Gala <galak@kernel.crashing.org>
Cc: Heiko Schocher <hs@denx.de>
This patch adds a new member to struct spi_flash (u16 sector_size)
and updates the spi flash drivers to start populating it.
This parameter can be used by spi flash commands that need to round
up units of operation to the flash's sector_size.
Having this number in one place also allows duplicated code to be
further collapsed into one common location (such as erase parameter
and the detected message).
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The AT45 flashes are completely different (at the command set and
status register level) from all other SPI flashes, so we can't unify
their logic with common code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
All of the spi flash drivers implement the status register polling for
detecting the device ready state, so unify them all in a new helper
function -- spi_flash_wait_ready.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
collect code which protects default sectors in a function, called
flash_protect_default. So boardspecific code can call it too.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
If NCE is hooked up to NCS3, we don't need to (and can't)
explicitly set the state of the NCE pin. Instead, the
controller asserts it automatically as part of a
command/data access. Only "CE don't care"-type NAND chips
can be used in this manner.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
This patch adds support for reading an ONFI page parameter from a NAND
device supporting it. If this is the case, struct nand_chip onfi_version
member contains the supported ONFI version, 0 otherwise.
This allows NAND drivers past nand_scan_ident to set the best timings for the
NAND chip.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The function find_sector() does not take into account if the flash bank
has changed since the last call. This could lead to illegal accesses inside
and beyond the flash_info_t info strcture. For example if the current
flash bank has less sectors than the last used flash bank.
This patch adds two cheks. One that insures, that the current sector does
not exceed the allowed maximum (which is always a good idea). And one that
checks if the current access is to the same flash bank as the last access.
If not, the search loop will start with sector 0.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Stefan Roese <sr@denx.de>
There's no compelling reason to have the output on bootup or the
"flinfo" command print "flash" in uppercase, so use the proper case
where appropriate.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This patch sync with David's patch on Linux for handling nand_scan_ident.
commit 5e81e88a4c140586d9212999cea683bcd66a15c6
Author: David Woodhouse <David.Woodhouse@intel.com>
Date: Fri Feb 26 18:32:56 2010 +0000
mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
This patch add addition suffix to nand write to give the uboot
the power to directly burn the yaffs image to nand.
Signed-off-by: Lei Wen <leiwen@marvell.com>
The flash_verbose logic is only used by the CFI MTD layer, so if we aren't
using that, disable the logic completely.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This is part of the timer cleanup effort.
In the future we only use get_timer() in its intended way to
program timeout loops.
reset_timer() shall not be used anymore.
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
While we're here, cut out the useless id defines too.
Signed-off-by: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds the possibility to (optinally) write to the
flash configuration register. The Intel style CFI chips support
such a register that can be used to configure the operation
mode to a non-default value.
This method will be used by the t3corp board, which needs to
configure the DS617 Xilinx flash for async read mode.
Signed-off-by: Stefan Roese <sr@denx.de>
The function sector_erased() is modified to not use pointer
access, but to use the correct accessor functions. This fixes a
problem on the t3corp board with the Xilinx DS617 flash chips. Here
a board specific accessor function is needed to read from flash
in 32bit mode. This patch enables such an operation mode.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds some calls to set the flash chip in the read-status-
register- or read-id-mode before the corresponding register is
read back. This problem was detected while porting the common CFI
driver to support the Xilinx DS617 flash chips.
Signed-off-by: Stefan Roese <sr@denx.de>
According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):
"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."
The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The attached patch fixes wrong timing default values and adds the
possibility to specify board specific timing value in the board config file.
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
commit ec50a8e389
"cfi_flash: handle 'chip size exceeds address window' situation"
added 3rd argument to flash_get_size() but didn't fix all the
function calls from the board specific code. Many boards have
their own flash_get_size() definitions in the board code and
use them there, but some boards (e.g. tqm834x, tqm85xx, pdm360ng)
use flash_get_size() from the cfi_flash.c driver.
The bug shows up if the value of the "max_size" argument (which
is not defined when calling the function with two arguments)
happens to be less than "info->size". In this case on the
affected boards we end up with a bank of reduced size and
in the worst case might even be not able to update U-Boot or
to boot the kernel from flash:
=> fli
Bank # 1: CFI conformant FLASH (32 x 16) Size: 0 kB in 1 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 3 ms, buffer size: 64 bytes
Sector Start Addresses:
F0000000 RO
Bank # 2: CFI conformant FLASH (32 x 16) Size: 128 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 3 ms, buffer size: 64 bytes
Sector Start Addresses:
F8000000 F8040000 F8080000 F80C0000 F8100000
F8140000 F8180000 F81C0000 F8200000 F8240000
...
E.g., updating U-Boot is not possible now:
=> protect off ${u-boot_addr} +${u-boot_size}
Error: end address (0xf007ffff) not in flash!
Bad address format
=> era ${u-boot_addr} +${u-boot_size}
Error: end address (0xf007ffff) not in flash!
Bad address format
This patch removes the 3rd argument of flash_get_size() again
and sets "max_size" in the function itself instead of passing
it as a function argument.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This is needed for the canyonlands_nand build target. Without it
the resulting image won't fit into 4k.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
Supports most types that support Read-Id and the FM25H20.
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
By now, the majority of architectures have working relocation
support, so the few remaining architectures have become exceptions.
To make this more obvious, we make working relocation now the default
case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This patch adds generic support for the Samsung s3c2440 processor.
Global s3c24x0 changes to struct members converting from upper case to
lower case.
Signed-off-by: Craig Nauman <cnauman@diagraph.com>
Cc: kevin.morfitt@fearnside-systems.co.uk
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On some boards we have flash mapped high in the address space with
considerably small window (say 0xFE000000 and 32MB). When we install
bigger chip (say 64MB) on such a board strange things happen
(flash_write() doesn't work at all, for ex). That's because cfi_flash
driver doesn't care about window size at all.
Of course, cleanest solution would probably be to just extend address
window to be able to map the whole flash but for legacy/compatibility
reasons some people prefer just truncate the flash size and never use
the upper part.
This patch adds an option for cfi_flash driver to handle this situation
properly. To achieve this we add the new function cfi_flash_bank_size()
which can be provided by the board code and weak-aliased to default
implementation that returns value from the CONFIG_SYS_FLASH_BANKS_SIZES
array if it's defined or 0 otherwise (the last case is added for
compatibility).
If non-zero flash bank size is provided and detected chip size is bigger
than provided address window size the warning will be displayed and
flash chip will be truncated.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Changed cfi_flash_bank_size() return type to unsigned long
to match caller function.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The ECC calculations were started by writing 1 << 13 to the nand FCR register;
that value is also defined as DAVINCI_NANDFCR_4BIT_CALC_START in emif_defs.h.
This patch substitutes the macro DAVINCI_NANDFCR_4BIT_CALC_START for the
magic number '1 << 13'.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This allows for arbitrarily long manufacturer ids following the JEDEC
standard of 0x7f continuation bytes. It also makes adding new entries
easier as it's just one element in an array. The downside is that it
increases code size a bit, but we're talking ~50 bytes.
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When a CFI flash chip could not be detected an error message similar to
the following would be printed on bootup:
FLASH: ## Unknown FLASH on Bank 1 - Size = 0x01000000 = 0 MB
The printf incorrectly converted the flash size into megabytes. This
patch fixes the printing of the flash size in megabytes:
FLASH: ## Unknown FLASH on Bank 1 - Size = 0x01000000 = 16 MB
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the Numonyx manufacturer code (0x20) to
onenand manufacturers.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Consolidate some code in mtd_get_len_incl_bad(), and fix a condition
where a valid partition could be reported as truncated if it has a
good block at the end of the device (unlikely, since the BBT is usually
there).
Fix mid-block declarations in net_part_size().
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Ben Gardiner <bengardiner@nanometrics.ca>
The logic to 'spread' mtd partitions needs to calculate the length in
the mtd device, including bad blocks.
This patch introduces a new function, mtd_get_len_incl_bad that can
return both the length including bad blocks and whether that length
was truncated on the device. This new function will be used by the
mtdparts spread command later in this series. The definition of the
function is #ifdef'd out in configurations that do not use the new
'mtdparts spread' command.
Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca>
CC: Scott Wood <scottwood@freescale.com>
Get rid of the several "#if 0" sections that were keeping around Linux
code that isn't relevant to U-Boot. Besides cluttering the code, these
sections make tracking upstream changes harder, rather than easier.
It's easy to discard obviously irrelevant diff hunks that patch rejects,
but it's not as easy to notice hunks that apply cleanly to the #if 0
section, but *are* relevant to U-Boot and require modification elsewhere.
Also remove suspend/resume, as this is not applicable to U-Boot. Removal
saves 232 bytes on powerpc.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
A while back, in http://lists.denx.de/pipermail/u-boot/2009-June/054428.html,
Michele De Candia posted a patch to not count bad blocks toward the
requested size to be erased. This is desireable when you're passing in
something like $filesize, but not when you're trying to erase a partition.
Thus, a .spread subcommand (named for consistency with
http://lists.denx.de/pipermail/u-boot/2010-August/075163.html) is introduced
to make explicit the user's desire to erase for a given amount of data,
rather than to erase a specific region of the chip.
While passing $filesize to "nand erase" is useful, accidentally passing
something like $fliesize currently produces quite unpleasant results, as the
variable evaluates to nothing and U-Boot assumes that you want to erase
the entire rest of the chip/partition. To improve the safety of the
erase command, require the user to make explicit their intentions by
using a .part or .chip subcommand. This is an incompatible user interface
change, but keeping compatibility would eliminate the safety gain, and IMHO
it's worth it.
While touching nand_erase_opts(), make it accept 64-bit offsets and sizes,
fix the percentage display when erase length is rounded up, eliminate
an inconsistent warning about rounding up the erase length which only
happened when the length was less than one block (rounding up for $filesize
is normal operation), and add a diagnostic if there's an attempt to erase
beginning at a non-block boundary.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
The underlying code in nand_base.c already supports non-page-aligned reads
and writes, but the block-skipping wrapper code did not.
With block skipping, an unaligned start address is not useful since you
really want to be starting at the beginning of a partition -- or at least
that's where you want to start checking for blocks to skip, but we don't
(yet) support that. So we still require the start address to be aligned.
An unaligned length, though, is useful for passing $filesize to the
read/write command, and handling it does not complicate block skipping.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
This patch introduces an extra mask-field in spansion_spi_flash_params
to support flash chips with 1-byte extended ID (like the S25FL032P).
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The spansion_erase currently only works when the sector size is 64KB.
cmd[1] should contain the higher 8 bit of the 24 bit address of the
sector to be erased. Currently it is holding the sector index to be
erased which happens to be the same thing when the sector size is
64KB.
Signed-off-by: Marc-Andre Hebert <marc-andre.hebert@humanware.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Adds support for Winbond's W25Q64 SPI flash. These devices are used on
(among others) Xilinx' SP601 and SP605 Spartan-6 evaluation boards.
Tested with "sf" commands.
Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Commit 2ee951ba (UBI: Enable re-initializing of the "ubi part" command)
reset mtd_devs in ubi_exit() but missed ubi_init()'s failure path.
Signed-off-by: Karl Beldan <karl.beldan@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some ppc4xx related headers from the common include
directory (include/) to the powerpc specific one
(arch/powerpc/include/asm/). This way to common include directory is not
so cluttered with files.
Signed-off-by: Stefan Roese <sr@denx.de>
Now that the defines are moved to header files we don't need this
conditional compilation any more. Remove it.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch simplifies the use of CONFIG_SYS_MAX_FLASH_BANKS_DETECT. By
moving these optional variables and defines into the common code, board
specific code is minimized. Currently only the following board use
this feature:
APC405, IDS8247, TQM834x
And IDS8247 doesn't seem to really need this feature, since its not
updating the bank number variable at all. So this patch removes the
definition of CONFIG_SYS_MAX_FLASH_BANKS_DETECT from this board port.
This new framework will be used by the upcoming lwmon5 update as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
cfi_flash_bank_addr(int bank_nr) returns the base addresses of the
requested bank. Introducing this weak default enables boards to override
this functions with a board specific version when required.
This feature will be used in the lwmon5 board update, supporting runtime
detection of 2 board revisions with different flash layouts.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes an unecessary check in the return statement. This is
not needed, since "info" is initializes to NULL. And "info" will not be
written to again, if the flash address is not found.
Additionally "info" is not initialized to "0" but to "NULL".
Signed-off-by: Stefan Roese <sr@denx.de>
Due to a register glitch (result code <4 might show up right after the
start-calculation-bit was set), make sure the ECC has really started.
See 1c3275b656045aff9a75bb2c9f3251af1043ebb3 in the kernel.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
This printk was added recently and results in ugly output on systems
with no NAND:
NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB
instead of:
NAND: 0 MiB
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30
256-Mbit 65nm flash chips.
After some time :( searching for bugs in our board or soft, we have
discovered that those chips have a small but annoying bug, documented in
"Numonyx Axcell P33/P30 256-Mbit Specification Update"
It states :
When customer uses [...] block unlock, the block lock status might be
altered inadvertently. Lock status might be set to either 01h or 03h
unexpectedly (00h as expected data), which leads to program/erase failure
on certain blocks.
A working workaround is given, which I have applied and tested with success :
Workaround: If the interval between 60h and its subsequent command
can be guaranteed within 20us, Option I is recommended,
otherwise Option II (involves hardware) should be selected.
Option I: The table below lists the detail command sequences:
Command
Data bus Address bus Remarks
Sequence
1 90h Block Address
Read Lock Status
2 Read Block Address + 02h
(2)(3) (1)
3 60h Block Address
(2)(3) (1) Lock/Unlock/RCR Configuration
4 D0h/01h/03h Block Address
Notes:
(1) Block Address refers to RCR configuration data only when the 60h
command sequence is used to set RCR register combined with 03h
subsequent command.
(2) For the third and fourth command sequences, the Block Address must
be the same.
(3) The interval between 60h command and its subsequent D0h/01h/2Fh/03h
commands should be less than 20us.
And here is a log comparison of a simple (destructive) flash test without
and with the workaround.
diff without-numonyx-workaround.log with-numonyx-workaround.log
-U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:07:47)
+U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:25:19)
CPU: Freescale MCF5484
CPU CLK 200 MHz BUS CLK 100 MHz
Board: Macq Electronique ME2060
I2C: ready
DRAM: 64 MiB
FLASH: 32 MiB
In: serial
Out: serial
Err: serial
Net: FEC0, FEC1
-> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 32 MB in 259 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8922
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 5 ms, buffer size: 1024 bytes
Sector Start Addresses:
FE000000 RO FE008000 RO FE010000 RO FE018000 RO FE020000 RO
FE040000 RO FE060000 RO FE080000 RO FE0A0000 RO FE0C0000 RO
...
FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO
-> protect off all
Un-Protect Flash Bank # 1
................... done
-> erase all
Erase Flash Bank # 1
................... done
-> cp.b 1000000 fe000000 2000000
-Copy to Flash... Flash not Erased
+Copy to Flash... done
->
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch does the following:
- Extract code to detect if sector is erased into function
sector_erased().
- Because of this, we don't have variable declarations inside the
sector loop in flash_print_info()
- Change "return" to "break" in the "if (ctrlc()) statement:
This fixes a problem with the resulting output. Before this
patch the output was:
Sector Start Addresses:
FC000000 FC020000 FC040000 =>
With this patch it is now:
Sector Start Addresses:
FC000000 FC020000 FC040000
=>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Fix reading and printing of CFI flashes 16-bit devices identifiers
Nowadays CFI flashes have a 16-bit device identifier. U-boot still
print them and read them as if they were only 8-bit wide. Fix that.
Before:
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1B
After:
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x881B
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Stefan Roese <sr@denx.de>
While running from flash, i. e. before relocation, we have only a
limited C runtime environment without writable data segment. In this
phase, some configurations (for example with environment in EEPROM)
must not use the normal getenv(), but a special function. This
function had been called getenv_r(), with the idea that the "_r"
suffix would mean the same as in the _r_eentrant versions of some of
the C library functions (for example getdate vs. getdate_r, getgrent
vs. getgrent_r, etc.).
Unfortunately this was a misleading name, as in U-Boot the "_r"
generally means "running from RAM", i. e. _after_ relocation.
To avoid confusion, rename into getenv_f() [as "running from flash"]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rather than bang MMRs directly, use the new portmux framework to handle
the details.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Scott Wood <scottwood@freescale.com>
Make it easy to use GPIOs for the DEV_READY pin by using the common GPIO
framework. Also make the NAND_PLAT_INIT() define optional.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Thomas Chou <thomas@wytron.com.tw>
The Toshiba TC58NVG0* parts are 128Mbytes x 8 bits 3.3V parts with the 0xD1
identifier. Add these to the list of known devices IDs.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
When the NAND part is not supported, it is useful to show the manufacturer
and device ID to help debugging and reporting.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
At the moment, the default SPI flash subsystem is quite terse. Errors and
successes both result in a generic message. So move the useful errors and
useful successes to printf output by default.
While we're here, also convert the messages to use print_size().
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some old STMicro parts do not support JEDEC ID (0x9f). This patch
uses RES (0xab) to get Electronic ID and translates it to JEDEC ID.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Mike Frysinger <vapier@gentoo.org>
UBI: initialise update marker
The in kernel copy of a volume's update marker is not initialised from the
volume table. This means that volumes where an update was unfinnished will
not be treated as "forbidden to use". This is basically that the update
functionality was broken.
Signed-off-by: Peter Horton <zero@colonel-panic.org>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Stefan Roese <sr@denx.de>
The current Blackfin nand write function fills up the write buffer but
returns before it has had a chance to drain. On faster systems, this
isn't a problem as the operation finishes before the ECC registers are
read, but on slower systems the ECC may be incomplete when the core tries
to read it.
So wait for the buffer to drain once we're done writing to it.
Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current U-Boot UBI implementation is copied from Linux. In this
porting the UBI background thread was not handled correctly. Upon write
operations ubi_wl_flush() makes sure, that all queued operations, like
page-erase, are completed. But this is missing for read operations.
This patch now makes sure that such operations (like scrubbing upon
bit-flip errors) are not queued, but executed directly.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds reset_timer() before the flash status check
waiting loop.
Since the timer is basically running asynchronous to the cfi
code, it is possible to call get_timer(0), then only a few
_SYSCLK_ cycles later an interrupt is generated. This causes
timeout even though much less time has elapsed. So the timer
period registers should be reset before get_timer(0) is
called.
There is similar usage in nand_base.c.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.
This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.
This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.
Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
This is a patch to use the hardware ECC controller of
the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33.
Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;'
Signed-off-by: Thomas Weber <swirl@gmx.li>
Add some more: neither Makefile nor config.mk need execute permissions.
Signed-off-by: Wolfgang Denk <wd@denx.de>
For platforms with flash below ram addresses, the current check to
activate monitor protection is wrong/insufficient. This patch fixes
CONFIG_MONITOR_IS_IN_RAM for these systems by adding a check for
this configuration.
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
Signed-off-by: Stefan Roese <sr@denx.de>
eraseregions numblocks was sometimes one less than actual, possibly producing
erase regions with zero blocks. As MTD code touches eraseregions only if
numeraseregions is greater that zero, allocate eraseregions only for non
uniform erase size flash.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for version 1.1 of the nfc nand flash
controller which is on the i.mx25 soc.
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Scott Wood <scottwood@freescale.com>
SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.
Signed-off-by: Vipin <vipin.kumar@st.com>
Import the large page oob layout from Linux mxc_nand.c driver.
The CONFIG_SYS_NAND_LARGEPAGE option is used to activate
the large page oob layout. Run time detection is not supported
as this moment.
This has been tested on the i.MX31 PDK board with a large
page NAND device.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Introduces various optimisations that approximately triple the
read data rate from NAND when run on da830evm.
Most of these optimisations depend on the endianess of the machine
and most of them are very similar to optimisations already present
in the Linux Kernel.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Davinci: NAND enable ECC even when not in NAND boot mode
On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Davinci: Configurable NAND chip selects
Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Currently, the last block of NAND devices can't be accessed. This patch
fixes this issue by correcting the boundary checking (off-by-one error).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
Depending on offset, flash size and the number of bad blocks,
get_len_incl_bad may return a too small value which may lead to:
1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the
bad block aware read/write code. This may hurt performance, but does
not have any adverse effects.
2) If there are bad blocks, the nand_{read,write}_skip_bad may choose
the bad block unaware read/write code (if len_incl_bad == *length)
which leads to corrupted data.
Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.
checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:
ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch
As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.
The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
I'll fix these errors in another patch.
Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for NAND devices with a page size of
4K in the DaVinci NAND driver. The layout matches the layout that TI uses
for 4K page size NAND devices in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch add nand_read_buf() for S3C2410 NAND SPL.
In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip,
so nand->select_chip should also be initialized.
Signed-off-by: Hui.Tang <zetalabs@gmail.com>
This patch updates a check condition in the NAND driver.
The check condition is similat to what is in linux/next.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for Flex-OneNAND devices.
Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com>
Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
The syndrome based page read/write routines store ECC, and possibly other
"OOB" data, right after each chunk of ECC'd data. With ECC chunk size of
512 bytes and a large page (2KiB) NAND, the layout is:
data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover
Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines
use a traditional layout -- data OOB, disregarding the prepad and postpad
values -- so when they're used with that type of ECC hardware, those calls
mix up the data and OOB. Which means, in particular, that bad block
tables won't be found on startup, with data corruption and related chaos
ensuing.
The current syndrome-based drivers in mainline all seem to use one chunk
per page; presumably they haven't noticed such bugs.
Fix this, by adding read/write page_raw_syndrome() routines as siblings of
the existing non-raw routines; "raw" just means to bypass the ECC
computations, not change data and OOB layout.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When computing oobavail from the list of free areas in the OOB,
don't assume there will always be an unused slot at the end.
This syncs up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch updates the check condition for determining
whether the ECC corrections has failed.
This makes it similar to what is in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This was originally part of Thomas Gleixner's patch for
adding support for 4KiB pages.
This is not part of the U-Boot NAND driver so updating the
driver with this to sync up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch updates the "chip_shift" calculation in the
NAND driver. This is being done to sync up the NAND driver with
the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
Some of the new spi flash files were missing explicit license lines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes
to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patches 1/4, 2/4 and 3/4 of this series
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch includes the onenand driver for s5pc100
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Add #ifdefs where necessary to not perform relocation fixups. This
allows boards/architectures which support relocation to trim a decent
chunk of code.
Note that this patch doesn't add #ifdefs to architecture-specific code
which does not support relocation.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to
support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND
chips. This ECC mode is similar to NAND_ECC_HW, with the exception of
read_page API that first reads the OOB area, reads the data in chunks,
feeds the ECC from OOB area to the ECC hw engine and perform any
correction on the data as per the ECC status reported by the engine.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds a new "page" parameter to all NAND read_page/read_page_raw
APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the
page information to send the READOOB command and read the OOB area before
the data area.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch
WE would like this to become part of the u-boot GIT as well
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove unused read_spareram and add unlock_all as kernel does
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
see http://www.jedec.org/download/search/jep106Z.pdf
Add some second source legacy flash chips 256x8.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix ECC Correction bug where the byte offset location were double
flipped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the s1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byteoffs = (s1 << 0) & 0x80;
.
.
byteoffs |= (s0 >> 4) & 0x08;
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix bug introduced by 9c048b5234.
The cfi_flash.c driver cast the flash buffer size to a uchar in
flash_write_cfibuffer(). On some flash parts, (tested on Numonyx
part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to
uchar to enable buffer sizes to be larger.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This chip is used in a number of boards manufactured by Calao-Systems
which should be supported soon. This driver provides the necessary
spi_read and spi_write functions necessary to communicate with the chip.
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Legacy NAND had been scheduled for removal. Any boards that use this
were already not building in the previous release due to an #error.
The disk on chip code in common/cmd_doc.c relies on legacy NAND,
and it has also been removed. There is newer disk on chip code
in drivers/mtd/nand; someone with access to hardware and sufficient
time and motivation can try to get that working, but for now disk
on chip is not supported.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Now that the 4xx NAND driver ndfc is moved to the common NAND driver
directory we don't need this #ifdef's anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
a.k.a cfi_mtd.c does as cfi_flash.c does. This also prevents
the TQM834x build from doing a:
cfi_mtd.c:36: error: variably modified 'cfi_mtd_info' at file scope
cfi_mtd.c:37: error: variably modified 'cfi_mtd_names' at file scope
using gcc 4.4.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For JEDEC flash, we should issue word programming command relative to
base address rather than sector base address. Original source makes
SST Flash fails to program sectors which are not on the 0x10000 boundaries.
e.g.
SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector
is 0x1000 bytes.
Thus, if we issue command to "sector base (0x41000) + offset(0x5555)",
it sends to 0x46555 and the chip fails to recognize that address.
This patch is tested with SST39LF040.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds a NAND driver for the Marvell Kirkwood SoC's
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The bbt descriptors contains the pointer to the bbt pattern which
are statically initialized memory struct. When relocated to RAM,
these pointers will continue point to NOR flash(or L2 SRAM, or
other boot device). If the contents of NOR flash changed or L2
SRAM disabled, it'll hang the system.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The S3C2410 NAND driver source file is included in the makefile instead of
the object file.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Scott Wood <scottwood@freescale.com>
nand_util currently uses size_t which is arch dependent and not always a
unsigned long. Now use loff_t, as does the linux mtd layer.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped. Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Update chipselect handling in davinci_nand.c so that it can
handle 2 GByte chips the same way Linux does: as one device,
even though it has two halves with independent chip selects.
For such chips the "nand info" command reports:
Device 0: 2x nand0, sector size 128 KiB
Switch to use the default chipselect function unless the board
really needs its own. The logic for the Sonata board moves out
of the driver into board-specific code. (Which doesn't affect
current build breakage if its NAND support is enabled...)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty;
it's also unused by any current boards, and doesn't even match the
main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
on newer chips that support it).
DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths
do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
and 5.0/2.6.18) do ... but only for small pages. Large page support
is really broken (and it's unclear just what software it was trying
to match!), and the ECC layout was making three more bytes available
for use by filesystem (or whatever) code.
Since this option itself seems broken, remove it. Add a comment
about the MV/TI compat issue, and the most straightforward way to
address it (should someone really need to solve it).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Minor cleanup for DaVinci NAND code:
- Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't
be defined when there are multiple chipselect lines in use
(as with common 2 GByte chips).
- Cleanup handling of EMIF control registers
* Only need one pointer pointing to them
* Remove incorrect and unused struct supersetting them
- Use the standard waitfunc; we don't need a custom version
- Partial legacy cleanup:
* Don't initialize every board like it's a DM6446 EVM
* #ifdef a bit more code for BROKEN_ECC
Sanity checked with small page NAND on dm355 and dm6446 EVMs;
and large page on dm355 EVM (packaged as two devices, not one).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch fixes a build problem noticed on Apollon by using
mtd_dev_by_eb() instead of "/" as done in the Linux UBI version.
So this brings the U-Boot UBI version more in sync with the Linux
version again.
Signed-off-by: Stefan Roese <sr@denx.de>
new chips supported:-
MX25L1605D, MX25L3205D, MX25L6405D, MX25L12855E
out of which MX25L6405D and MX25L12855E tested on Kirkwood platforms
Modified the Macronix flash support to use 2 bytes of device id instead of 1
This was required to support MX25L12855E
Signed-off-by: Piyush Shah <spiyush@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Looks like when I was encoding the sector sizes, I forgot to divide by 8
(due to the stupid marketing driven process that declares all sizes in
useless megabits and not megabytes).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
NAND module should not modify EMIF registers unrelated to CS2
that is used for NAND, i.e. do not modify EWAIT config register
or registers for other Chip Selects.
Without this patch, EMIF configurations made in board_init()
will be invalidated.
Signed-off-by: Thomas Lange <thomas@corelatus.se>
This patch adds NAND Flash Controller driver for MPC5121 revision 2.
All device features, except hardware ECC and power management, are
supported.
This NFC driver replaces the one orignally posted by John Rigby:
"[PATCH] Freescale NFC NAND driver"
It's a port of the Linux driver version posted by Piotr Ziecik a few
weeks ago. Using this driver has the following advantages (from my
point of view):
- Compatibility with the Linux NAND driver (e.g. ECC usage)
- Better code quality in general
- Resulting U-Boot image is a bit smaller (approx. 3k)
- Better to sync with newer Linux driver versions
The only disadvantage I can see, is that HW-ECC is not supported right
now. But this could be added later (e.g. port from Linux driver after
it's supported there). Using HW-ECC on the MCP5121 NFC has a general
problem because of the ECC usage in the spare area. This collides with
JFFS2 for example.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Piotr Ziecik <kosmo@semihalf.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
UBI is quite memory greedy and requires at least approx. 512k of malloc
area. This patch adds a compile-time check, so that boards will not
build with less memory reserved for this area (CONFIG_SYS_MALLOC_LEN).
Signed-off-by: Stefan Roese <sr@denx.de>
Added macronix SF driver for MTD framework
MX25L12805D is supported and tested
TBD: sector erase implementation, other deivces support
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This new define enables mtdcore.c compilation and with this we can
select the MTD device infrastructure needed for the reworked mtdparts
command.
We now have the 2 MTD infrastructure defines, CONFIG_MTD_DEVICE and
CONFIG_MTD_PARTITIONS. CONFIG_MTD_DEVICE is needed (as explained above)
for the "mtdparts" command and CONFIG_MTD_PARTITIONS is needed for UBI.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
This patch brings the U-Boot MTD infrastructure in sync with the current
Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size
support and a resync of the mtdpart.c file which has seen multiple fixes
meanwhile.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kyungmin Park <kmpark@infradead.org>
This patch adds concatenation support to the U-Boot MTD infrastructure.
By enabling CONFIG_MTD_CONCAT this MTD CFI wrapper will concatenate
all found NOR devices into one single MTD device. This can be used by
e.g by UBI to access a partition that spans over multiple NOR chips.
Signed-off-by: Stefan Roese <sr@denx.de>
Several boards used different ways to specify the size of the
protected area when enabling flash write protection for the sectors
holding the environment variables: some used CONFIG_ENV_SIZE and
CONFIG_ENV_SIZE_REDUND, some used CONFIG_ENV_SECT_SIZE, and some even
a mix of both for the "normal" and the "redundant" areas.
Normally, this makes no difference at all. However, things are
different when you have to deal with boards that can come with
different types of flash chips, which may have different sector
sizes.
Here we may have to chose CONFIG_ENV_SECT_SIZE such that it fits the
biggest sector size, which may include several sectors on boards using
the smaller sector flash types. In such a case, using CONFIG_ENV_SIZE
or CONFIG_ENV_SIZE_REDUND to enable the protection may lead to the
case that only the first of these sectors get protected, while the
following ones aren't.
This is no real problem, but it can be confusing for the user -
especially on boards that use CONFIG_ENV_SECT_SIZE to protect the
"normal" areas, while using CONFIG_ENV_SIZE_REDUND for the
"redundant" area.
To avoid such inconsistencies, I changed all sucn boards that I found
to consistently use CONFIG_ENV_SECT_SIZE for protection. This should
not cause any functional changes to the code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Paul Ruhland
Cc: Pantelis Antoniou <panto@intracom.gr>
Cc: Stefan Roese <sr@denx.de>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: Dave Ellis <DGE@sixnetio.com>
Acked-by: Stefan Roese <sr@denx.de>
This patch now enabled this cfi-mtd wrapper to correctly detect and
erase the last sector in an NOR FLASH device.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables Smart Media (SMC) ECC byte ordering which is used
on the PPC4xx NAND FLASH controller (NDFC). Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
With this patch non-uniform NOR FLASH chips (chips with multiple erase
regions) can be exported via the cfi-mtd layer and therefor used by UBI.
We select the largest sector size as erasesize. The cfi driver will make
sure that the smaller sectors are handled correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
With this patch the NAND and OneNAND devices are registered in the MTD
subsystem and can then be referenced by the mtdcore code (e.g.
get_mtd_device_nm()). This is needed for the new "ubi part" command
syntax without the flash type parameter (nor|nand|onenand).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes this compilation warning when CONFIG_MTD_PARTITIONS is
defined:
nand_base.c: In function 'nand_release':
nand_base.c:2922: warning: implicit declaration of function 'del_mtd_partitions'
Signed-off-by: Stefan Roese <sr@denx.de>
Fix dependency goofage: it should certainly be possible to have the
partition support without bringing in UBI commands.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Stefan Roese <sr@denx.de>
We need to make sure the data written to the nand flash controller makes
it there before we start polling its status register. Otherwise, we may
get stale data and return before the controller is actually ready.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Scott Wood <scottwood@freescale.com>
On platforms with multiple NOR chips, currently only the first one
can be selected using the "ubi part" command. This patch fixes this
problem by using different names for the NOR "mtd devices".
It also changes the name of the NOR MTD device from "cfi-mtd" to
"norX" (X indexing the device numer) to better match the mtdparts
defaults.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
The AT91RM9200-EK Evaluation Board supports the AT91RM9200
ARM9-based 32-bit RISC microcontroller and enables real-time code development
and evaluation.
Here is the chip page on Atmel website:
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507
with
- NOR (cfi driver)
- DataFlash
- USB OHCI
- Net
- I2C (hard)
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Legacy NAND is marked for feature removal after April 2009 (i.e. this
upcoming release). There are still several boards that reference it
(though many do so only for disk-on-chip support which has been silently
disabled for a while now). These boards will now fail to build
with #error, though the code is still there if the user removes #error.
The plan is to remove the code outright in the next release, along with
any board code that refers to it (such as board/esd/common/auto_update.c).
Also, remove the legacy NAND API description from README.nand.
Signed-off-by: Scott Wood <scottwood@freescale.com>
I can't find anywhere in the datasheet that says the status register needs
3 dummy bytes sent to it before being able to read back the first real
result. Tests on a Blackfin board show that after writing the opcode, the
status register starts coming back immediately. So only write out the
read status register opcode before polling the result.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Jason McMullan <mcmullan@netapp.com>
CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Since timeouts are only hit when there is a problem in the system, we
don't want to prematurely timeout on a functioning setup. Thus having
low timeouts (in milliseconds) doesn't gain us anything in the production
case, but rather increases likely hood of causing problems where none
otherwise exist.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Some SPI flash drivers like to have extended id information available
(like the spansion flash), so rather than making it re-issue the ID cmd
to get at the last 2 bytes, have the common code read 5 bytes rather than
just 3. This also matches the Linux behavior where it always reads 5 id
bytes from all flashes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Mingkai Hu <Mingkai.hu@freescale.com>
The common SPI flash code reads the idcode and passes it down to the SPI
flash driver, so there is no need to read it again ourselves.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Jason McMullan <mcmullan@netapp.com>
CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Add MTD SPI Flash support for S25FL008A, S25FL016A,
S25FL032A, S25FL064A, S25FL128P.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The NAND flash on the TQM8548_BE modules requires a short delay after
running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE
requires a further short delay after writing out a buffer. Normally the
R/B pin should be checked, but it's not connected on the TQM8548_BE.
The corresponding Linux FSL UPM driver uses similar delay points at the
same locations. To manage these extra delays in a more general way, I
introduced the "wait_flags" field allowing the board-specific driver to
specify various types of extra delay.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For the NAND chips on the TQM8548 modules, a special chip-select logic is
used. It uses dedicated address lines to be set via UPM machine address
register (mar). This patch adds such support to the FSL-UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for multi-chip NAND devices to the FSL-UPM
driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now
called with the argument "chip_nr" to allow testing the proper chip
select line. The NAND support of the MPC8360ERDK is updated as well.
No other boards are currently using the FSL UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for NAND_MAX_CHIPS to the MTD NAND layer.
Multi-chips devices are displayed as shown:
Device 0: 2x NAND 512MiB 3,3V 8-bit, sector size 128 KiB
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
On the pcm030 the environment is located in the onboard EEPROM. But we want
to handle flash sector protection in a safe manner. So we must read the
unlock environment variable from EEPROM instead from flash.
This patch is required as long the evironment is saved into the EEPROM.
Stefan: Additional change as suggested by Wolfgang, use bigger char array
(instead of 4).
Signed-off-by: Eric Schumann <E.Schumann@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
