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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse source 
Conflicts:
	drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2009-07-07 22:22:05 +02:00
commit a48ecc969f
125 changed files with 7964 additions and 2421 deletions
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14
MAINTAINERS
View file

@ -209,6 +209,7 @@ Klaus Heydeck <heydeck@kieback-peter.de>
Ilko Iliev <iliev@ronetix.at>
PM9261 AT91SAM9261
PM9263 AT91SAM9263
Gary Jennejohn <garyj@denx.de>
@ -501,6 +502,11 @@ Rowel Atienza <rowel@diwalabs.com>
armadillo ARM720T
Stefano Babic <sbabic@denx.de>
polaris xscale
trizepsiv xscale
Dirk Behme <dirk.behme@gmail.com>
omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
@ -529,10 +535,18 @@ Thomas Elste <info@elste.org>
modnet50 ARM720T (NET+50)
Fabio Estevam <Fabio.Estevam@freescale.com>
mx31pdk i.MX31
Peter Figuli <peposh@etc.sk>
wepep250 xscale
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
meesc ARM926EJS (AT91SAM9263 SoC)
Marius Gröger <mag@sysgo.de>
impa7 ARM720T (EP7211)

9
MAKEALL
View file

@ -513,7 +513,8 @@ LIST_ARM9=" \
mx1ads \
mx1fs2 \
netstar \
nmdk8815 \
nhk8815 \
nhk8815_onenand \
omap1510inn \
omap1610h2 \
omap1610inn \
@ -555,6 +556,8 @@ LIST_ARM11=" \
imx31_phycore \
imx31_phycore_eet \
mx31ads \
mx31pdk \
mx31pdk_nand \
qong \
smdk6400 \
"
@ -588,8 +591,10 @@ LIST_at91=" \
cmc_pu2 \
csb637 \
kb9202 \
meesc \
mp2usb \
m501sk \
pm9261 \
pm9263 \
"
@ -605,7 +610,9 @@ LIST_pxa=" \
innokom \
lubbock \
pleb2 \
polaris \
pxa255_idp \
trizepsiv \
wepep250 \
xaeniax \
xm250 \

47
Makefile
View file

@ -2757,6 +2757,8 @@ at91sam9261ek_config : unconfig
fi;
@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
at91sam9263ek_norflash_config \
at91sam9263ek_norflash_boot_config \
at91sam9263ek_nandflash_config \
at91sam9263ek_dataflash_config \
at91sam9263ek_dataflash_cs0_config \
@ -2765,10 +2767,17 @@ at91sam9263ek_config : unconfig
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
elif [ "$(findstring norflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NORFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NOR FLASH" ; \
else \
echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
fi;
@if [ "$(findstring norflash_boot,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... and boot from NOR FLASH" ; \
fi;
@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
at91sam9rlek_nandflash_config \
@ -2785,6 +2794,12 @@ at91sam9rlek_config : unconfig
fi;
@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
meesc_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
pm9261_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
@ -2800,7 +2815,7 @@ ap720t_config \
ap920t_config \
ap926ejs_config \
ap946es_config: unconfig
@board/armltd/integratorap/split_by_variant.sh $@
@board/armltd/integrator/split_by_variant.sh ap $@
integratorcp_config \
cp_config \
@ -2812,7 +2827,7 @@ cp966_config \
cp922_config \
cp922_XA10_config \
cp1026_config: unconfig
@board/armltd/integratorcp/split_by_variant.sh $@
@board/armltd/integrator/split_by_variant.sh cp $@
davinci_dvevm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
@ -2842,17 +2857,17 @@ mx1fs2_config : unconfig
netstar_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t netstar
nmdk8815_config \
nmdk8815_onenand_config: unconfig
nhk8815_config \
nhk8815_onenand_config: unconfig
@mkdir -p $(obj)include
@ > $(obj)include/config.h
@if [ "$(findstring _onenand, $@)" ] ; then \
echo "#define CONFIG_BOOT_ONENAND" >> $(obj)include/config.h; \
$(XECHO) "... configured for OneNand Flash"; \
$(XECHO) "... configured to boot from OneNand Flash"; \
else \
$(XECHO) "... configured for Nand Flash"; \
$(XECHO) "... configured to boot from Nand Flash"; \
fi
@$(MKCONFIG) -a nmdk8815 arm arm926ejs nmdk8815 st nomadik
@$(MKCONFIG) -a nhk8815 arm arm926ejs nhk8815 st nomadik
omap1510inn_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
@ -3083,8 +3098,13 @@ scpu_config: unconfig
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
polaris_config \
trizepsiv_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
@mkdir -p $(obj)include
@if [ "$(findstring polaris,$@)" ] ; then \
echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -a trizepsiv arm pxa trizepsiv
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250
@ -3126,6 +3146,17 @@ imx31_phycore_config : unconfig
mx31ads_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
mx31pdk_config \
mx31pdk_nand_config : unconfig
@mkdir -p $(obj)include
@if [ -n "$(findstring _nand_,$@)" ]; then \
echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \
else \
echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \
echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h; \
fi
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx

5
README
View file

@ -2702,6 +2702,11 @@ Low Level (hardware related) configuration options:
some other boot loader or by a debugger which
performs these initializations itself.
- CONFIG_PRELOADER
Modifies the behaviour of start.S when compiling a loader
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
Building the Software:
======================

6
board/afeb9260/afeb9260.c
View file

@ -81,6 +81,8 @@ static void afeb9260_nand_hw_init(void)
#ifdef CONFIG_MACB
static void afeb9260_macb_hw_init(void)
{
unsigned long rstc;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
@ -103,6 +105,8 @@ static void afeb9260_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
@ -115,7 +119,7 @@ static void afeb9260_macb_hw_init(void)
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0 << 8) |
(rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */

2
board/armltd/.gitignore vendored
View file

@ -1,2 +0,0 @@
/integratorap/u-boot.lds
/integratorcp/u-boot.lds

19
board/armltd/integratorap/Makefile → board/armltd/integrator/Makefile
View file

@ -29,18 +29,21 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := integratorap.o flash.o
SOBJS := lowlevel_init.o
SOBJS-y := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
COBJS-y := integrator.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += timer.o
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
COBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
rm -f $(SOBJS) $(COBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend

0
board/armltd/integratorap/config.mk → board/armltd/integrator/config.mk
View file

135
board/armltd/integrator/integrator.c Normal file
View file

@ -0,0 +1,135 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* (C) Copyright 2004
* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#ifdef CONFIG_PCI
#include <netdev.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
#endif
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
/* arch number of Integrator Board */
#ifdef CONFIG_ARCH_CINTEGRATOR
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
#else
gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
gd->flags = 0;
#ifdef CONFIG_CM_REMAP
extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
icache_enable ();
return 0;
}
int misc_init_r (void)
{
#ifdef CONFIG_PCI
pci_init();
#endif
setenv("verify", "n");
return (0);
}
/******************************
Routine:
Description:
******************************/
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
unsigned long cm_reg_sdram;
unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
}
#endif /* CM_SPD_DETECT */
return 0;
}
#ifdef CONFIG_PCI
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
#endif

0
board/armltd/integratorap/lowlevel_init.S → board/armltd/integrator/lowlevel_init.S
View file

262
board/armltd/integratorap/integratorap.c → board/armltd/integrator/pci.c
View file

@ -34,77 +34,13 @@
*/
#include <common.h>
#ifdef CONFIG_PCI
#include <pci.h>
#endif
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
void flash__init (void);
void ether__init (void);
void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
#endif
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
/* arch number of Integrator Board */
gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
gd->flags = 0;
#ifdef CONFIG_CM_REMAP
extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
icache_enable ();
flash__init ();
return 0;
}
int misc_init_r (void)
{
#ifdef CONFIG_PCI
pci_init();
#endif
setenv("verify", "n");
return (0);
}
/*
* Initialize PCI Devices, report devices found.
*/
#ifdef CONFIG_PCI
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_integrator_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
@ -112,7 +48,7 @@ static struct pci_config_table pci_integrator_config_table[] = {
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ }
};
#endif
#endif /* CONFIG_PCI_PNP */
/* V3 access routines */
#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
@ -458,199 +394,3 @@ void pci_init_board (void)
hose->last_busno = pci_hose_scan (hose);
}
#endif
/******************************
Routine:
Description:
******************************/
void flash__init (void)
{
}
/*************************************************************
Routine:ether__init
Description: take the Ethernet controller out of reset and wait
for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
}
/******************************
Routine:
Description:
******************************/
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
unsigned long cm_reg_sdram;
unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
}
#endif /* CM_SPD_DETECT */
return 0;
}
/* The Integrator/AP timer1 is clocked at 24MHz
* can be divided by 16 or 256
* and is a 16-bit counter
*/
/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
static ulong timestamp; /* U-Boot ticks since startup */
static ulong total_count = 0; /* Total timer count */
static ulong lastdec; /* Timer reading at last call */
static ulong div_clock = 256; /* Divisor applied to the timer clock */
static ulong div_timer = 1; /* Divisor to convert timer reading
* change to U-Boot ticks
*/
/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
#define TIMER_LOAD_VAL 0x0000FFFFL
#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
* - unless otherwise stated
*/
/* starts a counter
* - the Integrator/AP timer issues an interrupt
* each time it reaches zero
*/
int timer_init (void)
{
/* Load timer with initial value */
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
/* Set timer to be
* enabled 1
* free-running 0
* XX 00
* divider 256 10
* XX 00
*/
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
total_count = 0;
/* init the timestamp and lastdec value */
reset_timer_masked();
div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
div_timer /= div_clock;
return (0);
}
/*
* timer without interrupts
*/
void reset_timer (void)
{
reset_timer_masked ();
}
ulong get_timer (ulong base_ticks)
{
return get_timer_masked () - base_ticks;
}
void set_timer (ulong ticks)
{
timestamp = ticks;
total_count = ticks * div_timer;
reset_timer_masked();
}
/* delay x useconds */
void udelay (unsigned long usec)
{
ulong tmo, tmp;
/* Convert to U-Boot ticks */
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000000L);
tmp = get_timer_masked(); /* get current timestamp */
tmo += tmp; /* wake up timestamp */
while (get_timer_masked () < tmo) { /* loop till event */
/*NOP*/;
}
}
void reset_timer_masked (void)
{
/* reset time */
lastdec = READ_TIMER; /* capture current decrementer value */
timestamp = 0; /* start "advancing" time stamp from 0 */
}
/* converts the timer reading to U-Boot ticks */
/* the timestamp is the number of ticks since reset */
/* This routine does not detect wraps unless called regularly
ASSUMES a call at least every 16 seconds to detect every reload */
ulong get_timer_masked (void)
{
ulong now = READ_TIMER; /* current count */
if (now > lastdec) {
/* Must have wrapped */
total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
} else {
total_count += lastdec - now;
}
lastdec = now;
timestamp = total_count/div_timer;
return timestamp;
}
/* waits specified delay value and resets timestamp */
void udelay_masked (unsigned long usec)
{
udelay(usec);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* Return the timebase clock frequency
* i.e. how often the timer decrements
*/
ulong get_tbclk (void)
{
return CONFIG_SYS_HZ_CLOCK/div_clock;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}

235
board/armltd/integrator/split_by_variant.sh Executable file
View file

@ -0,0 +1,235 @@
#!/bin/sh
mkdir -p ${obj}include
mkdir -p ${obj}board/armltd/integrator
config_file=${obj}include/config.h
if [ "$1" = "ap" ]
then
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
echo -n "/* Integrator configuration implied " > ${config_file}
echo " by Makefile target */" >> ${config_file}
echo -n "#define CONFIG_INTEGRATOR" >> ${config_file}
echo " /* Integrator board */" >> ${config_file}
echo -n "#define CONFIG_ARCH_INTEGRATOR" >> ${config_file}
echo " 1 /* Integrator/AP */" >> ${config_file}
# ---------------------------------------------------------
# Set the core module defines according to Core Module
# ---------------------------------------------------------
cpu="arm_intcm"
variant="unknown core module"
if [ "$2" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
case "$2" in
ap7_config)
cpu="arm_intcm"
variant="unported core module CM7TDMI"
;;
ap966)
cpu="arm_intcm"
variant="unported core module CM966E-S"
;;
ap922_config)
cpu="arm_intcm"
variant="unported core module CM922T"
;;
integratorap_config | \
ap_config)
cpu="arm_intcm"
variant="unspecified core module"
;;
ap720t_config)
cpu="arm720t"
echo -n "#define CONFIG_CM720T" >> ${config_file}
echo " 1 /* CPU core is ARM720T */ " >> ${config_file}
variant="Core module CM720T"
;;
ap922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
echo -n "#define CONFIG_CM922T_XA10" >> ${config_file}
echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file}
;;
ap920t_config)
cpu="arm920t"
variant="Core module CM920T"
echo -n "#define CONFIG_CM920T" >> ${config_file}
echo " 1 /* CPU core is ARM920T */" >> ${config_file}
;;
ap926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
echo -n "#define CONFIG_CM926EJ_S" >> ${config_file}
echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file}
;;
ap946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
echo -n "#define CONFIG_CM946E_S" >> ${config_file}
echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file}
;;
*)
echo "$0:: Unknown core module"
variant="unknown core module"
cpu="arm_intcm"
;;
esac
fi
case "$cpu" in
arm_intcm)
echo "/* Core module undefined/not ported */" >> ${config_file}
echo "#define CONFIG_ARM_INTCM 1" >> ${config_file}
echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file}
echo -n " /* CM may not have " >> ${config_file}
echo "multiple SSRAM mapping */" >> ${config_file}
echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file}
echo -n " /* CM may not support SPD " >> ${config_file}
echo "query */" >> ${config_file}
echo -n "#undef CONFIG_CM_REMAP " >> ${config_file}
echo -n " /* CM may not support " >> ${config_file}
echo "remapping */" >> ${config_file}
echo -n "#undef CONFIG_CM_INIT " >> ${config_file}
echo -n " /* CM may not have " >> ${config_file}
echo "initialization reg */" >> ${config_file}
echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file}
echo " /* CM may not have TCRAM */" >> ${config_file}
echo -n " /* May not be processor " >> ${config_file}
echo "without cache support */" >> ${config_file}
echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file}
echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file}
;;
arm720t)
echo -n " /* May not be processor " >> ${config_file}
echo "without cache support */" >> ${config_file}
echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file}
echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file}
;;
esac
else
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
echo -n "/* Integrator configuration implied " > ${config_file}
echo " by Makefile target */" >> ${config_file}
echo -n "#define CONFIG_INTEGRATOR" >> ${config_file}
echo " /* Integrator board */" >> ${config_file}
echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> ${config_file}
echo " 1 /* Integrator/CP */" >> ${config_file}
cpu="arm_intcm"
variant="unknown core module"
if [ "$2" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
case "$2" in
ap966)
cpu="arm_intcm"
variant="unported core module CM966E-S"
;;
ap922_config)
cpu="arm_intcm"
variant="unported core module CM922T"
;;
integratorcp_config | \
cp_config)
cpu="arm_intcm"
variant="unspecified core module"
;;
cp922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
echo -n "#define CONFIG_CM922T_XA10" >> ${config_file}
echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file}
;;
cp920t_config)
cpu="arm920t"
variant="Core module CM920T"
echo -n "#define CONFIG_CM920T" >> ${config_file}
echo " 1 /* CPU core is ARM920T */" >> ${config_file}
;;
cp926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
echo -n "#define CONFIG_CM926EJ_S" >> ${config_file}
echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file}
;;
cp946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
echo -n "#define CONFIG_CM946E_S" >> ${config_file}
echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file}
;;
cp1136_config)
cpu="arm1136"
variant="Core module CM1136EJF-S"
echo -n "#define CONFIG_CM1136EJF_S" >> ${config_file}
echo " 1 /* CPU core is ARM1136JF-S */ " >> ${config_file}
;;
*)
echo "$0:: Unknown core module"
variant="unknown core module"
cpu="arm_intcm"
;;
esac
fi
if [ "$cpu" = "arm_intcm" ]
then
echo "/* Core module undefined/not ported */" >> ${config_file}
echo "#define CONFIG_ARM_INTCM 1" >> ${config_file}
echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file}
echo -n " /* CM may not have " >> ${config_file}
echo "multiple SSRAM mapping */" >> ${config_file}
echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file}
echo -n " /* CM may not support SPD " >> ${config_file}
echo "query */" >> ${config_file}
echo -n "#undef CONFIG_CM_REMAP " >> ${config_file}
echo -n " /* CM may not support " >> ${config_file}
echo "remapping */" >> ${config_file}
echo -n "#undef CONFIG_CM_INIT " >> ${config_file}
echo -n " /* CM may not have " >> ${config_file}
echo "initialization reg */" >> ${config_file}
echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file}
echo " /* CM may not have TCRAM */" >> ${config_file}
fi
fi # ap
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
$MKCONFIG -a integrator$1 arm $cpu integrator armltd;
echo "Variant:: $variant with core $cpu"

161
board/armltd/integratorcp/integratorcp.c → board/armltd/integrator/timer.c
View file

@ -36,109 +36,13 @@
#include <common.h>
#include <div64.h>
DECLARE_GLOBAL_DATA_PTR;
void flash__init (void);
void ether__init (void);
void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
#ifdef CONFIG_ARCH_CINTEGRATOR
#define DIV_CLOCK_INIT 1
#define TIMER_LOAD_VAL 0xFFFFFFFFL
#else
#define DIV_CLOCK_INIT 256
#define TIMER_LOAD_VAL 0x0000FFFFL
#endif
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
/* arch number of Integrator Board */
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
gd->flags = 0;
#ifdef CONFIG_CM_REMAP
extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
icache_enable ();
flash__init ();
ether__init ();
return 0;
}
int misc_init_r (void)
{
setenv("verify", "n");
return (0);
}
/******************************
Routine:
Description:
******************************/
void flash__init (void)
{
}
/*************************************************************
Routine:ether__init
Description: take the Ethernet controller out of reset and wait
for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
}
/******************************
Routine:
Description:
******************************/
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
unsigned long cm_reg_sdram;
unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
}
#endif /* CM_SPD_DETECT */
return 0;
}
/* The Integrator/CP timer1 is clocked at 1MHz
* can be divided by 16 or 256
* and can be set up as a 32-bit timer
@ -147,14 +51,14 @@ extern void dram_query(void);
/* Keep total timer count to avoid losing decrements < div_timer */
static unsigned long long total_count = 0;
static unsigned long long lastdec; /* Timer reading at last call */
static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
/* Divisor applied to timer clock */
static unsigned long long div_clock = DIV_CLOCK_INIT;
static unsigned long long div_timer = 1; /* Divisor to convert timer reading
* change to U-Boot ticks
*/
/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
static ulong timestamp; /* U-Boot ticks since startup */
static ulong timestamp; /* U-Boot ticks since startup */
#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
@ -167,22 +71,35 @@ int timer_init (void)
{
/* Load timer with initial value */
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
#ifdef CONFIG_ARCH_CINTEGRATOR
/* Set timer to be
* enabled 1
* periodic 1
* no interrupts 0
* X 0
* divider 1 00 == less rounding error
* 32 bit 1
* wrapping 0
* enabled 1
* periodic 1
* no interrupts 0
* X 0
* divider 1 00 == less rounding error
* 32 bit 1
* wrapping 0
*/
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
#else
/* Set timer to be
* enabled 1
* free-running 0
* XX 00
* divider 256 10
* XX 00
*/
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
#endif
/* init the timestamp */
total_count = 0ULL;
reset_timer_masked();
div_timer = (unsigned long long)(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ);
div_timer /= div_clock;
div_timer = CONFIG_SYS_HZ_CLOCK;
do_div(div_timer, CONFIG_SYS_HZ);
do_div(div_timer, div_clock);
return (0);
}
@ -203,7 +120,7 @@ ulong get_timer (ulong base_ticks)
void set_timer (ulong ticks)
{
timestamp = ticks;
total_count = (unsigned long long)ticks * div_timer;
total_count = ticks * div_timer;
}
/* delay usec useconds */
@ -226,7 +143,7 @@ void udelay (unsigned long usec)
void reset_timer_masked (void)
{
/* capure current decrementer value */
lastdec = (unsigned long long)READ_TIMER;
lastdec = READ_TIMER;
/* start "advancing" time stamp from 0 */
timestamp = 0L;
}
@ -236,7 +153,7 @@ void reset_timer_masked (void)
ulong get_timer_masked (void)
{
/* get current count */
unsigned long long now = (unsigned long long)READ_TIMER;
unsigned long long now = READ_TIMER;
if(now > lastdec) {
/* Must have wrapped */
@ -244,7 +161,7 @@ ulong get_timer_masked (void)
} else {
total_count += lastdec - now;
}
lastdec = now;
lastdec = now;
/* Reuse "now" */
now = total_count;
@ -266,7 +183,7 @@ void udelay_masked (unsigned long usec)
*/
unsigned long long get_ticks(void)
{
return (unsigned long long)get_timer(0);
return get_timer(0);
}
/*
@ -275,5 +192,9 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk (void)
{
return (ulong)(((unsigned long long)CONFIG_SYS_HZ_CLOCK)/div_clock);
unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
do_div(tmp, div_clock);
return tmp;
}

473
board/armltd/integratorap/flash.c
View file

@ -1,473 +0,0 @@
/*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/byteorder/swab.h>
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32
#define FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define mb() __asm__ __volatile__ ("" : : : "memory")
/* Flash Organization Structure */
typedef struct OrgDef {
unsigned int sector_number;
unsigned int sector_size;
} OrgDef;
/* Flash Organizations */
OrgDef OrgIntel_28F256L18T[] = {
{4, 32 * 1024}, /* 4 * 32kBytes sectors */
{255, 128 * 1024}, /* 255 * 128kBytes sectors */
};
/*-----------------------------------------------------------------------
* Functions
*/
unsigned long flash_init (void);
static ulong flash_get_size (FPW * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
void flash_print_info (flash_info_t * info);
void flash_unprotect_sectors (FPWV * addr);
int flash_erase (flash_info_t * info, int s_first, int s_last);
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
default:
panic ("configured too many flash banks!\n");
break;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
OrgDef *pOrgDef;
pOrgDef = OrgIntel_28F256L18T;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
if (i > 255) {
info->start[i] = base + (i * 0x8000);
info->protect[i] = 0;
} else {
info->start[i] = base +
(i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F256L18T:
printf ("FLASH 28F256L18T\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW * addr, flash_info_t * info)
{
volatile FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW) 0x00AA00AA;
addr[0x2AAA] = (FPW) 0x00550055;
addr[0x5555] = (FPW) 0x00900090;
mb ();
value = addr[0];
switch (value) {
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[1]; /* device ID */
switch (value) {
case (FPW) (INTEL_ID_28F256L18T):
info->flash_id += FLASH_28F256L18T;
info->sector_count = 259;
info->size = 0x02000000;
break; /* => 32 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (info->size);
}
/* unprotects a sector for write and erase
* on some intel parts, this unprotects the entire chip, but it
* wont hurt to call this additional times per sector...
*/
void flash_unprotect_sectors (FPWV * addr)
{
#define PD_FINTEL_WSMS_READY_MASK 0x0080
*addr = (FPW) 0x00500050; /* clear status register */
/* this sends the clear lock bit command */
*addr = (FPW) 0x00600060;
*addr = (FPW) 0x00D000D0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
start = get_timer (0);
last = start;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
printf ("Erasing sector %2d ... ", sect);
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
*addr = (FPW) 0x00D000D0;/* erase confirm */
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
if (get_timer_masked () >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
*addr = (FPW) 0x00B000B0;
/* reset to read mode */
*addr = (FPW) 0x00FF00FF;
rcode = 1;
break;
}
}
/* clear status register cmd. */
*addr = (FPW) 0x00500050;
*addr = (FPW) 0x00FF00FF;/* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, SWAP (data)));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
return (2);
}
flash_unprotect_sectors (addr);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

127
board/armltd/integratorap/split_by_variant.sh
View file

@ -1,127 +0,0 @@
#!/bin/sh
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
echo -n "/* Integrator configuration implied " > tmp.fil
echo " by Makefile target */" >> tmp.fil
echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil
echo " /* Integrator board */" >> tmp.fil
echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil
echo " 1 /* Integrator/AP */" >> tmp.fil
# ---------------------------------------------------------
# Set the core module defines according to Core Module
# ---------------------------------------------------------
cpu="arm_intcm"
variant="unknown core module"
if [ "$1" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
case "$1" in
ap7_config)
cpu="arm_intcm"
variant="unported core module CM7TDMI"
;;
ap966)
cpu="arm_intcm"
variant="unported core module CM966E-S"
;;
ap922_config)
cpu="arm_intcm"
variant="unported core module CM922T"
;;
integratorap_config | \
ap_config)
cpu="arm_intcm"
variant="unspecified core module"
;;
ap720t_config)
cpu="arm720t"
echo -n "#define CONFIG_CM720T" >> tmp.fil
echo " 1 /* CPU core is ARM720T */ " >> tmp.fil
variant="Core module CM720T"
;;
ap922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil
echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil
;;
ap920t_config)
cpu="arm920t"
variant="Core module CM920T"
echo -n "#define CONFIG_CM920T" >> tmp.fil
echo " 1 /* CPU core is ARM920T */" >> tmp.fil
;;
ap926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil
echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil
;;
ap946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
echo -n "#define CONFIG_CM946E_S" >> tmp.fil
echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil
;;
*)
echo "$0:: Unknown core module"
variant="unknown core module"
cpu="arm_intcm"
;;
esac
fi
case "$cpu" in
arm_intcm)
echo "/* Core module undefined/not ported */" >> tmp.fil
echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil
echo -n " /* CM may not have " >> tmp.fil
echo "multiple SSRAM mapping */" >> tmp.fil
echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil
echo -n " /* CM may not support SPD " >> tmp.fil
echo "query */" >> tmp.fil
echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil
echo -n " /* CM may not support " >> tmp.fil
echo "remapping */" >> tmp.fil
echo -n "#undef CONFIG_CM_INIT " >> tmp.fil
echo -n " /* CM may not have " >> tmp.fil
echo "initialization reg */" >> tmp.fil
echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
echo " /* CM may not have TCRAM */" >> tmp.fil
echo -n " /* May not be processor " >> tmp.fil
echo "without cache support */" >> tmp.fil
echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil
echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil
;;
arm720t)
echo -n " /* May not be processor " >> tmp.fil
echo "without cache support */" >> tmp.fil
echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil
echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil
;;
esac
mkdir -p ${obj}include
mkdir -p ${obj}board/armltd/integratorap
mv tmp.fil ${obj}include/config.h
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
$MKCONFIG -a integratorap arm $cpu integratorap armltd;
echo "Variant:: $variant with core $cpu"

5
board/armltd/integratorcp/config.mk
View file

@ -1,5 +0,0 @@
#
# image should be loaded at 0x01000000
#
TEXT_BASE = 0x01000000

564
board/armltd/integratorcp/flash.c
View file

@ -1,564 +0,0 @@
/*
* (C) Copyright 2004
* Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com
*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/byteorder/swab.h>
#define DEBUG
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#define FLASH_PORT_WIDTH32
#undef FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define mb() __asm__ __volatile__ ("" : : : "memory")
/* Flash Organization Structure */
typedef struct OrgDef {
unsigned int sector_number;
unsigned int sector_size;
} OrgDef;
/* Flash Organizations */
OrgDef OrgIntel_28F256L18T[] = {
{4, 32 * 1024}, /* 4 * 32kBytes sectors */
{255, 128 * 1024}, /* 255 * 128kBytes sectors */
};
/* CP control register base address */
#define CPCR_BASE 0xCB000000
#define CPCR_EXTRABANK 0x8
#define CPCR_FLASHSIZE 0x4
#define CPCR_FLWREN 0x2
#define CPCR_FLVPPEN 0x1
/*-----------------------------------------------------------------------
* Functions
*/
unsigned long flash_init (void);
static ulong flash_get_size (FPW * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
void flash_print_info (flash_info_t * info);
void flash_unprotect_sectors (FPWV * addr);
int flash_erase (flash_info_t * info, int s_first, int s_last);
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i, nbanks;
ulong size = 0;
vu_long *cpcr = (vu_long *)CPCR_BASE;
/* Check if there is an extra bank of flash */
if (cpcr[1] & CPCR_EXTRABANK)
nbanks = 2;
else
nbanks = 1;
if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
/* Enable flash write */
cpcr[1] |= 3;
for (i = 0; i < nbanks; i++) {
flash_get_size ((FPW *)(CONFIG_SYS_FLASH_BASE + size), &flash_info[i]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE + size, &flash_info[i]);
size += flash_info[i].size;
}
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection */
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
/* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */
flash_protect (FLAG_PROTECT_SET,
flash_info[0].start[62],
flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1,
&flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
/* Integrator CP board uses 28F640J3C or 28F128J3C parts,
* which have the same device id numbers as 28F640J3A or
* 28F128J3A
*/
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F256L18T:
printf ("FLASH 28F256L18T\n");
break;
case FLASH_28F640J3A:
printf ("FLASH 28F640J3C\n");
break;
case FLASH_28F128J3A:
printf ("FLASH 28F128J3C\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW * addr, flash_info_t * info)
{
volatile FPW value;
vu_long *cpcr = (vu_long *)CPCR_BASE;
int nsects;
/* Check the flash size */
if (cpcr[1] & CPCR_FLASHSIZE)
nsects = 128;
else
nsects = 64;
if (nsects > CONFIG_SYS_MAX_FLASH_SECT)
nsects = CONFIG_SYS_MAX_FLASH_SECT;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW) 0x00AA00AA;
addr[0x2AAA] = (FPW) 0x00550055;
addr[0x5555] = (FPW) 0x00900090;
mb ();
value = addr[0];
switch (value) {
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[1]; /* device ID */
switch (value) {
case (FPW) (INTEL_ID_28F256L18T):
info->flash_id += FLASH_28F256L18T;
info->sector_count = 259;
info->size = 0x02000000;
break; /* => 32 MB */
case (FPW) (INTEL_ID_28F640J3A):
info->flash_id += FLASH_28F640J3A;
info->sector_count = nsects;
info->size = nsects * PHYS_FLASH_SECT_SIZE;
break;
case (FPW) (INTEL_ID_28F128J3A):
info->flash_id += FLASH_28F128J3A;
info->sector_count = nsects;
info->size = nsects * PHYS_FLASH_SECT_SIZE;
break;
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (info->size);
}
/* unprotects a sector for write and erase
* on some intel parts, this unprotects the entire chip, but it
* wont hurt to call this additional times per sector...
*/
void flash_unprotect_sectors (FPWV * addr)
{
FPW status;
*addr = (FPW) 0x00500050; /* clear status register */
/* this sends the clear lock bit command */
*addr = (FPW) 0x00600060;
*addr = (FPW) 0x00D000D0;
reset_timer_masked();
while (((status = *addr) & (FPW)0x00800080) != 0x00800080) {
if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout");
break;
}
}
*addr = (FPW) 0x00FF00FF;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
printf ("Erasing sector %2d ... ", sect);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* flash_unprotect_sectors (addr); */
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
mb();
udelay(1000); /* Let's wait 1 ms */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = (FPW)0x00700070;
status = *addr;
if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) {
/* erase suspended? Resume it */
reset_timer_masked();
*addr = (FPW) 0x00D000D0;
} else {
#ifdef DEBUG
printf ("Timeout,0x%08lx\n", status);
#else
printf("Timeout\n");
#endif
*addr = (FPW) 0x00500050;
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
}
}
*addr = (FPW) 0x00FF00FF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, SWAP (data)));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* flash_unprotect_sectors (addr); */
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
mb();
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
#ifdef DEBUG
*addr = (FPW) 0x00700070;
status = *addr;
printf("## status=0x%08lx, addr=0x%p\n", status, addr);
#endif
*addr = (FPW) 0x00500050; /* clear status register cmd */
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

214
board/armltd/integratorcp/lowlevel_init.S
View file

@ -1,214 +0,0 @@
/*
* Board specific setup info
*
* (C) Copyright 2003, ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
/* Reset using CM control register */
.global reset_cpu
reset_cpu:
mov r0, #CM_BASE
ldr r1,[r0,#OS_CTRL]
orr r1,r1,#CMMASK_RESET
str r1,[r0,#OS_CTRL]
reset_failed:
b reset_failed
/* Set up the platform, once the cpu has been initialized */
.globl lowlevel_init
lowlevel_init:
/* If U-Boot has been run after the ARM boot monitor
* then all the necessary actions have been done
* otherwise we are running from user flash mapped to 0x00000000
* --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
* Changes to the (possibly soft) reset defaults of the processor
* itself should be performed in cpu/arm<>/start.S
* This function affects only the core module or board settings
*/
#ifdef CONFIG_CM_INIT
/* CM has an initialization register
* - bits in it are wired into test-chip pins to force
* reset defaults
* - may need to change its contents for U-Boot
*/
/* set the desired CM specific value */
mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
orr r2,r2,#CMMASK_INIT_102
#else
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
/* CMxx6 code */
#ifdef CONFIG_CM_MULTIPLE_SSRAM
/* set simple mapping */
and r2,r2,#CMMASK_MAP_SIMPLE
#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
#ifdef CONFIG_CM_TCRAM
/* disable TCRAM */
and r2,r2,#CMMASK_TCRAM_DISABLE
#endif /* #ifdef CONFIG_CM_TCRAM */
#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
defined (CONFIG_CM1136JF_S)
and r2,r2,#CMMASK_LE
#endif /* cpu with little endian initialization */
orr r2,r2,#CMMASK_CMxx6_COMMON
#endif /* CMxx6 code */
#endif /* ARM102xxE value */
/* read CM_INIT */
mov r0, #CM_BASE
ldr r1, [r0, #OS_INIT]
/* check against desired bit setting */
and r3,r1,r2
cmp r3,r2
beq init_reg_OK
/* lock for change */
mov r3, #CMVAL_LOCK1
and r3, r3, #CMVAL_LOCK2
str r3, [r0, #OS_LOCK]
/* set desired value */
orr r1,r1,r2
/* write & relock CM_INIT */
str r1, [r0, #OS_INIT]
mov r1, #CMVAL_UNLOCK
str r1, [r0, #OS_LOCK]
/* soft reset so new values used */
b reset_cpu
init_reg_OK:
#endif /* CONFIG_CM_INIT */
mov pc, lr
#ifdef CONFIG_CM_SPD_DETECT
/* Fast memory is available for the DRAM data
* - ensure it has been transferred, then summarize the data
* into a CM register
*/
.globl dram_query
dram_query:
stmfd r13!,{r4-r6,lr}
/* set up SDRAM info */
/* - based on example code from the CM User Guide */
mov r0, #CM_BASE
readspdbit:
ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
and r1, r1, #0x20 /* mask SPD bit (5) */
cmp r1, #0x20 /* test if set */
bne readspdbit
setupsdram:
add r0, r0, #OS_SPD /* address the copy of the SDP data */
ldrb r1, [r0, #3] /* number of row address lines */
ldrb r2, [r0, #4] /* number of column address lines */
ldrb r3, [r0, #5] /* number of banks */
ldrb r4, [r0, #31] /* module bank density */
mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
mov r5, r5, ASL#2 /* size in MB */
mov r0, #CM_BASE /* reload for later code */
cmp r5, #0x10 /* is it 16MB? */
bne not16
mov r6, #0x2 /* store size and CAS latency of 2 */
b writesize
not16:
cmp r5, #0x20 /* is it 32MB? */
bne not32
mov r6, #0x6
b writesize
not32:
cmp r5, #0x40 /* is it 64MB? */
bne not64
mov r6, #0xa
b writesize
not64:
cmp r5, #0x80 /* is it 128MB? */
bne not128
mov r6, #0xe
b writesize
not128:
/* if it is none of these sizes then it is either 256MB, or
* there is no SDRAM fitted so default to 256MB
*/
mov r6, #0x12
writesize:
mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
orr r2, r1, r2, ASL#12 /* OR in column address lines */
orr r3, r2, r3, ASL#16 /* OR in number of banks */
orr r6, r6, r3 /* OR in size and CAS latency */
str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
#endif /* #ifdef CONFIG_CM_SPD_DETECT */
ldmfd r13!,{r4-r6,pc} /* back to caller */
#ifdef CONFIG_CM_REMAP
/* CM remap bit is operational
* - use it to map writeable memory at 0x00000000, in place of flash
*/
.globl cm_remap
cm_remap:
stmfd r13!,{r4-r10,lr}
mov r0, #CM_BASE
ldr r1, [r0, #OS_CTRL]
orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
str r1, [r0, #OS_CTRL]
/* Now 0x00000000 is writeable, replace the vectors */
ldr r0, =_start /* r0 <- start of vectors */
ldr r2, =_armboot_start /* r2 <- past vectors */
sub r1,r1,r1 /* destination 0x00000000 */
copy_vec:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_vec
ldmfd r13!,{r4-r10,pc} /* back to caller */
#endif /* #ifdef CONFIG_CM_REMAP */

110
board/armltd/integratorcp/split_by_variant.sh
View file

@ -1,110 +0,0 @@
#!/bin/sh
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
echo -n "/* Integrator configuration implied " > tmp.fil
echo " by Makefile target */" >> tmp.fil
echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil
echo " /* Integrator board */" >> tmp.fil
echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil
echo " 1 /* Integrator/CP */" >> tmp.fil
cpu="arm_intcm"
variant="unknown core module"
if [ "$1" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
case "$1" in
ap966)
cpu="arm_intcm"
variant="unported core module CM966E-S"
;;
ap922_config)
cpu="arm_intcm"
variant="unported core module CM922T"
;;
integratorcp_config | \
cp_config)
cpu="arm_intcm"
variant="unspecified core module"
;;
cp922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil
echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil
;;
cp920t_config)
cpu="arm920t"
variant="Core module CM920T"
echo -n "#define CONFIG_CM920T" >> tmp.fil
echo " 1 /* CPU core is ARM920T */" >> tmp.fil
;;
cp926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil
echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil
;;
cp946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
echo -n "#define CONFIG_CM946E_S" >> tmp.fil
echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil
;;
cp1136_config)
cpu="arm1136"
variant="Core module CM1136EJF-S"
echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil
echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil
;;
*)
echo "$0:: Unknown core module"
variant="unknown core module"
cpu="arm_intcm"
;;
esac
fi
if [ "$cpu" = "arm_intcm" ]
then
echo "/* Core module undefined/not ported */" >> tmp.fil
echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil
echo -n " /* CM may not have " >> tmp.fil
echo "multiple SSRAM mapping */" >> tmp.fil
echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil
echo -n " /* CM may not support SPD " >> tmp.fil
echo "query */" >> tmp.fil
echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil
echo -n " /* CM may not support " >> tmp.fil
echo "remapping */" >> tmp.fil
echo -n "#undef CONFIG_CM_INIT " >> tmp.fil
echo -n " /* CM may not have " >> tmp.fil
echo "initialization reg */" >> tmp.fil
echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
echo " /* CM may not have TCRAM */" >> tmp.fil
fi
mkdir -p ${obj}include
mkdir -p ${obj}board/armltd/integratorcp
mv tmp.fil ${obj}include/config.h
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
$MKCONFIG -a integratorcp arm $cpu integratorcp armltd;
echo "Variant:: $variant with core $cpu"

7
board/armltd/versatile/versatile.c
View file

@ -46,13 +46,6 @@ void show_boot_progress(int progress)
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/

6
board/atmel/at91sam9260ek/at91sam9260ek.c
View file

@ -86,6 +86,8 @@ static void at91sam9260ek_nand_hw_init(void)
#ifdef CONFIG_MACB
static void at91sam9260ek_macb_hw_init(void)
{
unsigned long rstc;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
@ -108,6 +110,8 @@ static void at91sam9260ek_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
@ -120,7 +124,7 @@ static void at91sam9260ek_macb_hw_init(void)
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0 << 8)) |
(rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */

4
board/atmel/at91sam9263ek/Makefile
View file

@ -33,9 +33,9 @@ COBJS-y += at91sam9263ek.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

25
board/atmel/at91sam9263ek/at91sam9263ek.c
View file

@ -91,6 +91,8 @@ static void at91sam9263ek_nand_hw_init(void)
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
unsigned long rstc;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
@ -108,6 +110,8 @@ static void at91sam9263ek_macb_hw_init(void)
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
@ -120,7 +124,7 @@ static void at91sam9263ek_macb_hw_init(void)
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0 << 8)) |
(rstc) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
@ -196,9 +200,16 @@ static void at91sam9263ek_lcd_hw_init(void)
#include <nand.h>
#include <version.h>
#ifndef CONFIG_SYS_NO_FLASH
extern flash_info_t flash_info[];
#endif
void lcd_show_board_info(void)
{
ulong dram_size, nand_size;
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
#endif
int i;
char temp[32];
@ -215,9 +226,19 @@ void lcd_show_board_info(void)
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
#ifndef CONFIG_SYS_NO_FLASH
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
flash_size += flash_info[i].size;
#endif
lcd_printf (" %ld MB SDRAM, %ld MB NAND",
dram_size >> 20,
nand_size >> 20 );
#ifndef CONFIG_SYS_NO_FLASH
lcd_printf (",\n %ld MB NOR",
flash_size >> 20);
#endif
lcd_puts ("\n");
}
#endif /* CONFIG_LCD_INFO */
#endif

55
board/esd/meesc/Makefile Normal file
View file

@ -0,0 +1,55 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
board/esd/meesc/config.mk Normal file
View file

@ -0,0 +1 @@
TEXT_BASE = 0x21f00000

198
board/esd/meesc/meesc.c Normal file
View file

@ -0,0 +1,198 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2009
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
static int hw_rev = -1; /* hardware revision */
int get_hw_rev(void)
{
if (hw_rev >= 0)
return hw_rev;
hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
if (hw_rev == 15)
hw_rev = 0;
return hw_rev;
}
#ifdef CONFIG_CMD_NAND
static void meesc_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
#ifdef CONFIG_MACB
static void meesc_macb_hw_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
at91_macb_hw_init();
}
#endif
/*
* Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
* controller debugging
* The ET1100 is located at physical address 0x70000000
* Its process memory is located at physical address 0x70001000
*/
static void meesc_ethercat_hw_init(void)
{
/* Configure SMC EBI1_CS0 for EtherCAT */
at91_sys_write(AT91_SMC1_SETUP(0),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC1_PULSE(0),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
at91_sys_write(AT91_SMC1_CYCLE(0),
AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
/* Configure behavior at external wait signal, byte-select mode, 16 bit
data bus width, none data float wait states and TDF optimization */
at91_sys_write(AT91_SMC1_MODE(0),
AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
AT91_SMC_TDFMODE);
/* Configure RDY/BSY */
at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
#endif
return rc;
}
int checkboard(void)
{
char str[32];
puts("Board: esd CAN-EtherCAT Gateway");
if (getenv_r("serial#", str, sizeof(str)) > 0) {
puts(", serial# ");
puts(str);
}
printf("\nHardware-revision: 1.%d\n", get_hw_rev());
printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
return 0;
}
int board_init(void)
{
/* Peripheral Clock Enable Register */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE);
/* arch number of MEESC-Board */
gd->bd->bi_arch_number = MACH_TYPE_MEESC;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91_serial_hw_init();
#ifdef CONFIG_CMD_NAND
meesc_nand_hw_init();
#endif
meesc_ethercat_hw_init();
#ifdef CONFIG_HAS_DATAFLASH
at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
meesc_macb_hw_init();
#endif
#ifdef CONFIG_AT91_CAN
at91_can_hw_init();
#endif
return 0;
}

37
board/esd/meesc/partition.c Normal file
View file

@ -0,0 +1,37 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
/* define the area offsets */
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
};

5
board/armltd/integratorcp/Makefile → board/freescale/mx31pdk/Makefile
View file

@ -1,4 +1,6 @@
#
# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -25,8 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := integratorcp.o flash.o
SOBJS := lowlevel_init.o
COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

5
board/freescale/mx31pdk/config.mk Normal file
View file

@ -0,0 +1,5 @@
ifdef CONFIG_NAND_SPL
TEXT_BASE = 0x87ec0000
else
TEXT_BASE = 0x87f00000
endif

93
board/freescale/mx31pdk/lowlevel_init.S Normal file
View file

@ -0,0 +1,93 @@
/*
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/mx31-regs.h>
#include <asm/macro.h>
.globl lowlevel_init
lowlevel_init:
/* Also setup the Peripheral Port Remap register inside the core */
ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
mcr p15, 0, r0, c15, c2, 4
write32 IPU_CONF, IPU_CONF_DI_EN
write32 CCM_CCMR, CCM_CCMR_SETUP
wait_timer 0x40000
write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
/* Set up clock to 532MHz */
write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
/* Set up MX31 DDR pins */
write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
/* Set up MX31 DDR Memory Controller */
write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
/* Perform DDR init sequence */
write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
write32 CSD0_BASE | 0x0f00, 0x12344321
write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
write32 CSD0_BASE, 0x12344321
write32 CSD0_BASE, 0x12344321
write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
write8 CSD0_BASE | 0x00000033, 0xda
write8 CSD0_BASE | 0x01000000, 0xff
write32 WEIM_ESDCTL0, ESDCTL_RW
write32 CSD0_BASE, 0xDEADBEEF
write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
mov pc, lr

63
board/freescale/mx31pdk/mx31pdk.c Normal file
View file

@ -0,0 +1,63 @@
/*
*
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
int board_init(void)
{
/* CS5: CPLD incl. network controller */
__REG(CSCR_U(5)) = 0x0000d843;
__REG(CSCR_L(5)) = 0x22252521;
__REG(CSCR_A(5)) = 0x22220a00;
/* Setup UART1 and SPI2 pins */
mx31_uart1_hw_init();
mx31_spi2_hw_init();
gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int checkboard(void)
{
printf("Board: i.MX31 MAX PDK (3DS)\n");
return 0;
}

16
board/omap3/evm/evm.c
View file

@ -92,17 +92,17 @@ void set_muxconf_regs(void)
static void setup_net_chip(void)
{
gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

57
board/ronetix/pm9261/Makefile Normal file
View file

@ -0,0 +1,57 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
# Ilko Iliev <www.ronetix.at>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
board/ronetix/pm9261/config.mk Normal file
View file

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

44
board/ronetix/pm9261/led.c Normal file
View file

@ -0,0 +1,44 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
* Ilko Iliev <www.ronetix.at>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
}

47
board/ronetix/pm9261/partition.c Normal file
View file

@ -0,0 +1,47 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
* Ilko Iliev <www.ronetix.at>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
/*define the area offsets*/
#ifdef CONFIG_SYS_USE_DATAFLASH
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
#else
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
};
#endif

288
board/ronetix/pm9261/pm9261.c Normal file
View file

@ -0,0 +1,288 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#include <dataflash.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
#ifdef CONFIG_CMD_NAND
static void pm9261_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PA16, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PC14, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_DRIVER_DM9000
static void pm9261_dm9000_hw_init(void)
{
/* Configure SMC CS2 for DM9000 */
at91_sys_write(AT91_SMC_SETUP(2),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(2),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
at91_sys_write(AT91_SMC_CYCLE(2),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(2),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_(1));
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PA24, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9261_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */
}
static void pm9261_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
gd->fb_base = AT91SAM9261_SRAM_BASE;
}
#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>
extern flash_info_t flash_info[];
void lcd_show_board_info(void)
{
ulong dram_size, nand_size, flash_size, dataflash_size;
int i;
char temp[32];
lcd_printf ("%s\n", U_BOOT_VERSION);
lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz",
AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
flash_size += flash_info[i].size;
dataflash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
dataflash_info[i].Device.pages_size;
lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
"%ld MB DataFlash\n",
dram_size >> 20,
nand_size >> 20,
flash_size >> 20,
dataflash_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_LCD */
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
/* arch number of PM9261-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9261;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91_serial_hw_init();
#ifdef CONFIG_CMD_NAND
pm9261_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_DRIVER_DM9000
pm9261_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
pm9261_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
char buf[32];
printf ("Board : Ronetix PM9261\n");
printf ("Crystal frequency: %8s MHz\n",
strmhz(buf, get_main_clk_rate()));
printf ("CPU clock : %8s MHz\n",
strmhz(buf, get_cpu_clk_rate()));
printf ("Master clock : %8s MHz\n",
strmhz(buf, get_mck_clk_rate()));
return 0;
}
#endif

4
board/ronetix/pm9263/Makefile
View file

@ -34,10 +34,6 @@ COBJS-y += pm9263.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
SOBJS-y := lowlevel_init.o
endif
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))

23
board/ronetix/pm9263/pm9263.c
View file

@ -165,6 +165,27 @@ void lcd_disable(void)
static int pm9263_lcd_hw_psram_init(void)
{
volatile uint16_t x;
unsigned long csa;
/* Enable CS3 3.3v, no pull-ups */
csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
at91_sys_write(AT91_MATRIX_EBI1CSA,
csa | AT91_MATRIX_EBI1_DBPUC |
AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
/* Configure SMC1 CS0 for PSRAM - 16-bit */
at91_sys_write(AT91_SMC1_SETUP(0),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC1_PULSE(0),
AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
at91_sys_write(AT91_SMC1_CYCLE(0),
AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
at91_sys_write(AT91_SMC1_MODE(0),
AT91_SMC_DBW_16 |
AT91_SMC_PMEN |
AT91_SMC_PS_32);
/* setup PB29 as output */
at91_set_gpio_output(PSRAM_CRE_PIN, 1);
@ -218,7 +239,7 @@ static int pm9263_lcd_hw_psram_init(void)
at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
AT91_MATRIX_DEFMSTR_TYPE_FIXED |
(AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
(AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
return 0;
}

2
board/st/nmdk8815/Makefile → board/st/nhk8815/Makefile
View file

@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := nmdk8815.o
COBJS := nhk8815.o
SOBJS := platform.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

0
board/st/nmdk8815/config.mk → board/st/nhk8815/config.mk
View file

4
board/st/nmdk8815/nmdk8815.c → board/st/nhk8815/nhk8815.c
View file

@ -53,6 +53,10 @@ int board_init(void)
writel(0x0000305b, REG_FSMC_BCR1);
writel(0x00033f33, REG_FSMC_BTR1);
/* Set up SMCS0 for OneNand: sram-like once again */
writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
icache_enable();
return 0;
}

0
board/st/nmdk8815/platform.S → board/st/nhk8815/platform.S
View file

27
board/trizepsiv/conxs.c
View file

@ -44,13 +44,18 @@ extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
#if CONFIG_POLARIS
#define BOOT_CONSOLE "serial_stuart"
#else
#define BOOT_CONSOLE "serial_ffuart"
#endif
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
void usb_board_init(void)
int usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
@ -71,6 +76,8 @@ void usb_board_init(void)
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
return 0;
}
void usb_board_init_fail(void)
@ -89,7 +96,6 @@ void usb_board_stop(void)
CKEN &= ~CKEN10_USBHOST;
puts("Called USB STOP\n");
return;
}
@ -112,17 +118,14 @@ int board_late_init(void)
#if defined(CONFIG_SERIAL_MULTI)
char *console=getenv("boot_console");
if ((strcmp(console,"serial_btuart") == 0) ||
(strcmp(console,"serial_stuart") == 0) ||
(strcmp(console,"serial_ffuart") == 0)) {
setenv("stdout",console);
setenv("stdin", console);
setenv("stderr",console);
} else {
setenv("stdout", "serial");
setenv("stdin", "serial");
setenv("stderr", "serial");
if ((console == NULL) || (strcmp(console,"serial_btuart") &&
strcmp(console,"serial_stuart") &&
strcmp(console,"serial_ffuart"))) {
console = BOOT_CONSOLE;
}
setenv("stdout",console);
setenv("stdin", console);
setenv("stderr",console);
#endif
return 0;
}

1
cpu/arm1136/mx31/Makefile
View file

@ -27,6 +27,7 @@ LIB = $(obj)lib$(SOC).a
COBJS += generic.o
COBJS += timer.o
COBJS += devices.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

56
cpu/arm1136/mx31/devices.c Normal file
View file

@ -0,0 +1,56 @@
/*
*
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/mx31-regs.h>
#include <asm/arch/mx31.h>
#ifdef CONFIG_SYS_MX31_UART1
void mx31_uart1_hw_init(void)
{
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
}
#endif
#ifdef CONFIG_MXC_SPI
void mx31_spi2_hw_init(void)
{
/* SPI2 */
mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
/* start SPI2 clock */
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
}
#endif

33
cpu/arm1136/start.S
View file

@ -32,7 +32,7 @@
#include <version.h>
.globl _start
_start: b reset
#ifdef CONFIG_ONENAND_IPL
#ifdef CONFIG_PRELOADER
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
@ -67,7 +67,7 @@ _not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_PRELOADER */
.global _end_vect
_end_vect:
@ -156,9 +156,9 @@ relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
#ifndef CONFIG_ONENAND_IPL
#ifndef CONFIG_PRELOADER
beq stack_setup
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_PRELOADER */
ldr r2, _armboot_start
ldr r3, _bss_start
@ -175,7 +175,7 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
#ifdef CONFIG_ONENAND_IPL
#ifdef CONFIG_PRELOADER
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
@ -184,14 +184,14 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_PRELOADER */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_ONENAND_IPL
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
@ -200,12 +200,15 @@ clbss_l:str r2, [r0] /* clear loop... */
ldr pc, _start_armboot
#ifdef CONFIG_NAND_SPL
_start_armboot: .word nand_boot
#else
#ifdef CONFIG_ONENAND_IPL
_start_armboot: .word start_oneboot
#else
_start_armboot: .word start_armboot
#endif
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_NAND_SPL */
/*
*************************************************************************
@ -217,6 +220,7 @@ _start_armboot: .word start_armboot
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
@ -243,8 +247,9 @@ cpu_init_crit:
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_ONENAND_IPL
#ifndef CONFIG_PRELOADER
/*
*************************************************************************
*
@ -357,17 +362,17 @@ cpu_init_crit:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_PRELOADER */
/*
* exception handlers
*/
#ifdef CONFIG_ONENAND_IPL
#ifdef CONFIG_PRELOADER
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
#else /* !CONFIG_ONENAND IPL */
#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@ -435,4 +440,4 @@ fiq:
arm1136_cache_flush:
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
mov pc, lr @ back to caller
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_PRELOADER */

16
cpu/arm1176/cpu.c
View file

@ -58,22 +58,6 @@ int cleanup_before_linux (void)
return 0;
}
/* * reset the cpu by setting up the watchdog timer and let him time out */
void reset_cpu (ulong ignored)
{
printf("reset... \n\n\n");
SW_RST_REG = 0x6400;
/* loop forever and wait for reset to happen */
while (1) {
if (serial_tstc()) {
serial_getc();
break;
}
}
/*NOTREACHED*/
}
/* flush I/D-cache */
static void cache_flush (void)
{

2
cpu/arm1176/s3c64xx/Makefile
View file

@ -28,6 +28,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
SOBJS = reset.o
COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
COBJS-y += timer.o

34
cpu/arm1176/s3c64xx/reset.S Normal file
View file

@ -0,0 +1,34 @@
/*
* Copyright (c) 2009 Samsung Electronics.
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <s3c6400.h>
.globl reset_cpu
reset_cpu:
ldr r1, =ELFIN_CLOCK_POWER_BASE
ldr r2, [r1, #SYS_ID_OFFSET]
ldr r3, =0xffff
and r2, r3, r2, lsr #12
str r2, [r1, #SW_RST_OFFSET]
_loop_forever:
b _loop_forever

8
cpu/arm920t/Makefile
View file

@ -26,10 +26,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = cpu.o interrupts.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
COBJS-y += cpu.o
COBJS-$(CONFIG_USE_IRQ) += interrupts.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)

10
cpu/arm920t/interrupts.c
View file

@ -30,20 +30,14 @@
*/
#include <common.h>
#ifdef CONFIG_USE_IRQ
#include <asm/proc-armv/ptrace.h>
#if defined (CONFIG_ARCH_INTEGRATOR)
void do_irq (struct pt_regs *pt_regs)
{
#if defined (ARM920_IRQ_CALLBACK)
ARM920_IRQ_CALLBACK();
#elif defined (CONFIG_ARCH_INTEGRATOR)
/* ASSUMED to be a timer interrupt */
/* Just clear it - count handled in */
/* integratorap.c */
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
#else
#error do_irq() not defined for this cpu type
#endif
}
#endif

14
cpu/arm920t/s3c24x0/Makefile
View file

@ -25,13 +25,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS += speed.o
COBJS += timer.o
COBJS += usb.o
COBJS += usb_ohci.o
COBJS-$(CONFIG_USE_IRQ) += interrupts.o
COBJS-y += speed.o
COBJS-y += timer.o
COBJS-y += usb.o
COBJS-y += usb_ohci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)

46
cpu/arm920t/s3c24x0/interrupts.c Normal file
View file

@ -0,0 +1,46 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/proc-armv/ptrace.h>
void do_irq (struct pt_regs *pt_regs)
{
S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
u_int32_t intpnd = irq->INTPND;
}

9
cpu/arm920t/s3c24x0/timer.c
View file

@ -215,13 +215,4 @@ void reset_cpu (ulong ignored)
/*NOTREACHED*/
}
#ifdef CONFIG_USE_IRQ
void s3c2410_irq(void)
{
S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
u_int32_t intpnd = irq->INTPND;
}
#endif /* USE_IRQ */
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */

8
cpu/arm926ejs/at91/Makefile
View file

@ -37,8 +37,12 @@ COBJS-y += cpu.o
COBJS-y += reset.o
COBJS-y += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
ifndef CONFIG_SKIP_LOWLEVEL_INIT
SOBJS-y := lowlevel_init.o
endif
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
all: $(obj).depend $(LIB)

15
cpu/arm926ejs/at91/at91cap9_devices.c
View file

@ -3,6 +3,10 @@
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2009
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -174,3 +178,14 @@ void at91_macb_hw_init(void)
#endif
}
#endif
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */
at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN);
}
#endif

15
cpu/arm926ejs/at91/at91sam9263_devices.c
View file

@ -3,6 +3,10 @@
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2009
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -182,3 +186,14 @@ void at91_uhp_hw_init(void)
at91_set_gpio_output(AT91_PIN_PA24, 0);
}
#endif
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */
at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN);
}
#endif

39
board/ronetix/pm9263/lowlevel_init.S → cpu/arm926ejs/at91/lowlevel_init.S
View file

@ -33,9 +33,9 @@
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_wdt.h>
#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91sam9263_matrix.h>
_TEXT_BASE:
.word TEXT_BASE
@ -87,8 +87,9 @@ POS1:
*/
ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
ldr r0, =0x0000FF01
str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
/* Main oscillator Enable register PMC_MOR: */
ldr r0, =CONFIG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
mov r4, #AT91_PMC_MOSCS
@ -119,7 +120,7 @@ MOSCS_Loop1:
/* ----------------------------------------------------------------------------
* PMC Init Step 3.
* ----------------------------------------------------------------------------
* - Switch on the Main Oscillator 18.432 MHz
* - Switch on the Main Oscillator
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
@ -185,21 +186,32 @@ SMRDATA:
.word (AT91_BASE_SYS + AT91_WDT_MR)
.word CONFIG_SYS_WDTC_WDMR_VAL
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
.word CONFIG_SYS_PIOD_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
.word CONFIG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9261)
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
.word CONFIG_SYS_PIOC_PDR_VAL1
.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
.word CONFIG_SYS_PIOC_PPUDR_VAL
#endif
#if defined(AT91_MATRIX_EBI0CSA)
.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
.word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
.word CONFIG_SYS_MATRIX_EBI1CSA_VAL
#else /* AT91_MATRIX_EBICSA */
.word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
.word CONFIG_SYS_MATRIX_EBICSA_VAL
#endif
/* flash */
.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
.word CONFIG_SYS_SMC0_CTRL0_VAL
.word CONFIG_SYS_SMC0_MODE0_VAL
.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
.word CONFIG_SYS_SMC0_CYCLE0_VAL
@ -210,19 +222,6 @@ SMRDATA:
.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
.word CONFIG_SYS_SMC0_SETUP0_VAL
/* PSRAM */
.word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
.word CONFIG_SYS_SMC1_CTRL0_VAL
.word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
.word CONFIG_SYS_SMC1_CYCLE0_VAL
.word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
.word CONFIG_SYS_SMC1_PULSE0_VAL
.word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
.word CONFIG_SYS_SMC1_SETUP0_VAL
SMRDATA1:
.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
.word CONFIG_SYS_SDRC_MR_VAL1

49
cpu/arm926ejs/kirkwood/Makefile Normal file
View file

@ -0,0 +1,49 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS-y = dram.o
COBJS-y += cpu.o
COBJS-y += mpp.o
COBJS-y += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

311
cpu/arm926ejs/kirkwood/cpu.c Normal file
View file

@ -0,0 +1,311 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/cache.h>
#include <u-boot/md5.h>
#include <asm/arch/kirkwood.h>
#define BUFLEN 16
void reset_cpu(unsigned long ignored)
{
struct kwcpu_registers *cpureg =
(struct kwcpu_registers *)KW_CPU_REG_BASE;
writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
&cpureg->rstoutn_mask);
writel(readl(&cpureg->sys_soft_rst) | 1,
&cpureg->sys_soft_rst);
while (1) ;
}
/*
* Generates Ramdom hex number reading some time varient system registers
* and using md5 algorithm
*/
unsigned char get_random_hex(void)
{
int i;
u32 inbuf[BUFLEN];
u8 outbuf[BUFLEN];
/*
* in case of 88F6281/88F6192 A0,
* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
* Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
* Does not have names at this moment (no errata available)
*/
writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
for (i = 0; i < BUFLEN; i++) {
inbuf[i] = readl(KW_REG_UNDOC_0x1470);
}
md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
return outbuf[outbuf[7] % 0x0f];
}
/*
* Window Size
* Used with the Base register to set the address window size and location.
* Must be programmed from LSB to MSB as sequence of ones followed by
* sequence of zeros. The number of ones specifies the size of the window in
* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
* NOTE: A value of 0x0 specifies 64-KByte size.
*/
unsigned int kw_winctrl_calcsize(unsigned int sizeval)
{
int i;
unsigned int j = 0;
u32 val = sizeval >> 1;
for (i = 0; val > 0x10000; i++) {
j |= (1 << i);
val = val >> 1;
}
return (0x0000ffff & j);
}
/*
* kw_config_adr_windows - Configure address Windows
*
* There are 8 address windows supported by Kirkwood Soc to addess different
* devices. Each window can be configured for size, BAR and remap addr
* Below configuration is standard for most of the cases
*
* If remap function not used, remap_lo must be set as base
*
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
*/
int kw_config_adr_windows(void)
{
struct kwwin_registers *winregs =
(struct kwwin_registers *)KW_CPU_WIN_BASE;
/* Window 0: PCIE MEM address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
writel(0x0, &winregs[0].remap_hi);
/* Window 1: PCIE IO address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
writel(KW_DEFADR_PCI_IO, &winregs[1].base);
writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
writel(0x0, &winregs[1].remap_hi);
/* Window 2: NAND Flash address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
writel(KW_DEFADR_NANDF, &winregs[2].base);
writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
writel(0x0, &winregs[2].remap_hi);
/* Window 3: SPI Flash address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
writel(KW_DEFADR_SPIF, &winregs[3].base);
writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
writel(0x0, &winregs[3].remap_hi);
/* Window 4: BOOT Memory address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
writel(KW_DEFADR_BOOTROM, &winregs[4].base);
/* Window 5: Security SRAM address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
writel(KW_DEFADR_SASRAM, &winregs[5].base);
/* Window 6-7: Disabled */
writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
return 0;
}
/*
* kw_config_gpio - GPIO configuration
*/
void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
{
struct kwgpio_registers *gpio0reg =
(struct kwgpio_registers *)KW_GPIO0_BASE;
struct kwgpio_registers *gpio1reg =
(struct kwgpio_registers *)KW_GPIO1_BASE;
/* Init GPIOS to default values as per board requirement */
writel(gpp0_oe_val, &gpio0reg->dout);
writel(gpp1_oe_val, &gpio1reg->dout);
writel(gpp0_oe, &gpio0reg->oe);
writel(gpp1_oe, &gpio1reg->oe);
}
/*
* kw_config_mpp - Multi-Purpose Pins Functionality configuration
*
* Each MPP can be configured to different functionality through
* MPP control register, ref (sec 6.1 of kirkwood h/w specification)
*
* There are maximum 64 Multi-Pourpose Pins on Kirkwood
* Each MPP functionality can be configuration by a 4bit value
* of MPP control reg, the value and associated functionality depends
* upon used SoC varient
*/
int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
{
u32 *mppreg = (u32 *) KW_MPP_BASE;
/* program mpp registers */
writel(mpp0_7, &mppreg[0]);
writel(mpp8_15, &mppreg[1]);
writel(mpp16_23, &mppreg[2]);
writel(mpp24_31, &mppreg[3]);
writel(mpp32_39, &mppreg[4]);
writel(mpp40_47, &mppreg[5]);
writel(mpp48_55, &mppreg[6]);
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
char *name = "Unknown";
switch (readl(KW_REG_DEVICE_ID) & 0x03) {
case 1:
name = "88F6192_A0";
break;
case 2:
name = "88F6281_A0";
break;
default:
printf("SoC: Unsupported Kirkwood\n");
return -1;
}
printf("SoC: Kirkwood %s\n", name);
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
u32 reg;
struct kwcpu_registers *cpureg =
(struct kwcpu_registers *)KW_CPU_REG_BASE;
/* Linux expects` the internal registers to be at 0xf1000000 */
writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
/* Enable and invalidate L2 cache in write through mode */
writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
invalidate_l2_cache();
kw_config_adr_windows();
#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
/*
* Configures the I/O voltage of the pads connected to Egigabit
* Ethernet interface to 1.8V
* By defult it is set to 3.3V
*/
reg = readl(KW_REG_MPP_OUT_DRV_REG);
reg |= (1 << 7);
writel(reg, KW_REG_MPP_OUT_DRV_REG);
#endif
#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
/*
* Set egiga port0/1 in normal functional mode
* This is required becasue on kirkwood by default ports are in reset mode
* OS egiga driver may not have provision to set them in normal mode
* and if u-boot is build without network support, network may fail at OS level
*/
reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
reg &= ~(1 << 4); /* Clear PortReset Bit */
writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
reg &= ~(1 << 4); /* Clear PortReset Bit */
writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
#endif
#ifdef CONFIG_KIRKWOOD_PCIE_INIT
/*
* Enable PCI Express Port0
*/
reg = readl(&cpureg->ctrl_stat);
reg |= (1 << 0); /* Set PEX0En Bit */
writel(reg, &cpureg->ctrl_stat);
#endif
return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */
/*
* SOC specific misc init
*/
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
volatile u32 temp;
/*CPU streaming & write allocate */
temp = readfr_extra_feature_reg();
temp &= ~(1 << 28); /* disable wr alloc */
writefr_extra_feature_reg(temp);
temp = readfr_extra_feature_reg();
temp &= ~(1 << 29); /* streaming disabled */
writefr_extra_feature_reg(temp);
/* L2Cache settings */
temp = readfr_extra_feature_reg();
/* Disable L2C pre fetch - Set bit 24 */
temp |= (1 << 24);
/* enable L2C - Set bit 22 */
temp |= (1 << 22);
writefr_extra_feature_reg(temp);
icache_enable();
/* Change reset vector to address 0x0 */
temp = get_cr();
set_cr(temp & ~CR_V);
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
#ifdef CONFIG_KIRKWOOD_EGIGA
int cpu_eth_init(bd_t *bis)
{
kirkwood_egiga_initialize(bis);
return 0;
}
#endif

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cpu/arm926ejs/kirkwood/dram.c Normal file
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/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <config.h>
#include <asm/arch/kirkwood.h>
#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
/*
* kw_sdram_bar - reads SDRAM Base Address Register
*/
u32 kw_sdram_bar(enum memory_bank bank)
{
u32 result = 0;
u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
if ((!enable) || (bank > BANK3))
return 0;
result = readl(KW_REG_CPUCS_WIN_BAR(bank));
return result;
}
/*
* kw_sdram_bs - reads SDRAM Bank size
*/
u32 kw_sdram_bs(enum memory_bank bank)
{
u32 result = 0;
u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
if ((!enable) || (bank > BANK3))
return 0;
result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
result += 0x01000000;
return result;
}

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cpu/arm926ejs/kirkwood/mpp.c Normal file
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/*
* arch/arm/mach-kirkwood/mpp.c
*
* MPP functions for Marvell Kirkwood SoCs
* Referenced from Linux kernel source
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <common.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
static u32 kirkwood_variant(void)
{
switch (readl(KW_REG_DEVICE_ID) & 0x03) {
case 1:
return MPP_F6192_MASK;
case 2:
return MPP_F6281_MASK;
default:
debug("MPP setup: unknown kirkwood variant\n");
return 0;
}
}
#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
#define MPP_NR_REGS (1 + MPP_MAX/8)
void kirkwood_mpp_conf(u32 *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
int i;
variant_mask = kirkwood_variant();
if (!variant_mask)
return;
debug( "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
debug(" %08x", mpp_ctrl[i]);
}
debug("\n");
while (*mpp_list) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift;
if (num > MPP_MAX) {
debug("kirkwood_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (!(*mpp_list & variant_mask)) {
debug("kirkwood_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
mpp_list++;
}
debug(" final MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
writel(mpp_ctrl[i], MPP_CTRL(i));
debug(" %08x", mpp_ctrl[i]);
}
debug("\n");
}

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cpu/arm926ejs/kirkwood/timer.c Normal file
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/*
* Copyright (C) Marvell International Ltd. and its affiliates
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/arch/kirkwood.h>
#define UBOOT_CNTR 0 /* counter to use for uboot timer */
/* Timer reload and current value registers */
struct kwtmr_val {
u32 reload; /* Timer reload reg */
u32 val; /* Timer value reg */
};
/* Timer registers */
struct kwtmr_registers {
u32 ctrl; /* Timer control reg */
u32 pad[3];
struct kwtmr_val tmr[2];
u32 wdt_reload;
u32 wdt_val;
};
struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
/*
* ARM Timers Registers Map
*/
#define CNTMR_CTRL_REG &kwtmr_regs->ctrl
#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload
#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val
/*
* ARM Timers Control Register
* CPU_TIMERS_CTRL_REG (CTCR)
*/
#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
/*
* ARM Timer\Watchdog Reload Register
* CNTMR_RELOAD_REG (TRR)
*/
#define TRG_ARM_TIMER_REL_OFFS 0
#define TRG_ARM_TIMER_REL_MASK 0xffffffff
/*
* ARM Timer\Watchdog Register
* CNTMR_VAL_REG (TVRG)
*/
#define TVR_ARM_TIMER_OFFS 0
#define TVR_ARM_TIMER_MASK 0xffffffff
#define TVR_ARM_TIMER_MAX 0xffffffff
#define TIMER_LOAD_VAL 0xffffffff
#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
(CONFIG_SYS_TCLK / 1000))
static ulong timestamp;
static ulong lastdec;
void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER;
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong now = READ_TIMER;
if (lastdec >= now) {
/* normal mode */
timestamp += lastdec - now;
} else {
/* we have an overflow ... */
timestamp += lastdec +
(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
}
lastdec = now;
return timestamp;
}
void reset_timer(void)
{
reset_timer_masked();
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
void udelay(unsigned long usec)
{
uint current;
ulong delayticks;
current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
if (current < delayticks) {
delayticks -= current;
while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
while ((TIMER_LOAD_VAL - delayticks) <
readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
} else {
while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
(current - delayticks)) ;
}
}
/*
* init the counter
*/
int timer_init(void)
{
unsigned int cntmrctrl;
/* load value into timer */
writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
/* enable timer in auto reload mode */
cntmrctrl = readl(CNTMR_CTRL_REG);
cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
writel(cntmrctrl, CNTMR_CTRL_REG);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}

44
cpu/arm926ejs/mx27/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = generic.o reset.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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cpu/arm926ejs/mx27/generic.c Normal file
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/*
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> 10) & 0xf;
unsigned int mfn = pll & 0x3ff;
unsigned int mfd = (pll >> 16) & 0x3ff;
unsigned int pd = (pll >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
(mfd + 1) * (pd + 1));
}
static ulong clk_in_32k(void)
{
return 1024 * CONFIG_MX27_CLK32;
}
static ulong clk_in_26m(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
/* divide by 1.5 */
return 26000000 * 2 / 3;
} else {
return 26000000;
}
}
ulong imx_get_mpllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_MCU_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->mpctl0), fref);
}
ulong imx_get_armclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
if (!(cscr & CSCR_ARM_SRC_MPLL))
fref = lldiv((fref * 2), 3);
div = ((cscr >> 12) & 0x3) + 1;
return lldiv(fref, div);
}
ulong imx_get_ahbclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
div = ((cscr >> 8) & 0x3) + 1;
return lldiv(fref * 2, 3 * div);
}
ulong imx_get_spllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_SP_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->spctl0), fref);
}
static ulong imx_decode_perclk(ulong div)
{
return lldiv((imx_get_mpllclk() * 2), (div * 3));
}
ulong imx_get_perclk1(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
}
ulong imx_get_perclk2(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
}
ulong imx_get_perclk3(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
}
ulong imx_get_perclk4(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
char buf[32];
printf("CPU: Freescale i.MX27 at %s MHz\n\n",
strmhz(buf, imx_get_mpllclk()));
return 0;
}
#endif
void imx_gpio_mode(int gpio_mode)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
unsigned int tmp;
/* Pullup enable */
if (gpio_mode & GPIO_PUEN) {
writel(readl(&regs->port[port].puen) | (1 << pin),
&regs->port[port].puen);
} else {
writel(readl(&regs->port[port].puen) & ~(1 << pin),
&regs->port[port].puen);
}
/* Data direction */
if (gpio_mode & GPIO_OUT) {
writel(readl(&regs->port[port].ddir) | 1 << pin,
&regs->port[port].ddir);
} else {
writel(readl(&regs->port[port].ddir) & ~(1 << pin),
&regs->port[port].ddir);
}
/* Primary / alternate function */
if (gpio_mode & GPIO_AF) {
writel(readl(&regs->port[port].gpr) | (1 << pin),
&regs->port[port].gpr);
} else {
writel(readl(&regs->port[port].gpr) & ~(1 << pin),
&regs->port[port].gpr);
}
/* use as gpio? */
if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
writel(readl(&regs->port[port].gius) | (1 << pin),
&regs->port[port].gius);
} else {
writel(readl(&regs->port[port].gius) & ~(1 << pin),
&regs->port[port].gius);
}
/* Output / input configuration */
if (pin < 16) {
tmp = readl(&regs->port[port].ocr1);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr1);
writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
&regs->port[port].iconfb1);
writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
&regs->port[port].iconfb1);
} else {
pin -= 16;
tmp = readl(&regs->port[port].ocr2);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr2);
writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
&regs->port[port].iconfb2);
writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
&regs->port[port].iconfb2);
}
}

57
cpu/arm926ejs/mx27/reset.c Normal file
View file

@ -0,0 +1,57 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu (ulong ignored)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writel(0x00000000, &regs->wcr);
/* Write Service Sequence */
writel(0x00005555, &regs->wsr);
writel(0x0000AAAA, &regs->wsr);
/* Enable watchdog */
writel(WCR_WDE, &regs->wcr);
while (1);
/*NOTREACHED*/
}

191
cpu/arm926ejs/mx27/timer.c Normal file
View file

@ -0,0 +1,191 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 8) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
static ulong timestamp;
static ulong lastinc;
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX27_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX27_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX27_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &regs->gpt_tctl);
writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
for (i = 0; i < 100; i++)
writel(0, &regs->gpt_tctl); /* We have no udelay by now */
writel(0, &regs->gpt_tprer); /* 32Khz */
/* Freerun Mode, PERCLK1 input */
writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&regs->gpt_tctl);
writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
return 0;
}
void reset_timer_masked(void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
/* reset time */
/* capture current incrementer value time */
lastinc = readl(&regs->gpt_tcn);
timestamp = 0; /* start "advancing" time stamp from 0 */
}
void reset_timer(void)
{
reset_timer_masked();
}
unsigned long long get_ticks (void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
ulong now = readl(&regs->gpt_tcn); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
ulong get_timer_masked (void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
void set_timer (ulong t)
{
timestamp = time_to_tick(t);
}
/* delay x useconds AND perserve advance timstamp value */
void udelay (unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}

13
cpu/arm926ejs/nomadik/reset.S
View file

@ -6,20 +6,9 @@
.align 5
.globl reset_cpu
reset_cpu:
#if defined CONFIG_NOMADIK_8815
ldr r0, =NOMADIK_SRC_BASE
ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
ldr r1, =0x1
str r1, [r0, #0x18]
#else
ldr r1, rstctl1 /* get clkm1 reset ctl */
mov r3, #0x0
strh r3, [r1] /* clear it */
mov r3, #0x8
strh r3, [r1] /* force dsp+arm reset */
#endif
_loop_forever:
b _loop_forever
rstctl1:
.word 0xfffece10

166
cpu/arm926ejs/nomadik/timer.c
View file

@ -1,20 +1,5 @@
/*
* (C) Copyright 2003
* Texas Instruments <www.ti.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002-2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2004
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
* (C) Copyright 2009 Alessandro Rubini
*
* See file CREDITS for list of people who contributed to this
* project.
@ -37,146 +22,49 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mtu.h>
#define TIMER_LOAD_VAL 0xffffffff
/*
* The timer is a decrementer, we'll left it free running at 2.4MHz.
* We have 2.4 ticks per microsecond and an overflow in almost 30min
*/
#define TIMER_CLOCK (24 * 100 * 1000)
#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
/* macro to read the 32 bit timer */
#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20)
/* macro to read the 32 bit timer: since it decrements, we invert read value */
#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
static ulong timestamp;
static ulong lastdec;
/* nothing really to do with interrupts, just starts up a counter. */
/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
{
/* Load timer with initial value */
writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16);
/*
* Set timer to be enabled, free-running, no interrupts, 256 divider,
* 32-bit, wrap-mode
*/
writel(0x8a, CONFIG_SYS_TIMERBASE + 24);
/* init the timestamp and lastdec value */
reset_timer_masked();
writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
CONFIG_SYS_TIMERBASE + MTU_CR(0));
reset_timer();
return 0;
}
/*
* timer without interrupts
*/
/* Restart counting from 0 */
void reset_timer(void)
{
reset_timer_masked();
writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
}
/* Return how many HZ passed since "base" */
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
return TICKS_TO_HZ(READ_TIMER()) - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
/* delay x useconds AND perserve advance timstamp value */
/* Delay x useconds */
void udelay(unsigned long usec)
{
ulong tmo, tmp;
ulong ini, end;
if (usec >= 1000) {
/* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
tmo /= 1000; /* finish normalize. */
} else {
/* small number, don't kill it prior to HZ multiply */
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000 * 1000);
}
tmp = get_timer(0); /* get current timestamp */
if ((tmo + tmp + 1) < tmp) /* will roll time stamp? */
reset_timer_masked(); /* reset to 0, set lastdec value */
else
tmo += tmp;
while (get_timer_masked() < tmo)
/* nothing */ ;
}
void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER; /* capure current decrementer value time */
timestamp = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
{
ulong now = READ_TIMER; /* current tick value */
if (lastdec >= now) { /* normal mode (non roll) */
/* move stamp fordward */
timestamp += lastdec - now;
} else {
/*
* An overflow is expected.
* nts = ts + ld + (TLV - now)
* ts=old stamp, ld=time that passed before passing through -1
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll
*/
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
return timestamp;
}
/* waits specified delay value and resets timestamp */
void udelay_masked(unsigned long usec)
{
ulong tmo;
if (usec >= 1000) {
/* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
tmo /= 1000; /* finish normalize. */
} else {
/* else small number, don't kill it prior to HZ multiply */
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
reset_timer_masked();
/* set "advancing" timestamp to 0, set lastdec vaule */
while (get_timer_masked() < tmo)
/* nothing */ ;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CONFIG_SYS_HZ;
return tbclk;
ini = READ_TIMER();
end = ini + USEC_TO_COUNT(usec);
while ((signed)(end - READ_TIMER()) > 0)
;
}

70
cpu/arm_cortexa8/cpu.c
View file

@ -33,12 +33,8 @@
#include <common.h>
#include <command.h>
#include <asm/arch/sys_proto.h>
#include <asm/system.h>
#ifndef CONFIG_L2_OFF
void l2cache_disable(void);
#endif
#include <asm/cache.h>
static void cache_flush(void);
@ -63,7 +59,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2cache_disable();
l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@ -72,72 +68,14 @@ int cleanup_before_linux(void)
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
#ifndef CONFIG_L2_OFF
l2cache_enable();
l2_cache_enable();
#endif
return 0;
}
void l2cache_enable()
{
unsigned long i;
volatile unsigned int j;
/* ES2 onwards we can disable/enable L2 ourselves */
if (get_cpu_rev() >= CPU_3XX_ES20) {
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
} else {
/* Save r0, r12 and restore them after usage */
__asm__ __volatile__("mov %0, r12":"=r"(j));
__asm__ __volatile__("mov %0, r0":"=r"(i));
/*
* GP Device ROM code API usage here
* r12 = AUXCR Write function and r0 value
*/
__asm__ __volatile__("mov r12, #0x3");
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
__asm__ __volatile__("orr r0, r0, #0x2");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j));
}
}
void l2cache_disable()
{
unsigned long i;
volatile unsigned int j;
/* ES2 onwards we can disable/enable L2 ourselves */
if (get_cpu_rev() >= CPU_3XX_ES20) {
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
} else {
/* Save r0, r12 and restore them after usage */
__asm__ __volatile__("mov %0, r12":"=r"(j));
__asm__ __volatile__("mov %0, r0":"=r"(i));
/*
* GP Device ROM code API usage here
* r12 = AUXCR Write function and r0 value
*/
__asm__ __volatile__("mov r12, #0x3");
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
__asm__ __volatile__("bic r0, r0, #0x2");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j));
}
}
static void cache_flush(void)
{
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
}

1
cpu/arm_cortexa8/omap3/Makefile
View file

@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
COBJS += board.o
COBJS += cache.o
COBJS += clock.o
COBJS += gpio.o
COBJS += mem.o

5
cpu/arm_cortexa8/omap3/board.c
View file

@ -36,6 +36,7 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
extern omap3_sysinfo sysinfo;
@ -206,9 +207,9 @@ void s_init(void)
#endif
#ifdef CONFIG_L2_OFF
l2cache_disable();
l2_cache_disable();
#else
l2cache_enable();
l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV

96
cpu/arm_cortexa8/omap3/cache.c Normal file
View file

@ -0,0 +1,96 @@
/*
* (C) Copyright 2008 Texas Insturments
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* omap3 L2 cache code
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
void l2_cache_enable(void)
{
unsigned long i;
volatile unsigned int j;
/* ES2 onwards we can disable/enable L2 ourselves */
if (get_cpu_rev() >= CPU_3XX_ES20) {
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
} else {
/* Save r0, r12 and restore them after usage */
__asm__ __volatile__("mov %0, r12":"=r"(j));
__asm__ __volatile__("mov %0, r0":"=r"(i));
/*
* GP Device ROM code API usage here
* r12 = AUXCR Write function and r0 value
*/
__asm__ __volatile__("mov r12, #0x3");
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
__asm__ __volatile__("orr r0, r0, #0x2");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j));
}
}
void l2_cache_disable(void)
{
unsigned long i;
volatile unsigned int j;
/* ES2 onwards we can disable/enable L2 ourselves */
if (get_cpu_rev() >= CPU_3XX_ES20) {
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
} else {
/* Save r0, r12 and restore them after usage */
__asm__ __volatile__("mov %0, r12":"=r"(j));
__asm__ __volatile__("mov %0, r0":"=r"(i));
/*
* GP Device ROM code API usage here
* r12 = AUXCR Write function and r0 value
*/
__asm__ __volatile__("mov r12, #0x3");
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
__asm__ __volatile__("bic r0, r0, #0x2");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j));
}
}

5
doc/README.at91
View file

@ -62,11 +62,16 @@ Environment variables
U-Boot environment variables can be stored at different places:
- Dataflash on SPI chip select 0 (dataflash card)
- Nand flash.
- Nor falsh (not populate by default)
You can choose your storage location at config step (here for at91sam9260ek) :
make at91sam9263ek_config - use data flash (spi cs0) (default)
make at91sam9263ek_nandflash_config - use nand flash
make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
make at91sam9263ek_norflash_config - use nor falsh
You can choose to boot directly from U-Boot at config step
make at91sam9263ek_norflash_boot_config - boot from nor falsh
------------------------------------------------------------------------------

10
doc/README.nmdk8815 → doc/README.nhk8815
View file

@ -15,6 +15,16 @@ SDRAM configuration, PLL setup and initial loading from NAND is
implemented in the X-Loader, so U-Boot is already running in SDRAM
when control is handed over to it.
The Makefile offers two different configurations to be used if you
boot from Nand or OneNand.
make nhk8815_config
make nhk8815_onenand_config
Both support OneNand and Nand. Since U-Boot, running in RAM, can't know
where it was loaded from, the configurations differ in where the filesystem
is looked for by default.
On www.st.com/nomadik and on www.stnwireless.com there are documents,
summary data and white papers on Nomadik. The full datasheet for

12
drivers/mtd/nand/davinci_nand.c
View file

@ -386,9 +386,6 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
static void nand_flash_init(void)
{
u_int32_t acfg1 = 0x3ffffffc;
u_int32_t acfg2 = 0x3ffffffc;
u_int32_t acfg3 = 0x3ffffffc;
u_int32_t acfg4 = 0x3ffffffc;
emifregs emif_regs;
/*------------------------------------------------------------------*
@ -413,12 +410,9 @@ static void nand_flash_init(void)
emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
emif_regs->AWCCR |= 0x10000000;
emif_regs->AB1CR = acfg1; /* 0x08244128 */;
emif_regs->AB2CR = acfg2;
emif_regs->AB3CR = acfg3;
emif_regs->AB4CR = acfg4;
emif_regs->NANDFCR = 0x00000101;
emif_regs->AB1CR = acfg1; /* CS2 */
emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
}
int board_nand_init(struct nand_chip *nand)

1
drivers/net/kirkwood_egiga.c
View file

@ -662,3 +662,4 @@ int kirkwood_egiga_initialize(bd_t * bis)
#endif
}
return 0;
}

2
drivers/serial/Makefile
View file

@ -41,7 +41,7 @@ COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-$(CONFIG_MX31_UART) += serial_mx31.o
COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o

3
drivers/serial/serial.c
View file

@ -27,6 +27,9 @@
#ifdef CONFIG_NS87308
#include <ns87308.h>
#endif
#ifdef CONFIG_KIRKWOOD
#include <asm/arch/kirkwood.h>
#endif
#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>

21
drivers/serial/serial_mx31.c → drivers/serial/serial_mxc.c
View file

@ -18,7 +18,12 @@
*/
#include <common.h>
#ifdef CONFIG_MX31
#include <asm/arch/mx31.h>
#else
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#endif
#define __REG(x) (*((volatile u32 *)(x)))
@ -32,6 +37,18 @@
#define UART_PHYS 0x43fb0000
#elif defined(CONFIG_SYS_MX31_UART5)
#define UART_PHYS 0x43fb4000
#elif defined(CONFIG_SYS_MX27_UART1)
#define UART_PHYS 0x1000a000
#elif defined(CONFIG_SYS_MX27_UART2)
#define UART_PHYS 0x1000b000
#elif defined(CONFIG_SYS_MX27_UART3)
#define UART_PHYS 0x1000c000
#elif defined(CONFIG_SYS_MX27_UART4)
#define UART_PHYS 0x1000d000
#elif defined(CONFIG_SYS_MX27_UART5)
#define UART_PHYS 0x1001b000
#elif defined(CONFIG_SYS_MX27_UART6)
#define UART_PHYS 0x1001c000
#else
#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
#endif
@ -149,7 +166,11 @@ DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
#ifdef CONFIG_MX31
u32 clk = mx31_get_ipg_clk();
#else
u32 clk = imx_get_perclk1();
#endif
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;

1
drivers/spi/Makefile
View file

@ -28,6 +28,7 @@ LIB := $(obj)libspi.a
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o

185
drivers/spi/kirkwood_spi.c Normal file
View file

@ -0,0 +1,185 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Derived from drivers/spi/mpc8xxx_spi.c
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/spi.h>
#include <asm/arch/mpp.h>
static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
u32 data;
u32 kwspi_mpp_config[] = {
MPP0_GPIO,
MPP7_SPI_SCn,
0
};
if (!spi_cs_is_valid(bus, cs))
return NULL;
slave = malloc(sizeof(struct spi_slave));
if (!slave)
return NULL;
slave->bus = bus;
slave->cs = cs;
writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
/* calculate spi clock prescaller using max_hz */
data = ((CONFIG_SYS_TCLK / 2) / max_hz) & KWSPI_CLKPRESCL_MASK;
data |= 0x10;
/* program spi clock prescaller using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
debug("data = 0x%08x \n", data);
writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
writel(KWSPI_IRQMASK, spireg->irq_mask);
/* program mpp registers to select SPI_CSn */
if (cs) {
kwspi_mpp_config[0] = MPP0_GPIO;
kwspi_mpp_config[1] = MPP7_SPI_SCn;
} else {
kwspi_mpp_config[0] = MPP0_SPI_SCn;
kwspi_mpp_config[1] = MPP7_GPO;
}
kirkwood_mpp_conf(kwspi_mpp_config);
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
free(slave);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
#ifndef CONFIG_SPI_CS_IS_VALID
/*
* you can define this function board specific
* define above CONFIG in board specific config file and
* provide the function in board specific src file
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return (bus == 0 && (cs == 0 || cs == 1));
}
#endif
void spi_cs_activate(struct spi_slave *slave)
{
writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
unsigned int tmpdout, tmpdin;
int tm, isread = 0;
debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
slave->bus, slave->cs, dout, din, bitlen);
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
/*
* handle data in 8-bit chunks
* TBD: 2byte xfer mode to be enabled
*/
writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) |
KWSPI_XFERLEN_1BYTE), &spireg->cfg);
while (bitlen > 4) {
debug("loopstart bitlen %d\n", bitlen);
tmpdout = 0;
/* Shift data so it's msb-justified */
if (dout)
tmpdout = *(u32 *) dout & 0x0ff;
writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause);
writel(tmpdout, &spireg->dout); /* Write the data out */
debug("*** spi_xfer: ... %08x written, bitlen %d\n",
tmpdout, bitlen);
/*
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* The NE event must be read and cleared first
*/
for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
isread = 1;
tmpdin = readl(&spireg->din);
debug
("spi_xfer: din %08x..%08x read\n",
din, tmpdin);
if (din) {
*((u8 *) din) = (u8) tmpdin;
din += 1;
}
if (dout)
dout += 1;
bitlen -= 8;
}
if (isread)
break;
}
if (tm >= KWSPI_TIMEOUT)
printf("*** spi_xfer: Time out during SPI transfer\n");
debug("loopend bitlen %d\n", bitlen);
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
return 0;
}

1
include/asm-arm/arch-at91/at91_common.h
View file

@ -25,6 +25,7 @@
#ifndef AT91_COMMON_H
#define AT91_COMMON_H
void at91_can_hw_init(void);
void at91_macb_hw_init(void);
void at91_serial_hw_init(void);
void at91_serial0_hw_init(void);

1
include/asm-arm/arch-at91/at91_pmc.h
View file

@ -65,6 +65,7 @@
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */

28
include/asm-arm/arch-at91/at91sam9_matrix.h Normal file
View file

@ -0,0 +1,28 @@
/*
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
#define __ASM_ARCH_AT91SAM9_MATRIX_H
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260_matrix.h>
#elif defined(CONFIG_AT91SAM9261)
#include <asm/arch/at91sam9261_matrix.h>
#elif defined(CONFIG_AT91SAM9263)
#include <asm/arch/at91sam9263_matrix.h>
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl_matrix.h>
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9_matrix.h>
#else
#error "Unsupported AT91SAM9/CAP9 processor"
#endif
#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */

167
include/asm-arm/arch-kirkwood/cpu.h Normal file
View file

@ -0,0 +1,167 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _KWCPU_H
#define _KWCPU_H
#include <asm/system.h>
#ifndef __ASSEMBLY__
#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
enum memory_bank {
BANK0,
BANK1,
BANK2,
BANK3
};
enum kwcpu_winen {
KWCPU_WIN_DISABLE,
KWCPU_WIN_ENABLE
};
enum kwcpu_target {
KWCPU_TARGET_RESERVED,
KWCPU_TARGET_MEMORY,
KWCPU_TARGET_1RESERVED,
KWCPU_TARGET_SASRAM,
KWCPU_TARGET_PCIE
};
enum kwcpu_attrib {
KWCPU_ATTR_SASRAM = 0x01,
KWCPU_ATTR_DRAM_CS0 = 0x0e,
KWCPU_ATTR_DRAM_CS1 = 0x0d,
KWCPU_ATTR_DRAM_CS2 = 0x0b,
KWCPU_ATTR_DRAM_CS3 = 0x07,
KWCPU_ATTR_NANDFLASH = 0x2f,
KWCPU_ATTR_SPIFLASH = 0x1e,
KWCPU_ATTR_BOOTROM = 0x1d,
KWCPU_ATTR_PCIE_IO = 0xe0,
KWCPU_ATTR_PCIE_MEM = 0xe8
};
/*
* Default Device Address MAP BAR values
*/
#define KW_DEFADR_PCI_MEM 0x90000000
#define KW_DEFADR_PCI_IO 0xC0000000
#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
#define KW_DEFADR_SASRAM 0xC8010000
#define KW_DEFADR_NANDF 0xD8000000
#define KW_DEFADR_SPIF 0xE8000000
#define KW_DEFADR_BOOTROM 0xF8000000
/*
* read feroceon/sheeva core extra feature register
* using co-proc instruction
*/
static inline unsigned int readfr_extra_feature_reg(void)
{
unsigned int val;
asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
(val)::"cc");
return val;
}
/*
* write feroceon/sheeva core extra feature register
* using co-proc instruction
*/
static inline void writefr_extra_feature_reg(unsigned int val)
{
asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
(val):"cc");
isb();
}
/*
* MBus-L to Mbus Bridge Registers
* Ref: Datasheet sec:A.3
*/
struct kwwin_registers {
u32 ctrl;
u32 base;
u32 remap_lo;
u32 remap_hi;
};
/*
* CPU control and status Registers
* Ref: Datasheet sec:A.3.2
*/
struct kwcpu_registers {
u32 config; /*0x20100 */
u32 ctrl_stat; /*0x20104 */
u32 rstoutn_mask; /* 0x20108 */
u32 sys_soft_rst; /* 0x2010C */
u32 ahb_mbus_cause_irq; /* 0x20110 */
u32 ahb_mbus_mask_irq; /* 0x20114 */
u32 pad1[2];
u32 ftdll_config; /* 0x20120 */
u32 pad2;
u32 l2_cfg; /* 0x20128 */
};
/*
* GPIO Registers
* Ref: Datasheet sec:A.19
*/
struct kwgpio_registers {
u32 dout;
u32 oe;
u32 blink_en;
u32 din_pol;
u32 din;
u32 irq_cause;
u32 irq_mask;
u32 irq_level;
};
/*
* functions
*/
void reset_cpu(unsigned long ignored);
unsigned char get_random_hex(void);
unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
int kw_config_adr_windows(void);
void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
unsigned int mpp16_23, unsigned int mpp24_31,
unsigned int mpp32_39, unsigned int mpp40_47,
unsigned int mpp48_55);
unsigned int kw_winctrl_calcsize(unsigned int sizeval);
#endif /* __ASSEMBLY__ */
#endif /* _KWCPU_H */

70
include/asm-arm/arch-kirkwood/kirkwood.h Normal file
View file

@ -0,0 +1,70 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Header file for the Marvell's Feroceon CPU core.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ASM_ARCH_KIRKWOOD_H
#define _ASM_ARCH_KIRKWOOD_H
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/io.h>
#endif /* __ASSEMBLY__ */
#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
#include <asm/arch/cpu.h>
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x)
#define KW_OFFSET_REG (INTREG_BASE + 0x20080)
/* undocumented registers */
#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x13000))
#define KW_MPP_BASE (KW_REGISTER(0x10000))
#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
#define KW_NANDF_BASE (KW_REGISTER(0x10418))
#define KW_SPI_BASE (KW_REGISTER(0x10600))
#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
#define KW_TIMER_BASE (KW_REGISTER(0x20300))
#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
#define KW_USB20_BASE (KW_REGISTER(0x50000))
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
#include <asm/arch/kw88f6192.h>
#else
#error "SOC Name not defined"
#endif /* CONFIG_KW88F6281 */
#endif /* CONFIG_FEROCEON_88FR131 */
#endif /* _ASM_ARCH_KIRKWOOD_H */

37
include/asm-arm/arch-kirkwood/kw88f6192.h Normal file
View file

@ -0,0 +1,37 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_KW88F6192_H
#define _CONFIG_KW88F6192_H
/* SOC specific definations */
#define KW88F6192_REGS_PHYS_BASE 0xf1000000
#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
/* TCLK Core Clock defination */
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_KW88F6192_H */

37
include/asm-arm/arch-kirkwood/kw88f6281.h Normal file
View file

@ -0,0 +1,37 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ASM_ARCH_KW88F6281_H
#define _ASM_ARCH_KW88F6281_H
/* SOC specific definations */
#define KW88F6281_REGS_PHYS_BASE 0xf1000000
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock defination*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#endif /* _ASM_ARCH_KW88F6281_H */

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/*
* linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
*
* Copyright 2009: Marvell Technology Group Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __KIRKWOOD_MPP_H
#define __KIRKWOOD_MPP_H
#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
/* MPP number */ ((_num) & 0xff) | \
/* MPP select value */ (((_sel) & 0xf) << 8) | \
/* may be input signal */ ((!!(_in)) << 12) | \
/* may be output signal */ ((!!(_out)) << 13) | \
/* available on F6180 */ ((!!(_F6180)) << 14) | \
/* available on F6190 */ ((!!(_F6190)) << 15) | \
/* available on F6192 */ ((!!(_F6192)) << 16) | \
/* available on F6281 */ ((!!(_F6281)) << 17))
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
/* num sel i o 6180 6190 6192 6281 */
#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 )
#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 )
#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 )
#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 )
#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 )
#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 )
#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 )
#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 )
#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 )
#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 )
#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 )
#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 )
#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 )
#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 )
#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 )
#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 )
#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 )
#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 )
#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 )
#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 )
#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 )
#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 )
#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 )
#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 )
#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 )
#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 )
#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 )
#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 )
#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 )
#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 )
#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 )
#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 )
#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 )
#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 )
#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 )
#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 )
#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 )
#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 )
#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 )
#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 )
#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 )
#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 )
#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 )
#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 )
#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 )
#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 )
#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 )
#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 )
#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 )
#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 )
#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 )
#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 )
#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 )
#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 )
#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 )
#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 )
#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 )
#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 )
#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 )
#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 )
#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 )
#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 )
#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 )
#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 )
#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 )
#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 )
#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 )
#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 )
#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 )
#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 )
#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 )
#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 )
#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 )
#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 )
#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 )
#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 )
#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 )
#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 )
#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 )
#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 )
#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 )
#define MPP_MAX 49
void kirkwood_mpp_conf(unsigned int *mpp_list);
#endif

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/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Derived from drivers/spi/mpc8xxx_spi.c
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __KW_SPI_H__
#define __KW_SPI_H__
/* SPI Registers on kirkwood SOC */
struct kwspi_registers {
u32 ctrl; /* 0x10600 */
u32 cfg; /* 0x10604 */
u32 dout; /* 0x10608 */
u32 din; /* 0x1060c */
u32 irq_cause; /* 0x10610 */
u32 irq_mask; /* 0x10614 */
};
#define KWSPI_CLKPRESCL_MASK 0x1f
#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
#define KWSPI_XFERLEN_1BYTE 0
#define KWSPI_XFERLEN_2BYTE (1 << 5)
#define KWSPI_XFERLEN_MASK (1 << 5)
#define KWSPI_ADRLEN_1BYTE 0
#define KWSPI_ADRLEN_2BYTE 1 << 8
#define KWSPI_ADRLEN_3BYTE 2 << 8
#define KWSPI_ADRLEN_4BYTE 3 << 8
#define KWSPI_ADRLEN_MASK 3 << 8
#define KWSPI_TIMEOUT 10000
#endif /* __KW_SPI_H__ */

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#define AIPI1_PSR0 0x10000000
#define AIPI1_PSR1 0x10000004
#define AIPI2_PSR0 0x10020000
#define AIPI2_PSR1 0x10020004
#define CSCR 0x10027000
#define MPCTL0 0x10027004
#define SPCTL0 0x1002700c
#define PCDR0 0x10027018
#define PCDR1 0x1002701c
#define PCCR0 0x10027020
#define PCCR1 0x10027024
#define ESDCTL0_ROF 0x00
#define ESDCFG0_ROF 0x04
#define ESDCTL1_ROF 0x08
#define ESDCFG1_ROF 0x0C
#define ESDMISC_ROF 0x10

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/*
*
* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
ulong imx_get_mpllclk(void);
ulong imx_get_armclk(void);
ulong imx_get_spllclk(void);
ulong imx_get_fclk(void);
ulong imx_get_hclk(void);
ulong imx_get_bclk(void);
ulong imx_get_perclk1(void);
ulong imx_get_perclk2(void);
ulong imx_get_perclk3(void);
ulong imx_get_ahbclk(void);
#endif /* __ASM_ARCH_CLOCK_H */

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/*
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _IMX_REGS_H
#define _IMX_REGS_H
#ifndef __ASSEMBLY__
extern void imx_gpio_mode (int gpio_mode);
/* AIPI */
struct aipi_regs {
u32 psr0;
u32 psr1;
};
/* System Control */
struct system_control_regs {
u32 res[5];
u32 fmcr;
u32 gpcr;
u32 wbcr;
u32 dscr1;
u32 dscr2;
u32 dscr3;
u32 dscr4;
u32 dscr5;
u32 dscr6;
u32 dscr7;
u32 dscr8;
u32 dscr9;
u32 dscr10;
u32 dscr11;
u32 dscr12;
u32 dscr13;
u32 pscr;
u32 pmcr;
u32 res1;
u32 dcvr0;
u32 dcvr1;
u32 dcvr2;
u32 dcvr3;
};
/* Chip Select Registers */
struct weim_regs {
u32 cs0u; /* Chip Select 0 Upper Register */
u32 cs0l; /* Chip Select 0 Lower Register */
u32 cs0a; /* Chip Select 0 Addition Register */
u32 pad0;
u32 cs1u; /* Chip Select 1 Upper Register */
u32 cs1l; /* Chip Select 1 Lower Register */
u32 cs1a; /* Chip Select 1 Addition Register */
u32 pad1;
u32 cs2u; /* Chip Select 2 Upper Register */
u32 cs2l; /* Chip Select 2 Lower Register */
u32 cs2a; /* Chip Select 2 Addition Register */
u32 pad2;
u32 cs3u; /* Chip Select 3 Upper Register */
u32 cs3l; /* Chip Select 3 Lower Register */
u32 cs3a; /* Chip Select 3 Addition Register */
u32 pad3;
u32 cs4u; /* Chip Select 4 Upper Register */
u32 cs4l; /* Chip Select 4 Lower Register */
u32 cs4a; /* Chip Select 4 Addition Register */
u32 pad4;
u32 cs5u; /* Chip Select 5 Upper Register */
u32 cs5l; /* Chip Select 5 Lower Register */
u32 cs5a; /* Chip Select 5 Addition Register */
u32 pad5;
u32 eim; /* WEIM Configuration Register */
};
/* SDRAM Controller registers */
struct esdramc_regs {
/* Enhanced SDRAM Control Register 0 */
u32 esdctl0;
/* Enhanced SDRAM Configuration Register 0 */
u32 esdcfg0;
/* Enhanced SDRAM Control Register 1 */
u32 esdctl1;
/* Enhanced SDRAM Configuration Register 1 */
u32 esdcfg1;
/* Enhanced SDRAM Miscellanious Register */
u32 esdmisc;
};
/* Watchdog Registers*/
struct wdog_regs {
u32 wcr;
u32 wsr;
u32 wstr;
};
/* PLL registers */
struct pll_regs {
u32 cscr; /* Clock Source Control Register */
u32 mpctl0; /* MCU PLL Control Register 0 */
u32 mpctl1; /* MCU PLL Control Register 1 */
u32 spctl0; /* System PLL Control Register 0 */
u32 spctl1; /* System PLL Control Register 1 */
u32 osc26mctl; /* Oscillator 26M Register */
u32 pcdr0; /* Peripheral Clock Divider Register 0 */
u32 pcdr1; /* Peripheral Clock Divider Register 1 */
u32 pccr0; /* Peripheral Clock Control Register 0 */
u32 pccr1; /* Peripheral Clock Control Register 1 */
u32 ccsr; /* Clock Control Status Register */
};
/*
* Definitions for the clocksource registers
*/
struct gpt_regs {
u32 gpt_tctl;
u32 gpt_tprer;
u32 gpt_tcmp;
u32 gpt_tcr;
u32 gpt_tcn;
u32 gpt_tstat;
};
/*
* GPIO Module and I/O Multiplexer
*/
#define PORTA 0
#define PORTB 1
#define PORTC 2
#define PORTD 3
#define PORTE 4
#define PORTF 5
struct gpio_regs {
struct {
u32 ddir;
u32 ocr1;
u32 ocr2;
u32 iconfa1;
u32 iconfa2;
u32 iconfb1;
u32 iconfb2;
u32 dr;
u32 gius;
u32 ssr;
u32 icr1;
u32 icr2;
u32 imr;
u32 isr;
u32 gpr;
u32 swr;
u32 puen;
u32 res[0x2f];
} port[6];
};
/* IIM Control Registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
u32 iim_err;
u32 iim_emask;
u32 iim_fctl;
u32 iim_ua;
u32 iim_la;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_prog_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
u32 res[0x1F0];
u32 iim_bank_area0[0x100];
};
#endif
#define IMX_IO_BASE 0x10000000
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
#define IMX_ESD_BASE (0xD8001000)
#define IMX_WEIM_BASE (0xD8002000)
/* FMCR System Control bit definition*/
#define UART4_RXD_CTL (1 << 25)
#define UART4_RTS_CTL (1 << 24)
#define KP_COL6_CTL (1 << 18)
#define KP_ROW7_CTL (1 << 17)
#define KP_ROW6_CTL (1 << 16)
#define PC_WAIT_B_CTL (1 << 14)
#define PC_READY_CTL (1 << 13)
#define PC_VS1_CTL (1 << 12)
#define PC_VS2_CTL (1 << 11)
#define PC_BVD1_CTL (1 << 10)
#define PC_BVD2_CTL (1 << 9)
#define IOS16_CTL (1 << 8)
#define NF_FMS (1 << 5)
#define NF_16BIT_SEL (1 << 4)
#define SLCDC_SEL (1 << 2)
#define SDCS1_SEL (1 << 1)
#define SDCS0_SEL (1 << 0)
/* important definition of some bits of WCR */
#define WCR_WDE 0x04
#define CSCR_MPEN (1 << 0)
#define CSCR_SPEN (1 << 1)
#define CSCR_FPM_EN (1 << 2)
#define CSCR_OSC26M_DIS (1 << 3)
#define CSCR_OSC26M_DIV1P5 (1 << 4)
#define CSCR_AHB_DIV
#define CSCR_ARM_DIV
#define CSCR_ARM_SRC_MPLL (1 << 15)
#define CSCR_MCU_SEL (1 << 16)
#define CSCR_SP_SEL (1 << 17)
#define CSCR_MPLL_RESTART (1 << 18)
#define CSCR_SPLL_RESTART (1 << 19)
#define CSCR_MSHC_SEL (1 << 20)
#define CSCR_H264_SEL (1 << 21)
#define CSCR_SSI1_SEL (1 << 22)
#define CSCR_SSI2_SEL (1 << 23)
#define CSCR_SD_CNT
#define CSCR_USB_DIV
#define CSCR_UPDATE_DIS (1 << 31)
#define MPCTL1_BRMO (1 << 6)
#define MPCTL1_LF (1 << 15)
#define PCCR0_SSI2_EN (1 << 0)
#define PCCR0_SSI1_EN (1 << 1)
#define PCCR0_SLCDC_EN (1 << 2)
#define PCCR0_SDHC3_EN (1 << 3)
#define PCCR0_SDHC2_EN (1 << 4)
#define PCCR0_SDHC1_EN (1 << 5)
#define PCCR0_SDC_EN (1 << 6)
#define PCCR0_SAHARA_EN (1 << 7)
#define PCCR0_RTIC_EN (1 << 8)
#define PCCR0_RTC_EN (1 << 9)
#define PCCR0_PWM_EN (1 << 11)
#define PCCR0_OWIRE_EN (1 << 12)
#define PCCR0_MSHC_EN (1 << 13)
#define PCCR0_LCDC_EN (1 << 14)
#define PCCR0_KPP_EN (1 << 15)
#define PCCR0_IIM_EN (1 << 16)
#define PCCR0_I2C2_EN (1 << 17)
#define PCCR0_I2C1_EN (1 << 18)
#define PCCR0_GPT6_EN (1 << 19)
#define PCCR0_GPT5_EN (1 << 20)
#define PCCR0_GPT4_EN (1 << 21)
#define PCCR0_GPT3_EN (1 << 22)
#define PCCR0_GPT2_EN (1 << 23)
#define PCCR0_GPT1_EN (1 << 24)
#define PCCR0_GPIO_EN (1 << 25)
#define PCCR0_FEC_EN (1 << 26)
#define PCCR0_EMMA_EN (1 << 27)
#define PCCR0_DMA_EN (1 << 28)
#define PCCR0_CSPI3_EN (1 << 29)
#define PCCR0_CSPI2_EN (1 << 30)
#define PCCR0_CSPI1_EN (1 << 31)
#define PCCR1_MSHC_BAUDEN (1 << 2)
#define PCCR1_NFC_BAUDEN (1 << 3)
#define PCCR1_SSI2_BAUDEN (1 << 4)
#define PCCR1_SSI1_BAUDEN (1 << 5)
#define PCCR1_H264_BAUDEN (1 << 6)
#define PCCR1_PERCLK4_EN (1 << 7)
#define PCCR1_PERCLK3_EN (1 << 8)
#define PCCR1_PERCLK2_EN (1 << 9)
#define PCCR1_PERCLK1_EN (1 << 10)
#define PCCR1_HCLK_USB (1 << 11)
#define PCCR1_HCLK_SLCDC (1 << 12)
#define PCCR1_HCLK_SAHARA (1 << 13)
#define PCCR1_HCLK_RTIC (1 << 14)
#define PCCR1_HCLK_LCDC (1 << 15)
#define PCCR1_HCLK_H264 (1 << 16)
#define PCCR1_HCLK_FEC (1 << 17)
#define PCCR1_HCLK_EMMA (1 << 18)
#define PCCR1_HCLK_EMI (1 << 19)
#define PCCR1_HCLK_DMA (1 << 20)
#define PCCR1_HCLK_CSI (1 << 21)
#define PCCR1_HCLK_BROM (1 << 22)
#define PCCR1_HCLK_ATA (1 << 23)
#define PCCR1_WDT_EN (1 << 24)
#define PCCR1_USB_EN (1 << 25)
#define PCCR1_UART6_EN (1 << 26)
#define PCCR1_UART5_EN (1 << 27)
#define PCCR1_UART4_EN (1 << 28)
#define PCCR1_UART3_EN (1 << 29)
#define PCCR1_UART2_EN (1 << 30)
#define PCCR1_UART1_EN (1 << 31)
/* SDRAM Controller registers bitfields */
#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
#define ESDCTL_BL (1 << 7)
#define ESDCTL_FP (1 << 8)
#define ESDCTL_PWDT(x) (((x) & 3) << 10)
#define ESDCTL_SREFR(x) (((x) & 7) << 13)
#define ESDCTL_DSIZ_16_UPPER (0 << 16)
#define ESDCTL_DSIZ_16_LOWER (1 << 16)
#define ESDCTL_DSIZ_32 (2 << 16)
#define ESDCTL_COL8 (0 << 20)
#define ESDCTL_COL9 (1 << 20)
#define ESDCTL_COL10 (2 << 20)
#define ESDCTL_ROW11 (0 << 24)
#define ESDCTL_ROW12 (1 << 24)
#define ESDCTL_ROW13 (2 << 24)
#define ESDCTL_ROW14 (3 << 24)
#define ESDCTL_ROW15 (4 << 24)
#define ESDCTL_SP (1 << 27)
#define ESDCTL_SMODE_NORMAL (0 << 28)
#define ESDCTL_SMODE_PRECHARGE (1 << 28)
#define ESDCTL_SMODE_AUTO_REF (2 << 28)
#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
#define ESDCTL_SMODE_MAN_REF (4 << 28)
#define ESDCTL_SDE (1 << 31)
#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
#define ESDCFG_TWR (1 << 15)
#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
#define ESDCFG_TWTR (1 << 20)
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
#define ESDMISC_RST (1 << 1)
#define ESDMISC_MDDREN (1 << 2)
#define ESDMISC_MDDR_DL_RST (1 << 3)
#define ESDMISC_MDDR_MDIS (1 << 4)
#define ESDMISC_LHD (1 << 5)
#define ESDMISC_MA10_SHARE (1 << 6)
#define ESDMISC_SDRAM_RDY (1 << 31)
#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
/* Clocksource Bitfields */
#define TCTL_SWR (1 << 15) /* Software reset */
#define TCTL_FRR (1 << 8) /* Freerun / restart */
#define TCTL_CAP (3 << 6) /* Capture Edge */
#define TCTL_OM (1 << 5) /* output mode */
#define TCTL_IRQEN (1 << 4) /* interrupt enable */
#define TCTL_CLKSOURCE 1 /* Clock source bit position */
#define TCTL_TEN 1 /* Timer enable */
#define TPRER_PRES 0xff /* Prescale */
#define TSTAT_CAPT (1 << 1) /* Capture event */
#define TSTAT_COMP 1 /* Compare event */
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
#define GPIO_OUT (1 << 8)
#define GPIO_IN (0 << 8)
#define GPIO_PUEN (1 << 9)
#define GPIO_PF (1 << 10)
#define GPIO_AF (1 << 11)
#define GPIO_OCR_SHIFT 12
#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
#define GPIO_AOUT_SHIFT 14
#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
#define GPIO_BOUT_SHIFT 16
#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
#define IIM_STAT_BUSY (1 << 7)
#define IIM_STAT_PRGD (1 << 1)
#define IIM_STAT_SNSD (1 << 0)
#define IIM_ERR_PRGE (1 << 7)
#define IIM_ERR_WPE (1 << 6)
#define IIM_ERR_OPE (1 << 5)
#define IIM_ERR_RPE (1 << 4)
#define IIM_ERR_WLRE (1 << 3)
#define IIM_ERR_SNSE (1 << 2)
#define IIM_ERR_PARITYE (1 << 1)
/* Definitions for i.MX27 TO2 */
#define IIM0_MAC 5
#define IIM0_SCC_KEY 11
#define IIM1_SUID 1
#endif /* _IMX_REGS_H */

61
include/asm-arm/arch-mx31/mx31-regs.h
View file

@ -61,6 +61,29 @@
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
#define WEIM_ESDCTL0 0xB8001000
#define WEIM_ESDCFG0 0xB8001004
#define WEIM_ESDCTL1 0xB8001008
#define WEIM_ESDCFG1 0xB800100C
#define WEIM_ESDMISC 0xB8001010
#define ESDCTL_SDE (1 << 31)
#define ESDCTL_CMD_RW (0 << 28)
#define ESDCTL_CMD_PRECHARGE (1 << 28)
#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
#define ESDCTL_CMD_LOADMODEREG (3 << 28)
#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
#define ESDCTL_ROW_13 (2 << 24)
#define ESDCTL_ROW(x) ((x) << 24)
#define ESDCTL_COL_9 (1 << 20)
#define ESDCTL_COL(x) ((x) << 20)
#define ESDCTL_DSIZ(x) ((x) << 16)
#define ESDCTL_SREFR(x) ((x) << 13)
#define ESDCTL_PWDT(x) ((x) << 10)
#define ESDCTL_FP(x) ((x) << 8)
#define ESDCTL_BL(x) ((x) << 7)
#define ESDCTL_PRCT(x) ((x) << 0)
#define WEIM_BASE 0xb8002000
#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
@ -84,6 +107,8 @@
#define IPU_CONF_IC_EN (1<<1)
#define IPU_CONF_SCI_EN (1<<0)
#define ARM_PPMRR 0x40000015
#define WDOG_BASE 0x53FDC000
/*
@ -179,6 +204,37 @@
#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
/* PAD control registers for SDR/DDR */
#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
/*
* Memory regions and CS
*/
@ -194,4 +250,9 @@
#define CS5_BASE 0xB6000000
#define PCMCIA_MEM_BASE 0xC0000000
/*
* NAND controller
*/
#define NFC_BASE_ADDR 0xB8000000
#endif /* __ASM_ARCH_MX31_REGS_H */

3
include/asm-arm/arch-mx31/mx31.h
View file

@ -47,4 +47,7 @@ static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
}
#endif
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
#endif /* __ASM_ARCH_MX31_H */

66
include/asm-arm/arch-nomadik/mtu.h Normal file
View file

@ -0,0 +1,66 @@
/*
* (C) Copyright 2009 Alessandro Rubini
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MTU_H
#define __ASM_ARCH_MTU_H
/*
* The MTU device hosts four different counters, with 4 set of
* registers. These are register names.
*/
#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
#define MTU_RIS 0x04 /* Raw interrupt status */
#define MTU_MIS 0x08 /* Masked interrupt status */
#define MTU_ICR 0x0C /* Interrupt clear register */
/* per-timer registers take 0..3 as argument */
#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
/* bits for the control register */
#define MTU_CRn_ENA 0x80
#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK 0x0c
#define MTU_CRn_PRESCALE_1 0x00
#define MTU_CRn_PRESCALE_16 0x04
#define MTU_CRn_PRESCALE_256 0x08
#define MTU_CRn_32BITS 0x02
#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR 0xff0
#define MTU_ITOP 0xff4
#define MTU_PERIPH_ID0 0xfe0
#define MTU_PERIPH_ID1 0xfe4
#define MTU_PERIPH_ID2 0xfe8
#define MTU_PERIPH_ID3 0xfeC
#define MTU_PCELL0 0xff0
#define MTU_PCELL1 0xff4
#define MTU_PCELL2 0xff8
#define MTU_PCELL3 0xffC
#endif /* __ASM_ARCH_MTU_H */

5
include/asm-arm/arch-omap3/cpu.h
View file

@ -84,9 +84,10 @@ typedef struct ctrl_id {
/* GPMC CS3/cs4/cs6 not avaliable */
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
#define GPMC_CONFIG_CS6 0x150
#define GPMC_CONFIG_CS5 0x150
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
#define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30

45
include/asm-arm/cache.h Normal file
View file

@ -0,0 +1,45 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
#include <asm/system.h>
/*
* Invalidate L2 Cache using co-proc instruction
*/
static inline void invalidate_l2_cache(void)
{
unsigned int val=0;
asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
: : "r" (val) : "cc");
isb();
}
void l2_cache_enable(void);
void l2_cache_disable(void);
#endif /* _ASM_CACHE_H */

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